From 3cf966f8c0460b30bcd15dac3137d55cc6bbd895 Mon Sep 17 00:00:00 2001
From: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Date: Fri, 22 Sep 2023 14:54:23 -0700
Subject: [PATCH] ARM: dts: msm: Add a node for gclk cycle counter driver

Add gclk cycle counter register information to devicetree in a
separate node for use by associated driver.

Change-Id: Ie27724dc04703d496a652729d61e03e0f4ff0115
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
---
 qcom/sun-walt.dtsi | 20 ++++++++++++++++++++
 qcom/sun.dtsi      |  1 +
 2 files changed, 21 insertions(+)
 create mode 100644 qcom/sun-walt.dtsi

diff --git a/qcom/sun-walt.dtsi b/qcom/sun-walt.dtsi
new file mode 100644
index 00000000..05e6ce34
--- /dev/null
+++ b/qcom/sun-walt.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	walt {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom,cycle-cntr {
+			compatible = "qcom,gclk";
+			reg = <0x18880400 0x8>,
+				<0x19880400 0x8>;
+			reg-names = "freq-domain0",
+				"freq-domain1";
+		};
+	};
+};
diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index daaacaf5..c3e1026b 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -3154,6 +3154,7 @@
 #include "sun-thermal.dtsi"
 #include "sun-pcie.dtsi"
 #include "msm-rdbg.dtsi"
+#include "sun-walt.dtsi"
 
 &qupv3_se7_2uart {
 	status = "ok";