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ARM: dts: msm: reserve memory region for splash and ramdump

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Reserves memory region to enable continuous splash
and ramdump on tuna target.

Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326
Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
Sailesh Reddy Male
2025-01-03 12:24:22 +05:30
committed by lnxdisplay
parent e8ba29204b
commit 3253c6e1ea
2 changed files with 15 additions and 2 deletions
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14
display/kera-sde-display.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <dt-bindings/clock/qcom,dispcc-tuna.h> #include <dt-bindings/clock/qcom,dispcc-tuna.h>
@@ -14,6 +14,18 @@
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk"; clock-names = "mdp_core_clk";
}; };
disp_rdump_memory: disp_rdump_region@0xfc800000 {
reg = <0xfc800000 0x00800000>;
label = "disp_rdump_region";
};
};
&reserved_memory {
splash_memory: splash_region {
reg = <0x0 0xFC800000 0x0 0x02B00000>;
label = "cont_splash_region";
};
}; };
&sde_dsi { &sde_dsi {

3
display/kera-sde.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause // SPDX-License-Identifier: BSD-3-Clause
/* /*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
@@ -183,6 +183,7 @@
smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
<&smmu_sde_unsec 0xFC800000 0x02B00000>,
<&smmu_sde_sec 0x0 0x00020000>; <&smmu_sde_sec 0x0 0x00020000>;
}; };