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Merge 817e906297 on remote branch

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Change-Id: I923285d5405a3450cae83c3ee32595e885894b96
This commit is contained in:
Linux Build Service Account
2025-01-04 13:38:11 -08:00
parent 47ed6ef3f9 817e906297
commit 192a39f39a
7 changed files with 150 additions and 7 deletions
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27
bindings/mdss-dsi-panel.yaml
View File

@@ -543,6 +543,12 @@ properties:
"constant-fps-adjust-vfp" = FPS is maintained even after
dynamic clock switch by changing panel vertical front
porch values.
"adjust-hfp" = Dynamic clock switch is achieved by adjusting the
horizontal front porch value according to the qcom,dsi-dyn-hfp-list.
FPS may not be maintained after the switch.
"adjust-vfp" = Dynamic clock switch is achieved by adjusting the
vertical front porch value according to the qcom,dsi-dyn-vfp-list.
FPS may not be maintatined after the switch.
This dyn-clk-type entry is an optional binding which is
contingent on the enabling of dynamic clock switch.
$ref: /schemas/types.yaml#/definitions/string-array
@@ -1713,6 +1719,24 @@ properties:
order of preference.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,dsi-dyn-clk-hfp-list:
description: >
An u32 array of horizontal front porch values corresponding to the
dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode.
This property is essential for the adjust-hfp dynamic clock type,
which is used for specific horizontal porch adjustments when maintaining
a constant frame rate is not required.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,dsi-dyn-clk-vfp-list:
description: >
An u32 array of vertical front porch values corresponding to the
dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode.
This property is essential for the adjust-vfp dynamic clock type,
which is used for specific horizontal porch adjustments when maintaining
a constant frame rate is not required.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,disable-rsc-solver:
description: >
Timing node property to dynamically disable RSC solver for
@@ -1908,7 +1932,7 @@ examples:
qcom,platform-reset-gpio = <&tlmm 0 0>;
qcom,dsi-dyn-clk-enable;
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
qcom,dsi-dyn-clk-type = "adjust-hfp";
qcom,mdss-dsi-display-timings {
wqhd {
@@ -1988,6 +2012,7 @@ examples:
qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode";
qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>;
qcom,dsi-dyn-clk-hfp-list = <52 64 96>;
qcom,vert-padding-value = <2940>;
qcom,mdss-dsc-slice-height = <16>;

6
display/kera-sde-common.dtsi
View File

@@ -13,11 +13,13 @@
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x400000 0x2000>;
<0x400000 0x2000>,
<0x0af50000 0x140>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"ipcc_reg";
"ipcc_reg",
"swfuse_phys";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

2
display/kera-sde.dtsi
View File

@@ -228,7 +228,7 @@
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys";
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,

6
display/tuna-sde-common.dtsi
View File

@@ -13,11 +13,13 @@
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x400000 0x2000>;
<0x400000 0x2000>,
<0x0af50000 0x140>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"ipcc_reg";
"ipcc_reg",
"swfuse_phys";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

62
display/tuna-sde-display-cdp.dtsi
View File

@@ -5,6 +5,49 @@
#include "tuna-sde-display.dtsi"
&pm8550vs_g_gpios {
lcd_backlight_ctrl {
lcd_backlight_en_default: lcd_backlight_en_default {
pins = "gpio4";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <1>;
qcom,drive-strength = <3>;
};
};
};
&pm8550vs_f_gpios {
display_panel_avdd_default: display_panel_avdd_default {
pins = "gpio8";
function = "normal";
input-disable;
output-enable;
bias-disable;
power-source = <1>;
qcom,drive-strength = <3>;
};
};
&soc {
display_panel_avdd: display_gpio_regulator@1 {
compatible = "qti-regulator-fixed";
regulator-name = "display_panel_avdd";
regulator-min-microvolt = <5500000>;
regulator-max-microvolt = <5500000>;
regulator-enable-ramp-delay = <233>;
gpio = <&pm8550vs_f_gpios 8 0>;
enable-active-high;
regulator-boot-on;
proxy-supply = <&display_panel_avdd>;
qcom,proxy-consumer-enable;
pinctrl-names = "default";
pinctrl-0 = <&display_panel_avdd_default>;
};
};
&dsi_vtdr6130_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
@@ -216,6 +259,24 @@
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sharp_qhd_plus_dsc_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>;
};
&dsi_sharp_qhd_plus_dsc_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
@@ -257,6 +318,7 @@
};
&sde_dsi {
avdd-supply = <&display_panel_avdd>;
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};

52
display/tuna-sde-display-common.dtsi
View File

@@ -18,6 +18,8 @@
#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi"
#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi"
#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi"
#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi"
#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi"
#include "dsi-panel-sim-cmd-au.dtsi"
#include "dsi-panel-sim-cmd.dtsi"
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
@@ -88,6 +90,30 @@
};
};
dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd {
#address-cells = <1>;
#size-cells = <0>;
qcom,panel-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vddio";
qcom,supply-min-voltage = <1800000>;
qcom,supply-max-voltage = <1800000>;
qcom,supply-enable-load = <220000>;
qcom,supply-disable-load = <8000>;
qcom,supply-post-on-sleep = <20>;
};
qcom,panel-supply-entry@1 {
reg = <1>;
qcom,supply-name = "avdd";
qcom,supply-min-voltage = <4600000>;
qcom,supply-max-voltage = <6000000>;
qcom,supply-enable-load = <260000>;
qcom,supply-disable-load = <100>;
};
};
sde_dsi: qcom,dsi-display-primary {
compatible = "qcom,dsi-display";
label = "primary";
@@ -713,6 +739,32 @@
};
};
&dsi_sharp_qhd_plus_dsc_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07
07 07 02 04 00 17 0c];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sharp_qhd_plus_dsc_video {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
qcom,mdss-dsi-display-timings {
timing@0 { /* 120 FPS */
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07
07 07 02 04 00 17 0c];
qcom,display-topology = <2 2 2>;
qcom,default-topology-index = <0>;
};
};
};
&dsi_sim_cmd {
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";

2
display/tuna-sde.dtsi
View File

@@ -270,7 +270,7 @@
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys";
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,