From 1fbdd896c40bf1f1c6ec5e014b1e9557c7ea35c7 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 24 Oct 2024 11:09:38 +0530 Subject: [PATCH 01/10] ARM: dts: msm: Enable DP for Tuna CDP, QRD, and MTP platforms Enable DP support for MTP Harmonium, QRD, and CDP platforms for Tuna. Change-Id: I1cf8ff5a64f2d71df8e3247679ed03625aedee44 Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: Ritesh Kumar Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 8 ++++++++ display/tuna-sde-display-mtp-kiwi-harmonium.dtsi | 8 ++++++++ display/tuna-sde-display-qrd.dtsi | 8 ++++++++ display/tuna-sde.dtsi | 7 ++++--- 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index cbc2df0f..e18d17f2 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -260,6 +260,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_i2c { st_fts@49 { panel = <&dsi_nt37801_amoled_cmd diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index a4b9235b..afb97cbc 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -4,3 +4,11 @@ */ #include "tuna-sde-display-mtp.dtsi" + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 13de5d6f..0598d2ac 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -125,6 +125,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_spi { st_fts@0 { panel = <&dsi_nt37801_amoled_cmd_cphy diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 79fb22e3..2387ccee 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -34,10 +34,11 @@ compatible = "qcom,dp-display"; status = "disabled"; - //usb-phy = <&usb_qmp_dp_phy>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -104,7 +105,7 @@ vdda-1p2-supply = <&L4B>; vdda-0p9-supply = <&L3B>; vdda_usb-0p9-supply = <&L3B>; - //vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, @@ -133,7 +134,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <30000>; qcom,supply-disable-load = <0>; }; From 93cee5f4cbc95d0c7626127af8ac89a651be750b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 25 Nov 2024 11:55:48 +0530 Subject: [PATCH 02/10] ARM: dts: msm: update dsi supply voltage for kera Update DSI and panel supply voltage configuration as per the recent change in the supplier regulators for Kera. Change-Id: I512d381d4bf7e0a6b0d171736af872c7f45eeb74 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 4 ++-- display/kera-sde-display-common.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index b3621384..53bd54c2 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -346,7 +346,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -372,7 +372,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index f6710815..8fec279c 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -48,7 +48,7 @@ reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <2000000>; + qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <220000>; qcom,supply-disable-load = <8000>; qcom,supply-post-on-sleep = <20>; From 2c8658563ea6ca61d95cdafcd24a362845da2490 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 11 Nov 2024 12:04:28 +0530 Subject: [PATCH 03/10] ARM: dts: msm: add display node in trustedvm platform This change adds display node in trustedvm platform on Kera target. Change-Id: Ibe2c60bcb34bdedee75f7b8fa163a8aacb204562 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-kera-sde-display.dtsi | 2 +- display/trustedvm-kera-sde.dtsi | 37 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi index e6420a52..8ec7d0f1 100644 --- a/display/trustedvm-kera-sde-display.dtsi +++ b/display/trustedvm-kera-sde-display.dtsi @@ -24,5 +24,5 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; }; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 9b88fd38..3740746b 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -8,9 +8,46 @@ #include "kera-sde-common.dtsi" &soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; }; &mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0xC0040000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From ef1f3c4062fcf51f3afc371b9ac6d876b4968f4f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Sat, 23 Nov 2024 18:50:16 +0530 Subject: [PATCH 04/10] ARM: dts: msm: enable compilation for kera trustedvm platforms Enable compilation for kera trustedvm platforms. Change-Id: I7f05e7e7d6f245707db30e6315ff5cb46e1438f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Kbuild b/Kbuild index 3c212c66..31654078 100644 --- a/Kbuild +++ b/Kbuild @@ -57,6 +57,13 @@ dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ display/kera-sde-display-qrd-overlay.dtbo \ display/kera-sde-display-rumi-overlay.dtbo \ display/kera-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-kera-sde-display-atp-overlay.dtbo \ + display/trustedvm-kera-sde-display-cdp-overlay.dtbo \ + display/trustedvm-kera-sde-display-mtp-overlay.dtbo \ + display/trustedvm-kera-sde-display-qrd-overlay.dtbo \ + display/trustedvm-kera-sde-display-rumi-overlay.dtbo \ + display/trustedvm-kera-sde-display-rcm-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) From c56ffa64e79e8270a0ea56f9fb40c602555676cb Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 2 Dec 2024 17:22:01 +0530 Subject: [PATCH 05/10] ARM: dts: msm: update UBWC HBB configuration for kera This change updates UBWC highest bank bit configuration for kera target. Change-Id: Ie0ef2bea85d9e2ce542cef4fa3de97ccf93596a0 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index 53bd54c2..c54b3b69 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -150,7 +150,8 @@ qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-wb-linewidth-linear = <8192>; qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x8 0x2>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; qcom,sde-ubwc-version = <0x40000000>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; From 78a57f6b4d5eb2f884c5e8a000b4a6162781c74d Mon Sep 17 00:00:00 2001 From: Srihitha Tangudu Date: Mon, 25 Nov 2024 11:53:03 +0530 Subject: [PATCH 06/10] ARM: dts: msm: dynamic clock switch with specific HFP/VFP adjustment Add new dynamic clock types "adjust-hfp" and "adjust-vfp" to facilitate specific hfp/vfp adjustment as per "qcom,dsi-dyn-hfp-list" and "qcom,dsi-dyn-vfp-list" respectively corresponding to bit clock rates of "qcom,dsi-dyn-clk-list". FPS might not be maintained in these cases. Change-Id: Ic225624fb5e0bee0d8b099f2e955f65768371d4b Signed-off-by: Srihitha Tangudu Signed-off-by: lnxdisplay --- bindings/mdss-dsi-panel.yaml | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml index 20ae28ff..accf1822 100644 --- a/bindings/mdss-dsi-panel.yaml +++ b/bindings/mdss-dsi-panel.yaml @@ -543,6 +543,12 @@ properties: "constant-fps-adjust-vfp" = FPS is maintained even after dynamic clock switch by changing panel vertical front porch values. + "adjust-hfp" = Dynamic clock switch is achieved by adjusting the + horizontal front porch value according to the qcom,dsi-dyn-hfp-list. + FPS may not be maintained after the switch. + "adjust-vfp" = Dynamic clock switch is achieved by adjusting the + vertical front porch value according to the qcom,dsi-dyn-vfp-list. + FPS may not be maintatined after the switch. This dyn-clk-type entry is an optional binding which is contingent on the enabling of dynamic clock switch. $ref: /schemas/types.yaml#/definitions/string-array @@ -1713,6 +1719,24 @@ properties: order of preference. $ref: /schemas/types.yaml#/definitions/uint32-array + qcom,dsi-dyn-clk-hfp-list: + description: > + An u32 array of horizontal front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-hfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-dyn-clk-vfp-list: + description: > + An u32 array of vertical front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-vfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + qcom,disable-rsc-solver: description: > Timing node property to dynamically disable RSC solver for @@ -1908,7 +1932,7 @@ examples: qcom,platform-reset-gpio = <&tlmm 0 0>; qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,dsi-dyn-clk-type = "adjust-hfp"; qcom,mdss-dsi-display-timings { wqhd { @@ -1988,6 +2012,7 @@ examples: qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + qcom,dsi-dyn-clk-hfp-list = <52 64 96>; qcom,vert-padding-value = <2940>; qcom,mdss-dsc-slice-height = <16>; From ce0c7bb029e58e081495392bd318ddc6d13032d0 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Wed, 4 Dec 2024 15:43:19 +0530 Subject: [PATCH 07/10] ARM: dts: msm: add support for sw fuse for Kera target Add sw fuse range to dts file for Kera target. The swfuse_phys is only needed in primary VM. Change-Id: If8e58f86f15960633c2e058342d15c307dcc738c Signed-off-by: Sanskar Omar Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 6 ++++-- display/kera-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index c54b3b69..a2822e3e 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x140>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index b18d8140..22362ce2 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -228,7 +228,7 @@ qti,smmu-proxy-cb-id = ; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From 165cb0eb23cd111b66c09db1662708fd0a09a894 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Wed, 4 Dec 2024 15:29:42 +0530 Subject: [PATCH 08/10] ARM: dts: msm: add support for sw fuse for Tuna target Add sw fuse range to dts file for Tuna target. The swfuse_phys is only needed in primary VM. Change-Id: Ida97d23c3f0634864829ea8f7ea91e388062eb4c Signed-off-by: Sanskar Omar Signed-off-by: lnxdisplay --- display/tuna-sde-common.dtsi | 6 ++++-- display/tuna-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index e2a5d2f5..e3098929 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x140>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 2387ccee..6567fb17 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -231,7 +231,7 @@ qti,smmu-proxy-cb-id = ; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From 33b1c55941c4e1b31d2a2db6e35abec50827b6f0 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Tue, 19 Nov 2024 19:53:06 +0530 Subject: [PATCH 09/10] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: Ia50ffd92a35f13219877a73698ca6defa28dd2de Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/tuna-sde-display.dtsi | 12 ++++++++++++ display/tuna-sde.dtsi | 1 + 2 files changed, 13 insertions(+) diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index a3568aac..ce534cc8 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -22,6 +22,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 6567fb17..f9db998d 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 817e9062974d35c8283c997a476cbce9483407fd Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 2 Dec 2024 13:51:33 +0530 Subject: [PATCH 10/10] ARM: dts: msm: Add display support for Sharp qhd+ panel on Tuna CDP Add display support for Sharp qhd+ panel on Tuna CDP platform. Change-Id: I58a4bccc33cba4a2e471a24c3dfc25c6608a010c Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 62 ++++++++++++++++++++++++++++ display/tuna-sde-display-common.dtsi | 52 +++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index e18d17f2..2827224b 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,49 @@ #include "tuna-sde-display.dtsi" +&pm8550vs_g_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio4"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550vs_f_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio8"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550vs_f_gpios 8 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -216,6 +259,24 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -257,6 +318,7 @@ }; &sde_dsi { + avdd-supply = <&display_panel_avdd>; qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index beb59396..168db297 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -18,6 +18,8 @@ #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-dsc-10bit-cmd.dtsi" @@ -88,6 +90,30 @@ }; }; + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -713,6 +739,32 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";