Vishvanath Singh d5c176fe3b ARM: dts: msm: Fake UFS Ref clock to run on HS mode ...

Change-Id: I0045b2df13f1d6e6bcf0e4ee5c5553a7c0560807

Signed-off-by: Vishvanath Singh <quic_vishvana@quicinc.com>

2024-12-29 01:10:07 -08:00

bindings

dt-bindings: clock: qcom: add the DISPCC binding for kera

2024-12-27 23:21:37 +05:30

qcom

ARM: dts: msm: Fake UFS Ref clock to run on HS mode

2024-12-29 01:10:07 -08:00

BUILD.bazel

ARM: dts: msm: Add initial device trees for Sun SoC

2023-04-03 11:54:34 -07:00

Makefile

ARM: dts: msm: Add initial device trees for Sun SoC

2023-04-03 11:54:34 -07:00

Description

No description provided

11 MiB

Languages

Makefile 81.1%

Starlark 18.9%