Add ufs support for mtp/cdp/qrd sun platforms.
Enable ufs's smmu fastmap attribute.
Enable ufs host and device resets.
Change-Id: I7e4194a48c022284308c3debd6e18be40289693b
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add nodes to enable qcom dcvs, bwmon and memlat
on sun.
Change-Id: I515aa98f01b29fb51be11db33930f96193d13401
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add nodes to enable scmi communication to cpucp on sun.
Change-Id: I574949e32e397047701f836d54115f56414ea023
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add carved-out memory region used for hw-fencing on sun target.
Change-Id: I0aaba5a8a55de2e5b625667973841d90f3f9de3a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
Describe the available dma-buf memory pools on sun-vm.
Change-Id: I205b826849f36078d05a92492238d80a884aa65a
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the register, interrupts, and settings of the arm-smmu device.
Change-Id: I0ca4c90e2f767ed6240dd6ad6fc6cc8e7f6c278d
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
This change adds system low power violators device node.
Change-Id: Ie4b7923c2ef96d6d762275b7241948e120230163
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Snapshot the sys-pm-violators documentation from
qcom-6.1 'commit <16ac1827ff37> ("bindings: arm: msm:
Add sys-pm-violators bindings for monaco_au")'.
Updates:
- Add entry to support for sun.
Change-Id: I1a8cd4652b6680ff4b87199a6fc22b1ddbcd9614
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add initial device trees to support Sun QRD sku1 and sku2 SoC
and it's platforms.
Change-Id: Ibf28cbc9f33f19908c4d8ac1b431d17632c43e6b
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Remove fixed-factor-clock and enable device node for rpmh
clocks under apps_rsc in place of fixed clocks.
Change-Id: I9c4d242882f29f616574e339581722b65f27a74f
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
Add RPMH_CXO_CLK as ref_clk to UFS for Sun on pre-sil.
On Rumi ref_clk is to UFS PHY is 19.2MHz and actual device
it is 38.4MHz.
Also update correct gcc header file for sun.
Change-Id: I78ed60095e5229405e7962f4676bfab7b7556676
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Describe the properties of the memory region virtio-mem supports.
Change-Id: Ifdc420d25c4fcf1acc93ccd82a80c89857b3c427
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the message queues and capabilities of the mem-buf device.
Change-Id: I9ff137c3cfee8d5f9e56930bf8ca9a81066e0150
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add gh-msgq-test binding description and requirements which include
compatible, label and optional properties.
Change-Id: Ie894c1ca2179c9fed9b066893de03eff60749c81
Signed-off-by: Po-Jung Lai <quic_pojulai@quicinc.com>
Add DT bindings for SPI which provides the resource management details
for the SPI geni msm driver.
Change-Id: Ifcaccf747ee2efe41fba6d77660456916dcc099b
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
Add device_type property for the pcie devicetree nodes
in sun.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add device_type property for the pcie devicetree nodes
in pineapple.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I212e023880ed8373eb17379754da84b6947d1171
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add ON Semiconductor USB Type-C and display port 10Gbps Linear Re-Driver
bindings used on MSM platforms.
Change-Id: Ia333a63a958a5a890f2743a3ec6dc51d7053b720
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
Add DT bindings for I2C which provides the resource management details
for the I2C geni msm driver.
Change-Id: I2bc39bf86e0760db595cd2a17e7c1fc6ee1f98cf
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
This snapshot is taken from qcom-6.1 commit 5e1de6591957
("dt-bindings: IMEM: add binding for Modem DSM region").
Change-Id: Ie0af47ef3d0957ae3537a3b97912eaa85275bd86
Signed-off-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
Update enable-method to PSCI. Add idle-states node and
update cpu node to include appropriate idle state.
Disabled all idle-states for rumi.
Change-Id: I313d52c60081ef1d568781e33d0f2fed1a1f2de4
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Add a regulator over-current (OCP) notifier device along with
supply properties to map from PMIC peripherals to specific
regulator devices. This provides a mechanism to notify
consumers of a particular regulator when OCP occurs.
Change-Id: I17ee6af65492ece062722c41f97f3ea052970a25
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add a fixed regulator device for the DBO3 buck-boost regulator.
It is enabled via PM8550 GPIO 9 and outputs 3.6 V.
Change-Id: Iff6e0e1cceed6ad369fb67aca3926f5a808cf3e6
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
