Add ACD values for supported voltage levels for Sun GPU.
Change-Id: I8361f4026afbf05ba26860307ffc7158b55b8d2f
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add supporting power levels for AB and AC sku devices.
Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Signed-off-by: Vaishali Gupta <quic_vai@quicinc.com>
Add supporting power levels for AB and AC sku devices.
Change-Id: I233a5779a78cdc22883e1ed8b9b02c73aa0f576d
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
SVS is the highest voltage corner for GMU. The lowest DDR BW
that puts CX at SVS corner is 1555 MHz. This DDR vote puts CX
at a corner high enough such that GMU can run at 650 MHz. This
is to get better GMU performance at no extra power cost.
Change-Id: I919476577e9b2e69161142c93d47e91505ffc222
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
For gen8 targets, frequency limiter violations are published
through cx_host_irq interrupt. Thus, add cx_host_irq for sun
GPU.
Change-Id: Ie7e0c7fc53bdc002261ee05339c3e4c49da83ea0
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Hardware fence feature requires that we keep soccp from power collapsing
as long as GMU is active.
Change-Id: I3721aefd8cb34edfeba846115132002defa8f385
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
This is needed to vote for soccp boot/slumber sequence for
hardware fence feature.
Change-Id: I169d83ed9d5acf66027194bf5fee0825bb5602d2
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>
KGSL driver doesn't program PDC registers anymore.
Thus, remove the register information from device
tree for sun GPU.
Change-Id: I60c78e00942bb68e311b4c4632e5a3e2ed30dcd6
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
Add support for sunp variant msm-id.
Change-Id: I3dee70f03e360330636290ef665aced0b4f31542
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
GDSCs can be modeled as power domain on newer GPUs. This
property provides an option to specify the GDSCs as power
domain.
Change-Id: I2f687b9339accaad701737ccfaf5e41209201229
Signed-off-by: Kamal Agrawal <quic_kamaagra@quicinc.com>
QDSS clock is used in kgsl to program ISDB registers. Add the clock so
that kgsl can vote for it when needed.
Change-Id: I2b71bdc4b9884409c598ba20759c56bff12cdb64
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Add intermediate supported power levels for GPU and remove unsupported
power levels from the list.
Change-Id: Ie16c06293dc707561f03aa9f1839a8217f163726
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Enable Sun GPU to perform graphics functionality.
Also add ipc-core property for hwfences support.
Change-Id: Ia01d92e4b2d43a1f8ec24ff63768aab5d7a4e1e3
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
Add the devicetree files for the GPU on Sun devices.
Change-Id: Iaf7a19eb5e2c6c215e838ae1bfa3b01916c804d9
Signed-off-by: Hareesh Gundu <quic_hareeshg@quicinc.com>
