Update the compatible string of evacc for sun
v2 platform.
Change-Id: I3701aa5031cfb0568f9b8f3cf10e3ec499b270bf
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Add eva clock controller bindings on SUN v2 device.
Change-Id: I31b74f282031cfd2e081973e705d678d39e84832
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Add boot_device_type support and flag non-removable
for ufs node to check if the boot device is emmc or ufs.
Remove qcom,ufs-dev-revert to identify ufs device Version.
Change-Id: Id9e925d78860c4518ab10c12cc628dd8b385a5e8
Signed-off-by: kamasali Satyanarayan <quic_kamasali@quicinc.com>
Remove SDPM clock driver support from clarence gaming.
Remove cpu pause action on boot core.
Add cold temperature interrupt handling support in clarence.
Change-Id: I05da43e8a8e392f2bec8f425ac9750f559221953
Signed-off-by: Nitesh Kumar <quic_nitekuma@quicinc.com>
Add support for ice wrapped keys to the MMC DTSI entry
on parrot targets.
Change-Id: Ia818b700bfd2d7f117e90f0d1d1fdc2befe10cce
Signed-off-by: Seshu Madhavi Puppala <quic_spuppala@quicinc.com>
Add the TLMM GPIO reserved ranges for the sdxkova platform.
The reserved range is set to <110 6> to ensure proper
allocation and avoid conflicts with other GPIOs.
Change-Id: I6b01f9c6a21f918df078dcbe078be602dd889898
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Update the compatible string of cambistmclkcc for SUN v2
platform.
Change-Id: I5a984c8ea24308fbe39c4e84e61cc38891e1f7eb
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
Newly added optional quirk "qcom,sleep-clk-bcr" adds delay of
200-250us after deasserting the USB3 BCR. This is needed on
some targets where sleep clk is used for BCR demet.
Change-Id: I88370838c29f679f2d2d90f565d3884d48bcdff2
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Set RX settings mode to zero for Ultrashort channel
settings for sun PCIe controller.
Change-Id: I50b7896e6dabb2cda069c9242340dee02a225b8c
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Add idle states for CPUs and CPU clusters, added PSCI device,
to enable CPUs to enter deeper LPMs.
Disabled the idle states till Rumi validations are done.
Additionally. updated APPS RSC device to be in cluster power domain
to handle RSC activities when cluster is powering off.
Change-Id: I0dc50ff04bb480eb9ebdfa0bbaebfdf954c7c41b
Signed-off-by: Sneh Mankad <quic_smankad@quicinc.com>
The tui_test heap will be used by the large_dmabuf test
on sun-vm.
Change-Id: I84e5aee85c03e2cc809acc307509ce00aa74d967
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
When all clients remove DDR bandwidth vote, DDR may power collapse.
As part of its shutdown sequence, it waits for an 'active' signal to
no longer be asserted by the gpu cx gdsc. Thus, if SW votes for the
gdsc to be active, but not for DDR bandwidth, this sequence may
get stuck.
Change-Id: I48d704f08cfe6d17159eb04d02f5ed123809f967
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
APPS needs to place proxy votes to ddr and cnoc when the SOCCP is in D0.
Change-Id: Idfa93910b51c6df033ea010480c1a8adeacd4af5
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SOCCP_SOCCP_SPARE_REG0 is used to check D0 status of SOCCP.
TCSR_SOCCP_SLEEP_STATUS is used to check D3 status of SOCCP.
Change-Id: Icee37cddb0b7ef303962cab0d9a8f37a211a05da
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Bindings file for WALT cycle counter driver is in incorrect location.
Move it to the correct location where all other bindings files are
present.
Change-Id: I9e8ef0a87ac6b311931535a82ccf3c784bcdc896
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
Parrot need to follow non-relocatable absolute addresses for VM due to
firmware constraints. VM kernel load address is the start address of the
vm_mem_region and build system requires the load address of the kernel
to be 2MB aligned.
This patch adjusts the start address of the trust_ui_vm_mem region for
Parrot to align to 2MB. This also means reducing its size by 1MB.
Change-Id: I1816ec5f6ff18f55ecc4dec39958d442151f8cb0
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
Binding document to support MPAM(Memory System Resource Partitioning
and Monitoring) MSC(Memory System Component) interface framework added
to support multiple MSC components. Currently SLC(System Level Cache)
MSC support integrated to MSC interface with API support to configure
SLC Capacity and monitors.
Change-Id: I866b0e8cd6106f86535baf004d25e81e406e3e12
Signed-off-by: Avinash Philip <quic_avinashp@quicinc.com>
