These clock phandles are necessary to ensure the clock devices probe
before debugcc. Debugcc needs its parent clock devices to probe first,
otherwise it'll invalidate their associated mux_sels during
clk_debug_mux_init() and they can't be measured.
Change-Id: I30d1a9e24ae1ac5a9efc7d8f8e0740ebdce8e1b0
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Add the missing phy gdsc node in the pcie dt node for sun.
Change-Id: I0257c6123d4d3e8fe2740569bd4def68fa3c92a8
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add PMIC Glink devices and their client devices. The PMIC Glink
device with name PMIC_RTR_ADSP_APPS supports the clients: ucsi,
altmode, and battery_charger. The PMIC Glink device with name
PMIC_LOGS_ADSP_APPS supports the clients: battery_debug,
pmic_glink_debug, charger_ulog_glink, and glink_adc.
Change-Id: Ib5a15c136c77c8368d4a561f266a1588c4649893
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Describe the communication channel used to communicate with the
firmware which supports onlining and offlining of memory.
Keep the device in a disabled state for now until a conflict
between THP and memory-hotplug features can be resolved.
Change-Id: I3d74d9d3d58d379b2a91ee976a72dddfb7a221c6
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
PMIC5 GEN3 ADC has support for clients to read voltage and
current on supported channels connected to the PMIC.
Clients include reading voltage phone power and on board system
thermistors for thermal management. ADCs on certain PMICs have
support to read battery current.
Change-Id: Ief7cbdf77d227ba2cb4ef7919aa66d9962d98e37
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
[quic_amelende@quicinc.com: Converted binding change from .txt to .yaml]
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add ufs support for mtp/cdp/qrd sun platforms.
Enable ufs's smmu fastmap attribute.
Enable ufs host and device resets.
Change-Id: I7e4194a48c022284308c3debd6e18be40289693b
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add nodes to enable qcom dcvs, bwmon and memlat
on sun.
Change-Id: I515aa98f01b29fb51be11db33930f96193d13401
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add nodes to enable scmi communication to cpucp on sun.
Change-Id: I574949e32e397047701f836d54115f56414ea023
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add carved-out memory region used for hw-fencing on sun target.
Change-Id: I0aaba5a8a55de2e5b625667973841d90f3f9de3a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
Describe the available dma-buf memory pools on sun-vm.
Change-Id: I205b826849f36078d05a92492238d80a884aa65a
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the register, interrupts, and settings of the arm-smmu device.
Change-Id: I0ca4c90e2f767ed6240dd6ad6fc6cc8e7f6c278d
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
This change adds system low power violators device node.
Change-Id: Ie4b7923c2ef96d6d762275b7241948e120230163
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Snapshot the sys-pm-violators documentation from
qcom-6.1 'commit <16ac1827ff37> ("bindings: arm: msm:
Add sys-pm-violators bindings for monaco_au")'.
Updates:
- Add entry to support for sun.
Change-Id: I1a8cd4652b6680ff4b87199a6fc22b1ddbcd9614
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add initial device trees to support Sun QRD sku1 and sku2 SoC
and it's platforms.
Change-Id: Ibf28cbc9f33f19908c4d8ac1b431d17632c43e6b
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Remove fixed-factor-clock and enable device node for rpmh
clocks under apps_rsc in place of fixed clocks.
Change-Id: I9c4d242882f29f616574e339581722b65f27a74f
Signed-off-by: Xubin Bai <quic_xubibai@quicinc.com>
Add RPMH_CXO_CLK as ref_clk to UFS for Sun on pre-sil.
On Rumi ref_clk is to UFS PHY is 19.2MHz and actual device
it is 38.4MHz.
Also update correct gcc header file for sun.
Change-Id: I78ed60095e5229405e7962f4676bfab7b7556676
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Describe the properties of the memory region virtio-mem supports.
Change-Id: Ifdc420d25c4fcf1acc93ccd82a80c89857b3c427
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Describe the message queues and capabilities of the mem-buf device.
Change-Id: I9ff137c3cfee8d5f9e56930bf8ca9a81066e0150
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add gh-msgq-test binding description and requirements which include
compatible, label and optional properties.
Change-Id: Ie894c1ca2179c9fed9b066893de03eff60749c81
Signed-off-by: Po-Jung Lai <quic_pojulai@quicinc.com>
Add DT bindings for SPI which provides the resource management details
for the SPI geni msm driver.
Change-Id: Ifcaccf747ee2efe41fba6d77660456916dcc099b
Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com>
Add device_type property for the pcie devicetree nodes
in sun.
This is needed to make sure that the pcie devicetree node
is associated with the pci bus when ranges property gets
parsed by the of/address.c driver.
And this change is mandatory for pci devicetree nodes with
the introduction of the following change in of/address.c
upstream commit <3d5089c4263d> "of/address: Add support
for 3 address cell bus".
Without this change, BAR address allocation failure will
happen as error logs below as the flags cell in ranges
property in devicetree will be read wrong.
pci-msm 1c00000.qcom,pcie:err 0x0060200000..0x00602fffff -> 0x0060200000.
pci-msm 1c00000.qcom,pcie:err 0x0060300000..0x0063ffffff -> 0x0060300000.
pci-msm 1c00000.qcom,pcie: non-prefetchable memory resource required.
pci 0000:00:00.0: BAR 0: no space for [mem size 0x00001000 64bit].
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x00001000 64bit].
Change-Id: I8b1591ea83784ffc19c928e1af73117657ac7f15
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
