Update llcc gold bwmon to have its memory mapped as
non-early for sun.
Change-Id: I190283c136736b069eaed6805f5813ceb0c2d38f
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Update uart clock name from se to se-clk for Ravelin.
Change-Id: Ib2b614ba3a0f2bf307e7fa7678a10ccfe97da1c1
Signed-off-by: Prakash Yadachi <quic_pyadachi@quicinc.com>
Add test node to sun.dtsi, sun-vm.dtsi and sun-oemvm.dtsi
to validate large dmabuf transfer functionality.
Change-Id: I17cd06d12e18f26a6afe7c2da13fcca23a375b04
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
Add gh-large-dmabuf-test binding description and requirements
which include compatible, label and optional properties.
Change-Id: Ief22a3b609539ea307f289fb62e7c90b3a1284f6
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
Fix for pmic glink node for ravelin without this change glink
channel registration fails for the ADSP communication.
Change-Id: I02d1ea7b11db6e5e5dfd0f85e384797b1b6b96b9
Signed-off-by: Akhil Manikoth Kallankandy <quic_c_akhika@quicinc.com>
Remove the qcom,msm_fastrpc nodes as these
are moved to dsp-devicetree.
Change-Id: I2ae6d3d27b27895859c4f1e241012d288f5f7a72
Signed-off-by: Akhil Manikoth Kallankandy <quic_c_akhika@quicinc.com>
Add the DMA-BUF heaps node for kera. This adds default
heaps like system and secure-system heap. Clients
can add their own DMA-BUF heaps in here.
Change-Id: Iee72407be99b936e22f5cf4b5eb55b302fed5cac
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Add initial memory configuration and reserved memory map
for kera, inline with v1.
Change-Id: I2b3ed445feebd6141beb59bd23e416711e17747c
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Add generic bindings for the Qualcomm variant of the ARM MMU-500. It is
expected that all future platforms will use the generic qcom,smmu-500
compat string in addition to SoC-specific and the generic arm,mmu-500
ones. Older bindings are now described as deprecated.
Note: I have split the sdx55 and sdx65 from the legacy bindings. They
are not supported by the qcom SMMU implementation. I can suppose that
they are using the generic implementation rather than the
Qualcomm-speicific one.
[Add dt-bindings for qcom,smmu-500 for Qcom SoCs].
Change-Id: Id2520441f556590403ac712f68aa7487ca4f205e
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221114170635.1406534-5-dmitry.baryshkov@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>
Git-Commit: 6c84bbd103d85696af9cc0f746c01f9b2847637e
Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Document the sdxkova platform binding and also the boards using it.
Change-Id: Ifc488cf86c0113ce4df6140770b328851a786235
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
Add cpu0-0-0 zone's trip to make fan run at level 50.
Change-Id: Id3f38d165e513ec633f3a289cfddfc60284f8f7c
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Add cpufreq cycle counter register information to devicetree in a
separate node for use by driver. This will initialize walt for Monaco.
Change-Id: Iddbbd81168d49e0aea4076f18669ffb6a5d342a8
Signed-off-by: Ruchira Revdekar <quic_rrevdeka@quicinc.com>
Add keep-running property for OEMVM to let OEMVM shutdown gracefully
even if qcrosvm got killed.
Change-Id: I6b78f13f095ab8a3b068d94219b28cebbae2a75a
Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
For current design, we can't do VM restart after VM crash due to RM
not allow. Add new crash-restart property to let RM allow do VM
restart. The crash-restart property will be valid when remove
crash-fatal property.
Change-Id: If9cb90d7bc581465b760a5c780203911a247e341
Signed-off-by: Peng Yang <quic_penyan@quicinc.com>
Update gpu mitigation for bcl for sun based on latest
recommendation.
Change-Id: Ieb25a08cc260252a6a71da954cb2b0e0879c35b1
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
Use upstream compatible DT property "iommu-addresses" instead
of "qcom,iommu-dma-addr-pool" for dwc3 which describes the
addresses that dwc3 cannot use.
Extend the address and size cells to ensure that IOMMU returns
a 32 bit address, in order to define a region that will block
0xf0000000--0xffffffffffffffff.
Change-Id: I211ba1b8bd1f7717f639d91dddb8adb86f17b42e
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add the DMA-BUF heaps node for tuna. This adds default
heaps like system and secure-system heap. Clients
can add their own DMA-BUF heaps in here.
Change-Id: I7b4d36250759e69248ec3fa371a4e5262885dc7f
Signed-off-by: Vijayanand Jitta <quic_vjitta@quicinc.com>
Disable ipa, gsi, rmnet and smp2p nodes for monaco target.
All the nodes are added in data specific dt files.
Change-Id: I8d0ead8276702aa3a03688b4b6b99630facac926
Signed-off-by: Prasad Arepalli <quic_parepall@quicinc.com>
Currently fastrpc dt nodes are present in main dt file.
With fastrpc driver migrating to upstream driver,rpc
properties will be overlayed out of kernel.
Change-Id: I91d915ae9ce7d55b5e81ff10d20eb7c370740172
Signed-off-by: Abhinav Parihar <quic_parihar@quicinc.com>
