Disable turing dpm1/dpm2 tpdm because some clocks can not be enabled
from kernel side.
Change-Id: I4c51b3dbfdba44f843617e788ccd7c7d559646fc
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Update cpucp device to include reg-names property.
Change-Id: I78d9d386971952511f66f455857adcc8ea9edf58
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
All transferring memory between tvm, oemvm and pvm.
Change-Id: I2016350893bf79cfc09a22741dfa69627c795840
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add devicetree to the OEM dtsi for smcinvoke in
the OEM VM.
Change-Id: I88d22618297704a95eb36e46602b0d20fe88470d
Signed-off-by: songrui <quic_songrui@quicinc.com>
Added SP PBL Patch Version Register to read the SP-PBL
patch version to handle SPSS attach timed out scenario.
Change-Id: Id7ee4df5d09d9c09410bc24fc475ee2a36fca246
Signed-off-by: Magesh M <quic_murugan@quicinc.com>
Add dtsi entry for ssip fuse configuration on Sun platform.
Change-Id: I1f6dbc9608db1e29aef1d9699820eb1e1d3c9299
Signed-off-by: Ping Li <quic_pingli@quicinc.com>
Add 3.5mm support for MTP platform on Sun SoC.
Change-Id: Ia2e847329d320a79a393d8d6079385547511369f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
ATP on Sun SoC only supports v8 but is defaulting to v6 power grid.
Update ATP platform on Sun SoC to use v8 power grid.
Change-Id: I34382cdaa2bf95f6fc71758cf7ee34240e6c1c29
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
FastRPC node is added under glink node to provide intent
information. With fastrpc driver migrating to upstream
driver, this property will be overlayed from out of
kernel. Also update glink label for cdsp.
Change-Id: Id1e3aa0ebf13a894a9420c8a97f195bd906c4f7f
Signed-off-by: quic_anane <quic_anane@quicinc.com>
Add device tree files to support No Display support for
CDP platform on Sun SoC.
Change-Id: I4174e2640be1ba7974e5a1ec14f0aadac05aaf0b
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
"coresight-gfx-funnel" needs to be disabled by default, it will be enable
from GFX DT side.
Change-Id: I041fe3e3d43b1880147826d757029118da24cf24
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
We need to override the PCIe SM PWR_CTRL and PWR_CTRL_MASK
registers so that CXPC can happen when pcie driver is not probed.
Without this change, CXPC will be blocked when the pcie driver is
not probed as there will be no notification from PCIe SM entity to
allow CXPC. Once we these registers are written 0x1, no one will
wait for PCIe SM to allow CXPC.
Change-Id: I8d1542deb4fcc10849c848aa73718a47af556719
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add wireless firmware name in battery charger device to support wireless
FW update for IDT9418 wireless transceiver found on Sun platforms.
Change-Id: I0e715b5a2bd297eec5f801c2fb09bc6023ac9c42
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Make changes to enable SMEM Mailbox SMP2P nodes for sun to
communicate with modem.
Change-Id: Iea261c8f42768c05eec7caf62adcd1dcc93cd950
Signed-off-by: Tyler Wear <quic_twear@quicinc.com>
Enable skin sensor thermal zone based fail safe rule for high
ambient condition for sun.
Change-Id: I7661c3b4a318fbadd0f963b972274a75fe1b71fd
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
Enable different pmic die temperature alarm sensor mitigation
for sun.
Change-Id: I795121e91b288307fbc87bcd4a500e4d3b274150
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
