Removed SP PBL Patch Version Register from sun dtsi
since it is no longer used.
Change-Id: I52b28ed1a07676188a39c09b72c0e2364cfc0ac2
Signed-off-by: Magesh M <quic_murugan@quicinc.com>
Based on the DisplayPort CTS PHY test, current EQ settings were not
sufficient to pass the test margins. Adjust the EQ from 2dB to 0dB as
recommended by the display team based on the results.
Change-Id: Ib0b6c7f9ccb2d8385d57be0aceda704dc98f7f18
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add device nodes to configure PDP mailbox and add support
for PDP logging on both PDP cores.
Change-Id: I2393334d33373df3447f5140cc66cd7624faf0cd
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Currently ibi gpii irq configured wrongly, due to this
ibi controller doesn't generates irq. To solve this
rectified the gpii irq number.
Change-Id: I05c7f41463c19ffbf095c2ec6d217210f8d2aa8f
Signed-off-by: Anil Veshala Veshala <quic_aveshala@quicinc.com>
For AON usecase switching from HLOS to SSC needs TLMM function to be
non IBI, hence during sleep mode change function of the TLMM to QUP
mode so that SSC can work with IBI disable without any issue.
Also ensures to restore back the TLMM Function to IBI mode when HLOS
i3c usecase starts.
Change-Id: Id6a5cdeafe2c3ee50186c0020831e4eb8f329f95
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Currently, charger FW configures and enables ship mode in parallel with
shutdown activity. This can cause a race condition leaving the device in
a bad state if the device is powering off while SW is still issuing SPMI
writes.
Add the battery charger "qcom,ship-mode-immediate" property on Sun
platforms so that ship mode will be configured immediately by charger FW
after user sets ship_mode_en.
Change-Id: I55a78c7b5c59b8b82519713fb4267d081c54a92f
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Currently, charger FW configures and enables ship mode in parallel with
shutdown activity. This can cause a race condition leaving the device in
a bad state if the device is powering down while SW is still issuing SPMI
writes.
Add new "qcom,ship-mode-immediate" property to flag that ship mode should
be immediately configured after user sets ship_mode_en to avoid this
race condition.
Change-Id: I16b1e307cac8befff7a1136de1cb522e03a95c46
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add compatible strings for Ravelin and RavelinP SoCs.
Change-Id: Ibf00b144c1798024fec669545e4fbeeefe5b21c9
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add the pm8550_pa_therm2 ADC channel as well as the corresponding
thermal zone device which can be used by thermal SW.
Change-Id: I2c583ca8c00a67a122b6c1b7622436bcf8058165
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Mark GCC clock node as GenPD provider and disable the
PCIE GDSC regulator nodes.
Change-Id: I98fc6709592c393259da77443d4b6e580e61a0b8
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Mark dispcc clock node as GenPD provider and disable the
display GDSC regulator nodes.
Change-Id: I91cf788254ca0bd78a02dc4b196745da380fb74b
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Mark videocc clock node as GenPD provider and disable the
video GDSC regulator nodes.
Change-Id: I206ad77302fa8ece5b4efe28e20d8c1c23d9fac7
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Configure the L1F and L3G active-only regulator to be always enabled
in high power mode (HPM). These regulators power REFGENs and PLLs
used by the application processor itself. Unconditional active-only
voting is needed since the software running on the application
processor won't be capable of removing L1F and L3G votes after the
application processor subsystem is power collapsed.
Change-Id: I750da467f408f35b6015a2286696609f234abdc4
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add active-only and sleep-only regulator subnodes for rpmh-regulator
devices L1F and L3G on Sun boards. This allows requests to be issued
for them that are tied to the application processor's power collapse
state.
Change-Id: Ia8fd8c3aef5c5abfec1044ba3287b1a59f1d5824
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Add qcom,ramoops binding for its device and it is exactly copy of
ramoops device but differ in just memory is dynamically reserved
during early boot.
Change-Id: I2b2b288061ba001aa8cc9a73fad1176a01ce4769
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add dynamic ATID support for remote etm and non HLOS related TPDM.
Change-Id: Ib20d304b27377e19ca347e81eab587de41713ed0
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Disable tpdm-sdcc2 on sun, because kernel can't enable some clocks of it.
Change-Id: I5f8a29a6991d1b59e82bce0caf4149f8e9993697
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Add minidump vdeivce in vm-config to support minidump for Sun TUIVM.
Change-Id: I8aed4b1bec0b137bdcf8e103af59eb0cb70b999a
Signed-off-by: Cong Zhang <quic_congzhan@quicinc.com>
Add device tree files to support v6 and v8 power grids
for MTP platform with QMP1000 on Sun SoC.
Change-Id: Ic8636091236e3bcedd5af1fb2c5742371483607d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Adopt the upstream ufs bus voting implementation using
commit <03ce80a1bb8>
("scsi: ufs: qcom: Add support for scaling interconnects").
With this implementation, the Qualcomm's bus voting parameters
are moved to the driver source code. As a result, remove the bus
voting DT entries here.
Change-Id: I6366fe76fba4022cbd97bb757eaac2183274bcd2
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
The upstream commit <a5bf3cfce8cb7>
("iommu: Implement of_iommu_get_resv_regions()")
The upstream linux community has added a devicetree property
"iommu-addresses", which describes to the DMA api what IOVA
addresses a device can/cannot use. So we replace “qcom,iommu-
dma-addr-pool” by “iommu-addresses” since kernel 6.5 to follow
upstream.
Change-Id: If18f14d6cb13aa2ed67c1417295fc30723b0c932
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
The upstream commit <a5bf3cfce8cb7>
("iommu: Implement of_iommu_get_resv_regions()")
has added a devicetree property "iommu-addresses", which
describes to the DMA api what IOVA addresses a device
can/cannot use. So we replace “qcom,iommu-dma-addr-pool”
by “iommu-addresses” since kernel 6.5 to follow upstream.
Change-Id: I9c99fc931fa9a59a472f371bfb59f615f83539f4
Signed-off-by: Ziqi Chen <quic_ziqichen@quicinc.com>
