Currently, IRQ is set to IRQ = IRQ -2 for E2 builds,
but for the E3 build IRQ number should be set according
to document.
Change-Id: I18cc6f3172b61cdb0af868b59db48e151a15fb2c
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
Change https://lore.kernel.org/all/20230525113034.46880-1-tony@atomide.com
registers serial core controller as a child of msm uart device.
Since child should suspend first, due to the child's auto suspend
delay (SERIAL_PORT_AUTOSUSPEND_DELAY_MS), additional 500msecs
delay is added during msm_geni_serial_runtime_suspend.
Added new optional dtsi property 'qcom,suspend-ignore-children'
which when set ignores dependencies on children by PM framework, this
helps to exit quickly from msm_geni_serial_runtime_suspend and save power.
Change-Id: I36b239cf19293ee7b1ebecf32cdd0ad0749dbca1
Signed-off-by: Visweswara Tanuku <quic_vtanuku@quicinc.com>
Add support for ice wrapped keys to the UFS DTSI entry
on pineapple targets.
Change-Id: I3e04b07438b3859ef7e1545b73d0361406948aa2
Signed-off-by: Gaurav Kashyap <quic_gaurkash@quicinc.com>
Enable USB related properties for USB functionality
on tuna.
Change-Id: Ia4270aa4860d8b894ab094dafbad61d278f7606f
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
The cam_cc_titan_top_gdsc causes camera to permanently assert qactive
when it's enabled. If MMNOC attempts to collapse when the GDSC is
enabled, then the qactive signal will cause BCM to get stuck in the
collapse sequence. This will eventually lead to rpmh driver timeouts
when requested for MMNOC. Fix this by explicitly voting for MMNOC on
behalf of the GDSC.
Change-Id: I6689318f48fbdb4bd70b192143a11148acdb456e
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
There is 16K of DDR in a section memory and the rest is carveout in a
memory region [0x98000000 a0000000). As section size is 128M, which
require 2M of memmap. Lose this 16K to save (2M - 16K) of memory.
Change-Id: Ibca933768e89a978b97fe37a07938a08141d2e87
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Enable dma-heaps driver on OEMVM, as well as bringing in other features
such as virtio mem and large-dma buf support.
Change-Id: I7f679c061ba65237541363bd0b406bb4e58e697e
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
This device can communicate with more than one msgq. Describe
the names or these msgqs.
Change-Id: Ibc0a4de16c6158ac756459fc2ee8862bd9e23215
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Allow mem-buf ipc messages between oemvm and pvm.
Change-Id: Ib3209f72bbcb146f7f3ae9e4d75e474750e2dd97
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Only one top-level devicetree node can be defined per file; move
qcom,mem-buf-msgq to its own.
Fixes:
../Documentation/devicetree/bindings/soc/qcom/qcom,mem-buf.yaml:56:1:
[error] duplication of key "properties" in mapping (key-duplicates).
Change-Id: I8f7b5bdd94afa38ade3b2173ee2d99c6906cc74d
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add cpufreq cycle counter register information to devicetree in a
separate node for use by associated driver.
Change-Id: Idadbf45cfaf1fec6ee9187d28f6b939fceb76bd0
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
Add "qcom,max-cpus" DT to specify the maximum number
of CPUs the SoC supports.
Change-Id: Ia5a63d3fb2224652bf572d625f2d7b1bc51680e5
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add the dummy clock & gdsc handles for clients to be able to request
on them for tuna platform.
Change-Id: I6afb889a443b6e34ba94cbaff26bec43a85f6b88
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
Add ParrotPRO SKU soc id support in device tree.
Change-Id: Ifdc24bf2db97048706d2f655be063b5c57e19799
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Add MSC info to MPAM node, so MPAM driver can get the number and
name of one specific MSC.
Change-Id: I0966545a92a3bc755c44a3cd2cbdc355413a6aab
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
Add pinctrl node with compatible "qcom,kera-tlmm" in order to
enable the Top Level Multiplexer (TLMM) block on Kera SoC.
Change-Id: Ie0b58783d8c77c5f6375eb6ddab5495ca5061040
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
