Add cpufreq cycle counter register information to devicetree in a
separate node for use by associated driver.
Change-Id: If1b45003a1ce4faca372db2954293493bc45bbb6
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
For VM bootup the scm device needs to have memory from above 4GB, but for
PIL boot the Metadata memory needs to be limited to 32 bit. This is
because the authentication software for the metadata in the secure world
works with only 32 bit addresses. Add support for only 32 bit addresses
for PIL and memory from anywhere for other memory allocation from SCM
device.
Currently, this is being enabled for ADSP/CDSP/MSS however, this limitation
was applicable only for modem and not with ADSP/CDSP but there was some
issue observed with above 4G addresses allocated for ADSP/CDSP and it
was analyzed that it could be only issue on emulation platform and will
not observed on Silicon. So, we could revert this change for ADSP/CDSP
if the issue is not observed on Silicon.
Change-Id: I398158a76207f4ef43770ed60210d1f155263850
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
IMEM gets updated with Modem DSM memory region info when Modem taken out
of reset by APPS and the info is used for collection of coredumps.
Change-Id: I313d374772bcc95495e9965b7fa1f455ac36a82a
Signed-off-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
These clock phandles are necessary to ensure the clock devices probe
before debugcc. Debugcc needs its parent clock devices to probe first,
otherwise it'll invalidate their associated mux_sels during
clk_debug_mux_init() and they can't be measured.
Change-Id: I30d1a9e24ae1ac5a9efc7d8f8e0740ebdce8e1b0
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Describe the communication channel used to communicate with the
firmware which supports onlining and offlining of memory.
Keep the device in a disabled state for now until a conflict
between THP and memory-hotplug features can be resolved.
Change-Id: I3d74d9d3d58d379b2a91ee976a72dddfb7a221c6
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
There were 2 entries for spss, remove one.
Change-Id: Ia7aae336809953377f9a9da6457289262fb2524a
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Adding the firmware name and updating the additional memory assign node
for remoteproc's to be compatible with the driver.
Change-Id: I3787fd0c97c039821a91e15bc6e554caccf071a8
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.
Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Enable tlmm VM mem access device tree nodes for Pineapple.
Change-Id: I2bfbc22e8f9e933e3d0ec419b3fa67ff89b4fdad
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add base TUIVM and OEMVM device tree support for all Pineapple platforms.
Change-Id: I7c3cc2112e122f25a2f0b573128e8fdfb86975c5
Signed-off-by: Meena Pasumarthi <quic_pasumart@quicinc.com>
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add crmb and crmc register space for cesta devices on pineapple.
Change-Id: Ia8ec195ca1683e652b31a5daa2ab271e8bcec321
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Since we use downstream pmic_glink drivers, use the right compatible
string for pmic_glink devices on pineapple to support battery
management.
Change-Id: Ia6375ec2c938149dd31ae073b906b1c09b37b21e
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Update memory map to V6, from a baseline of V4.
Change-Id: I167de96b3a2f199188a4d8c995aa49ef6b83fee1
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Enable dma heap headers which was commented due to unmet
dependencies.
Change-Id: I46b380ff564a602cb85826407c76bf7c9324f50c
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
