Add test node to sun.dtsi, sun-vm.dtsi and sun-oemvm.dtsi
to validate large dmabuf transfer functionality.
Change-Id: I17cd06d12e18f26a6afe7c2da13fcca23a375b04
Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
Fix for pmic glink node for ravelin without this change glink
channel registration fails for the ADSP communication.
Change-Id: I02d1ea7b11db6e5e5dfd0f85e384797b1b6b96b9
Signed-off-by: Akhil Manikoth Kallankandy <quic_c_akhika@quicinc.com>
Remove the qcom,msm_fastrpc nodes as these
are moved to dsp-devicetree.
Change-Id: I2ae6d3d27b27895859c4f1e241012d288f5f7a72
Signed-off-by: Akhil Manikoth Kallankandy <quic_c_akhika@quicinc.com>
Add cpu0-0-0 zone's trip to make fan run at level 50.
Change-Id: Id3f38d165e513ec633f3a289cfddfc60284f8f7c
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Update gpu mitigation for bcl for sun based on latest
recommendation.
Change-Id: Ieb25a08cc260252a6a71da954cb2b0e0879c35b1
Signed-off-by: Manaf Meethalavalappu Pallikunhi <quic_manafm@quicinc.com>
Use upstream compatible DT property "iommu-addresses" instead
of "qcom,iommu-dma-addr-pool" for dwc3 which describes the
addresses that dwc3 cannot use.
Extend the address and size cells to ensure that IOMMU returns
a 32 bit address, in order to define a region that will block
0xf0000000--0xffffffffffffffff.
Change-Id: I211ba1b8bd1f7717f639d91dddb8adb86f17b42e
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Disable ipa, gsi, rmnet and smp2p nodes for monaco target.
All the nodes are added in data specific dt files.
Change-Id: I8d0ead8276702aa3a03688b4b6b99630facac926
Signed-off-by: Prasad Arepalli <quic_parepall@quicinc.com>
Currently fastrpc dt nodes are present in main dt file.
With fastrpc driver migrating to upstream driver,rpc
properties will be overlayed out of kernel.
Change-Id: I91d915ae9ce7d55b5e81ff10d20eb7c370740172
Signed-off-by: Abhinav Parihar <quic_parihar@quicinc.com>
Add a node for scm device and sysmon, shmbridge for Kera SoC.
Change-Id: Ied886250dba41209cac68cbe52498061bd6daf51
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Add EUD node in device tree to enable EUD driver
on Kera SoC.
Change-Id: I94aacb9b223b9935c78045bfc3de9179f3bf9871
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Update iova-width property for gfx_0_tbu and
gfx_1_tbu nodes under kgsl-smmu for ravelin.
Change-Id: Ib43fa6ca8a66716b8604658413f05551e5b04826
Signed-off-by: Archana Sriram <quic_c_apsrir@quicinc.com>
Enable parade touch driver node and add its documentation
for bring-up.
Change-Id: I717186399283741c7c1957acc3319148b4d843f3
Signed-off-by: Akshay Gola <quic_agola@quicinc.com>
Use upstream compatible DT property "iommu-addresses" instead
of "qcom,iommu-dma-addr-pool" for qup which describes the
addresses that qup cannot use.
Change-Id: I8912ee5a256a15ed8e0cb729dd784bce4568c4fb
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
Currently, it seems the HS transmit programmed isn't enough to
pass electrical compliance tests for all devices. Therefore
increasing it to 0xf (recommended by HW team) in order to
meet the passing marks.
Change-Id: I6609d6012e8ec6489c33af0a75873314a5b10e67
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
For backward compatibility for ravelin target, add
qcom,force-low-pwm-size property to limit setting PWM sizes to
6 and 9 bit modes only, rather than using the full 8 to 15 bit
PWM sizes range.
Change-Id: I3fdf12f49cec92cfb02ef994b6abbebbd29cc8e9
Signed-off-by: Shilpa Suresh <quic_c_sbsure@quicinc.com>
Add the smp2p nodes for lpaidsp, modem, cdsp and soccp for tuna.
Change-Id: I465ddbfcb6e69a65b730e395e705e08bc75c5060
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
Add devicetree nodes to enable qmp communication with aop and tme.
Change-Id: If869e4d16758d53808852517532aaf2a2ed98846
Signed-off-by: Pranav Mahesh Phansalkar <quic_pphansal@quicinc.com>
Fix for pmic glink node for parrot without this change glink
channel registration fails for the ADSP communication.
Change-Id: Ib8a79ca286a884ea679cc34829823cdeca8f5751
Signed-off-by: Akhil Manikoth Kallankandy <quic_c_akhika@quicinc.com>
