ARM: dts: msm: Use "iommu-addresses" property for ravelin qup
Use upstream compatible DT property "iommu-addresses" instead of "qcom,iommu-dma-addr-pool" for qup which describes the addresses that qup cannot use. Change-Id: I8912ee5a256a15ed8e0cb729dd784bce4568c4fb Signed-off-by: Saranya R <quic_sarar@quicinc.com>
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@@ -17,6 +17,13 @@
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* Qup1 4: SE 9
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*/
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qup_iommu_region: qup_iommu_region {
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iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>,
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<&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>,
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<&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>,
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<&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
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};
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/* GPI Instance */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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@@ -40,7 +47,7 @@
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qcom,static-gpii-mask = <0x1>;
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qcom,gpii-mask = <0x3e>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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memory-region = <&qup_iommu_region>;
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dma-coherent;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok";
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@@ -56,7 +63,7 @@
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x163 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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memory-region = <&qup_iommu_region>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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@@ -294,7 +301,7 @@
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,gpii-mask = <0x3f>;
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qcom,ev-factor = <2>;
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qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
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memory-region = <&qup_iommu_region>;
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dma-coherent;
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qcom,gpi-ee-offset = <0x10000>;
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status = "ok";
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@@ -310,7 +317,7 @@
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0x403 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
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memory-region = <&qup_iommu_region>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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