The L1F regulator is a parent for the M31 EUSB2 PHY. Vote for this
regulator when PHY is resumed, and disable when suspended.
Change-Id: I91d309b5afefc7c9b4205e9e73b3714963d3f45f
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Add the REFGEN_VDD_A_0P9/VDD_A_PCIE_0_0P9 regulator so that the
ufs phy driver can vote for this regulator. This vote is needed
according to the Sun's Power Grid Analysis document.
Change-Id: I3427e2f529ec734983ea6c2db97411c997260bb0
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add device tree support for v8 Power Grid on QRD SKU2
platform for Sun SoC.
Change-Id: I4bc070e9dbddae39d033fbf16f5ca811295efff6
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add device tree support for v8 Power Grid with Kiwi on MTP, CDP
platforms for Sun SoC.
Change-Id: I517f023e516cab8735bdd2e264e8028a4e7debe7
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add the nodes for enable qrtr communication between primary vm and
oemvm on sun.
This adds platform devices and vdevice descriptions to start the
qrtr gunyah transport on both primary vm and oemvm device trees. This
also adds the device tree node to configure qrtr as node id 21 on oem
vm.
Change-Id: I1575853a67fe9edbcb751dbb71062b6da624d9be
Signed-off-by: Kishore Kumar Ravi <quic_kiskum@quicinc.com>
Dtbo overlays were not being built with the Bazel build system
because they were not part of the platform map.
Add them now.
Change-Id: Icb88c76552e1ab7d0a0e0fa168ae91f87335be2f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Enable the UFS MCQ feature on the Sun platforms.
Change-Id: I6d58bb14ea085cfd792cfea0073cccfa8be38edb
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add the qref regulator for pcie node in sun.
Change-Id: I8959a683a5d73429069cd6795f00a5b1fe91c082
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Add GSI related registers dt entry to sun to support GSI functions.
Change-Id: I0920fc27e827952d55d87a59b093d945830868d5
Signed-off-by: Elson Roy Serrao <quic_eserrao@quicinc.com>
From Armv8.6 the counter operates at a higher fixed frequency of 1GHz.
This implies a resolution of 1ns. Change cpu arch timer frequency to 1ns
from 52ns (19.2Mhz) resolution.
Change-Id: Ib0bfe643edbd4de568cf30ebaa1ec1175111352e
Signed-off-by: Murali Nalajala <quic_mnalajal@quicinc.com>
Update the L11B and S7I regulator max voltage limits to match
the latest guideline.
Change-Id: Ia36cdbe8ad6526070e43325ff3cdb2cc6bfc58f0
Signed-off-by: David Collins <quic_collinsd@quicinc.com>
Disable tpdm ddr-ubwcp, because the clocks associated with it are
not enabled.
Change-Id: I4bebde68995bc9831c067ca25978fae858b7536c
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
Current setting votes for 912mV for the QMP PHY vdd rail, which is above
what is recommended from the power grid. Set the vdd operating voltage to
880mV to match what is suggested, in order to maintain the regulator
numbers expected for the rail.
Change-Id: Iaefd58656c72427933e45000db21f55bc5de979c
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
