Since, we are settle down with 19.2 MHZ for Arch timer frequency
for Sun target, let's do it for VM as well.
Change-Id: I456015fefd6fb7df53cb1d0258e2ee988fd5c88f
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Update disp_rsc device to use correct 0x1000 size instead of 0x10000
for sun.
Change-Id: I81607aaf202ff18032fa117dfbb6f47f4e4ebb40
Signed-off-by: Rashid Zafar <quic_rzafar@quicinc.com>
Add qcedev crypto support for sun platforms.
Change-Id: Id558a7d0620afa40c8d9b8e43161d8f6ca09e810
Signed-off-by: Daniel Perez-Zoghbi <quic_dperezzo@quicinc.com>
Provide a contiguous region for use by qmc. Unless explicitly
instructed, this region should not be used by external customers.
Change-Id: I98f651c835cf7fa19eba2bc209eb7b7807245877
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
There are some bootargs are redundant and unnecessary getting
carried from older target they are useless and need not be
carried on current targets like service_locator.enable=1.
While some like ftrace_dump_on_oops need to be enable when
minidump gets enabled.
Change-Id: Ib73d1cb7f7e2242dd52524520164c3c89b79083e
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
This reverts commit 704e2e0186.
Reason for revert: No longer needed once 1ns frequency is disabled.
Change-Id: I2355fff08acf5746efdce7562df99f83bba4696b
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
EUD node was set to bypass the pdc since the pdc node was unavailable.
Now that it's available, set the interrupt parent to the pdc and adjust
the EUD node accordingly.
Change-Id: I2516315753a3452d66b9cad3e6bdc089bb8dcd6c
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
PMK8550 has a couple of high resolution PWM channels which can support
from 8-bit to 15-bit PWM. Add it.
Change-Id: I277bca101546de07ffc8bb34380fc8bbdea10a92
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Updating build files with ATP platform DT support on Sun SoC.
Change-Id: I6e0d614d5ea3c6d781c432e8e5dde900aa1aa02f
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
The qcom,display heap is used for camera usecases.
Change-Id: Ib937670c33284fb2dc624258fd8e5978b4405ace
Signed-off-by: Vijay Kumar Tumati <vtumati@quicinc.com>
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
After hotplugging in memory, automatically online it to the movable zone.
Change-Id: I1dde15451e78196fc261c0bd9b25cdfa91749c4c
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add DT support for RCM platform on Sun SoC.
Change-Id: I1dc5b3b432b2126b0a380437a2a19854aa1db5f1
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Add AMOLED ECM device for PMD802X so that AMOLED panel current
can be measured on need basis for Sun platforms.
Change-Id: Ic5e699fa5c4c595bbcc1b540c0197c1e63673c32
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
Correct the SID ranges for the cam_hf qtb and the mdp_hf
qtbs.
Change-Id: I0d6127248bbfac122d14ca2c600dd81d3a7d5550
Signed-off-by: Oreoluwa Babatunde <quic_obabatun@quicinc.com>
Add qcom,sensitive property in vm-config node for Sun VM.
Change-Id: I5b2781df510f59d7c3f779eecb55c7bc64fad84c
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Add devicetree soccp node for Sun SoC. In addition to existing smp2p INT's
SOCCP H/W needs 2 more INT for controlling the power state of the H/W.
sleep bit and wakeup bit on master kernel corresponds to these INT.
Change-Id: I00d2f6a3fb76f306fa070df87f22bb2d07cb4c3b
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Add VADC GEN4 channels provided by pmk8550 that are used by thermal
clients on Sun. Also, add the corresponding thermal zone devices.
Change-Id: Ia1eca3b4eb5e95612590ec2405bb366ed170c60a
Signed-off-by: Minghao Zhang <quic_minghao@quicinc.com>
Signed-off-by: Anjelique Melendez <quic_amelende@quicinc.com>
Add thermal mitigation step for sun boards so that clients like
thermal SW can do thermal mitigation via charge_control_limit
property under battery power supply.
Change-Id: I0a4ec6e466d5cc52577a28334ec66eddcaf35ef5
Signed-off-by: Subbaraman Narayanamurthy <quic_subbaram@quicinc.com>
