Add properties like premature count, sample invalid time and whether
to use bias timer for cluster device.
Change-Id: I487e420ce422766b18d6c86632c521215b0ed484
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
CPUCP exposes certain clocks over SCMI. Enable the clock protocol to
handle these.
Change-Id: Idfc040e852cb19adae8340f6ceda7f95f52ccb1c
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Add CPUs for each CQ in qcom,esi-affinity-mask.
Change-Id: I78dd9b6ffa28aceaeb5feeaec543172c672bb986
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
Add an extra bit in the SOCCP SMP2P to check if the soccp is in D0.
Change-Id: I0df3ab9b135e4273d028443cecf8887e7ad794ab
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
GLINK PKT provides a userspace interface to RPMSG GLINK through
character device nodes. Add the loopback node and corresponding
channel device to enable GLINK communication from userspace to
communicate with loopback test server.
Change-Id: I8777564c695c5b5718d5016e79ec09beeb353d90
Signed-off-by: Vishnu Santhosh <quic_vishsant@quicinc.com>
Cpu and logbuf vendor hook module moved to simple helper
loadable modules and now there is no need of them to have
device node in device tree.
Change-Id: I97b79f76eef5743755746c684e8d306c11c9a507
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
The cam_cc_titan_top_gdsc causes camera to permanently assert qactive
when it's enabled. If MMNOC attempts to collapse when the GDSC is
enabled, then the qactive signal will cause BCM to get stuck in the
collapse sequence. This will eventually lead to rpmh driver timeouts
when requested for MMNOC. Fix this by explicitly voting for MMNOC on
behalf of the GDSC.
Change-Id: I6689318f48fbdb4bd70b192143a11148acdb456e
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
There is 16K of DDR in a section memory and the rest is carveout in a
memory region [0x98000000 a0000000). As section size is 128M, which
require 2M of memmap. Lose this 16K to save (2M - 16K) of memory.
Change-Id: Ibca933768e89a978b97fe37a07938a08141d2e87
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Allow mem-buf ipc messages between oemvm and pvm.
Change-Id: Ib3209f72bbcb146f7f3ae9e4d75e474750e2dd97
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Add "qcom,max-cpus" DT to specify the maximum number
of CPUs the SoC supports.
Change-Id: Ia5a63d3fb2224652bf572d625f2d7b1bc51680e5
Signed-off-by: Bao D. Nguyen <quic_nguyenb@quicinc.com>
Add MSC info to MPAM node, so MPAM driver can get the number and
name of one specific MSC.
Change-Id: I0966545a92a3bc755c44a3cd2cbdc355413a6aab
Signed-off-by: Huang Yiwei <quic_hyiwei@quicinc.com>
Configure low power cpu on gold bwmon for sun.
Change-Id: I323797604e76a5e872171ba359ee43cc155235c6
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Handle voting for the regulator for SPU sensors.
Change-Id: I192731df94cc894cdf6826c69230b0cf9a3e9c3e
Signed-off-by: Nurit Lichtenstein <quic_nuritl@quicinc.com>
Add glink probe driver entry for Sun to have a way for
glink core to get pm notifications during apps suspend/resume.
Change-Id: I0f27ac9377cd6818f4c60cace116bdefc935ab88
Signed-off-by: Sarannya S <quic_sarannya@quicinc.com>
Add shared memory to support persist on sun-oemvm.
Change-Id: Ic7f97ac2da114e56ef297d74f4a8d70fb27987e7
Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
Enable secondary ddr voting on llcc bwmons for sun
and remove existing ddr bwmon given this enablement.
Change-Id: Icbb1ad3fbf7b44bf66a64f3cc8cefe9061953015
Signed-off-by: Amir Vajid <quic_avajid@quicinc.com>
Add the soc-specific compatible string for qfprom to
support keepout regions on Sun SoC.
Change-Id: I676acc8110d05dd7d9d7fef0455b5152f3afc4ac
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
This reverts commit c0a6035e47.
Facing issue where PCIe PHY GDSC is getting turned off when system
suspend is happening. So reverting this change till we find a fix.
Change-Id: Ic4bb32c126e0247688d31e276a9a3f29c373b167
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
SOCCP uses mx and cx power rails and not the island rails.
Change-Id: I52f3f28f9206e62b4b7dc99dd4c7c9f19d6f92cf
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
SOCCP requires only LOWSVS power level for the regulators.
Change-Id: I940304eacd9d4e039d65b42866daf69aaae75b85
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes. While at it, update gxclkctl
node to add support for gx_clkctl_gx_gdsc power domain.
Change-Id: I0d4c84da2e3aadd7e1a901d6a9e26c7d4ad1a3c1
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
