Merge "Revert "ARM: dts: msm: Add GenPD phy regulator to PCIe node""

This commit is contained in:
qctecmdr
2024-04-11 20:03:05 -07:00
committed by Gerrit - the friendly Code Review server
2 changed files with 1 additions and 5 deletions

View File

@@ -51,8 +51,7 @@
&pcie0_clkreq_sleep
&pcie0_wake_default>;
power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
power-domain-names = "gdsc-phy-vdd";
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS

View File

@@ -1773,7 +1773,6 @@
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
@@ -2005,7 +2004,6 @@
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
@@ -2017,7 +2015,6 @@
qcom,no-status-check-on-disable;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 2>;
qcom,support-cfg-gdscr;
status = "disabled";
};
gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {