Manish Pandey
7ba4fef4ec
ARM: dts: msm: Update Reference Clock to clk8_a4 for Kera UFS 2.x
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The Kera UFS 2.x requires a reference clock of 19.2MHz. Currently,
the reference clock provided by the DTSI node RPMH_LN_BB_CLK3
returns clk_get_rate() as 38.4MHz.
To address this, the handler is updated to use clk8_a4, ensuring the
clock rate is set to 19.2MHz.
Change-Id: I92ad772c7b86652c0dc5bdc3af18a9db900d74e5
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com >
Signed-off-by: Vishvanath Singh <quic_vishvana@quicinc.com >
2025-01-20 15:13:53 +05:30
Vishvanath Singh
49f20e9cf6
Revert "ARM: dts: msm: Fake UFS Ref clock to run on HS mode"
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This reverts commit d5c176fe3bquic_vishvana@quicinc.com >
2025-01-20 15:13:30 +05:30
Vishvanath Singh
d5c176fe3b
ARM: dts: msm: Fake UFS Ref clock to run on HS mode
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Change-Id: I0045b2df13f1d6e6bcf0e4ee5c5553a7c0560807
Signed-off-by: Vishvanath Singh <quic_vishvana@quicinc.com >
2024-12-29 01:10:07 -08:00
Manish Pandey
8e42a691ce
ARM: dts: msm: Update ref_clk_src for kera UFS 2.x platforms
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Update ref_clk_src to source 19.2MHz clock to UFS 2.x Platforms.
Change-Id: I0f8a2307bc700a4eac2caa5e9ff5d0bfaac1b163
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com >
2024-12-27 23:22:01 +05:30
Manish Pandey
6cdef07bc0
ARM: dts: msm: Update UFS PHY compatible for Kera SoC
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Update Kera ufs device tree to use niobe UFS PHY driver. Hence
align with UFS SoC guide settings in HSR v19 specifications.
Change-Id: Ia83b887a2a8b49131e2141ff936ab3990700dd91
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com >
2024-11-27 22:40:19 -08:00
Manish Pandey
9c9b405454
ARM: dts: msm: Add UFS support for kera platforms
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Add UFS support for kera cdp, mtp and rcm platforms.
Change-Id: Iee003994d693a23e563e25621a23a99e85aaadac
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com >
2024-11-25 00:39:55 -08:00
