8e42a691ce
Update ref_clk_src to source 19.2MHz clock to UFS 2.x Platforms. Change-Id: I0f8a2307bc700a4eac2caa5e9ff5d0bfaac1b163 Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>
62 lines
1.6 KiB
Plaintext
62 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4-niobe";
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/* VDDA_UFS_CORE */
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vdda-phy-supply = <&L6B>;
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vdda-phy-max-microamp = <211860>;
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/* VDDA_UFS_0_1P2 */
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vdda-pll-supply = <&L4B>;
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vdda-pll-max-microamp = <18330>;
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/* Phy GDSC for VDD_MX, always on */
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vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
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/* Qref power supply, Refer Qref diagram */
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vdda-qref-supply = <&L2B>;
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vdda-qref-max-microamp = <1890>;
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clock-names = "ref_clk_src",
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"ref_aux_clk", "qref_clk",
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"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
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"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
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<&tcsrcc TCSR_UFS_CLKREF_EN>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
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<&ufs_phy_rx_symbol_0_clk>,
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<&ufs_phy_rx_symbol_1_clk>,
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<&ufs_phy_tx_symbol_0_clk>;
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status = "ok";
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};
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&ufshc_mem {
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vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
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vcc-supply = <&L12B>;
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vcc-max-microamp = <800000>;
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vccq2-supply = <&L1D>;
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vccq2-max-microamp = <750000>;
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/* VDD_PX10 is voted for the ufs_reset_n */
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qcom,vddp-ref-clk-supply = <&L3G>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq2-parent-supply = <&S1B>;
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qcom,vccq2-parent-max-microamp = <210000>;
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status = "ok";
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};
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