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dt-bindings: arm: msm: qcom,llcc: Add compatible for child node

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Child node support for SCID heuristics compatible device.

Change-Id: Id1fb1e190181d39053dce629c6807262032744ad
Signed-off-by: Avinash Philip <quic_avinashp@quicinc.com>
This commit is contained in:
Avinash Philip
2024-07-25 00:32:35 +05:30
parent 9a62421626
commit f01e170291
1 changed files with 51 additions and 12 deletions
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63
bindings/arm/msm/qcom,llcc.yaml
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@@ -9,14 +9,15 @@ title: Last Level Cache Controller
maintainers:
- Rishabh Bhatnagar <rishabhb@codeaurora.org>
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
- Avinash Philip <quic_avinashp@quicinc.com>
description: |
LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
that can be shared by multiple clients. Clients here are different cores in the
SoC, the idea is to minimize the local caches at the clients and migrate to
common pool of memory. Cache memory is divided into partitions called slices
which are assigned to clients. Clients can query the slice details, activate
and deactivate them.
LLCC (Last Level Cache Controller) provides last level of cache memory in
SoC, that can be shared by multiple clients. Clients here are different cores
in the SoC, the idea is to minimize the local caches at the clients and
migrate to common pool of memory. Cache memory is divided into partitions
called slices which are assigned to clients. Clients can query the slice
details, activate and deactivate them.
properties:
compatible:
@@ -49,11 +50,43 @@ properties:
maxItems: 1
child-node:
description: Container of llcc_perfmon node
description: |
- Container of llcc_perfmon node
- Container of scid heuristics
type: object
properties:
compatible:
const: qcom,llcc-perfmon
compatible:
items:
- const: qcom,llcc-perfmon
- const: qcom,scid-heuristics
qcom,heuristics_scid:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
SCID number of HEURISTICS SID
freq,threshold_idx:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
description: |
CPU DVFS frequency threshold index
minItems: 1
maxItems: 2
freq,threshold_residency:
$ref: '/schemas/types.yaml#/definitions/uint32-array'
description: |
CPU DVFS frequency threshold Residency value in micro seconds
minItems: 1
maxItems: 2
qcom,scid_heuristics_enabled:
description: |
On enabling this flag, Heristics driver will communicate to qcom
control software to enable the Heristics based SCID functionality.
type: boolean
required:
- compatible
additionalProperties: false
required:
- compatible
- reg
@@ -78,7 +111,7 @@ allOf:
- description: LLCC3 base register region
- description: LLCC broadcast base register region
reg-names:
items:
items:
- const: llcc0_base
- const: llcc1_base
- const: llcc2_base
@@ -89,8 +122,6 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -107,5 +138,13 @@ examples:
llcc_perfmon {
compatible = "qcom,llcc-perfmon";
}
scid_heuristics {
compatible = "qcom,scid-heuristics";
qcom,heuristics_scid = <32>;
freq,threshold_idx = <11>, <10>;
freq,threshold_residency = <5000>, <5000>;
qcom,scid_heuristics_enabled;
};
};
};