From f01e170291a5b66111731c5d851ec63289725003 Mon Sep 17 00:00:00 2001
From: Avinash Philip <quic_avinashp@quicinc.com>
Date: Thu, 25 Jul 2024 00:32:35 +0530
Subject: [PATCH] dt-bindings: arm: msm: qcom,llcc: Add compatible for child
 node

Child node support for SCID heuristics compatible device.

Change-Id: Id1fb1e190181d39053dce629c6807262032744ad
Signed-off-by: Avinash Philip <quic_avinashp@quicinc.com>
---
 bindings/arm/msm/qcom,llcc.yaml | 63 ++++++++++++++++++++++++++-------
 1 file changed, 51 insertions(+), 12 deletions(-)

diff --git a/bindings/arm/msm/qcom,llcc.yaml b/bindings/arm/msm/qcom,llcc.yaml
index 20bf3c49..555eadf1 100644
--- a/bindings/arm/msm/qcom,llcc.yaml
+++ b/bindings/arm/msm/qcom,llcc.yaml
@@ -9,14 +9,15 @@ title: Last Level Cache Controller
 maintainers:
   - Rishabh Bhatnagar <rishabhb@codeaurora.org>
   - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
+  - Avinash Philip <quic_avinashp@quicinc.com>
 
 description: |
-  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
-  that can be shared by multiple clients. Clients here are different cores in the
-  SoC, the idea is to minimize the local caches at the clients and migrate to
-  common pool of memory. Cache memory is divided into partitions called slices
-  which are assigned to clients. Clients can query the slice details, activate
-  and deactivate them.
+  LLCC (Last Level Cache Controller) provides last level of cache memory in
+  SoC, that can be shared by multiple clients. Clients here are different cores
+  in the SoC, the idea is to minimize the local caches at the clients and
+  migrate to common pool of memory. Cache memory is divided into partitions
+  called slices which are assigned to clients. Clients can query the slice
+  details, activate and deactivate them.
 
 properties:
   compatible:
@@ -49,11 +50,43 @@ properties:
     maxItems: 1
 
   child-node:
-    description: Container of llcc_perfmon node
+    description: |
+      - Container of llcc_perfmon node
+      - Container of scid heuristics
     type: object
     properties:
-        compatible:
-            const: qcom,llcc-perfmon
+      compatible:
+        items:
+          - const: qcom,llcc-perfmon
+          - const: qcom,scid-heuristics
+
+      qcom,heuristics_scid:
+        $ref: '/schemas/types.yaml#/definitions/uint32'
+        description: |
+          SCID number of HEURISTICS SID
+      freq,threshold_idx:
+        $ref: '/schemas/types.yaml#/definitions/uint32-array'
+        description: |
+          CPU DVFS frequency threshold index
+        minItems: 1
+        maxItems: 2
+      freq,threshold_residency:
+        $ref: '/schemas/types.yaml#/definitions/uint32-array'
+        description: |
+          CPU DVFS frequency threshold Residency value in micro seconds
+        minItems: 1
+        maxItems: 2
+      qcom,scid_heuristics_enabled:
+        description: |
+          On enabling this flag, Heristics driver will communicate to qcom
+          control software to enable the Heristics based SCID functionality.
+        type: boolean
+
+    required:
+      - compatible
+
+    additionalProperties: false
+
 required:
   - compatible
   - reg
@@ -78,7 +111,7 @@ allOf:
             - description: LLCC3 base register region
             - description: LLCC broadcast base register region
         reg-names:
-            items:
+          items:
             - const: llcc0_base
             - const: llcc1_base
             - const: llcc2_base
@@ -89,8 +122,6 @@ additionalProperties: false
 
 examples:
   - |
-    #include <dt-bindings/interrupt-controller/arm-gic.h>
-
     soc {
         #address-cells = <2>;
         #size-cells = <2>;
@@ -107,5 +138,13 @@ examples:
             llcc_perfmon {
                 compatible = "qcom,llcc-perfmon";
             }
+
+            scid_heuristics {
+                compatible = "qcom,scid-heuristics";
+                qcom,heuristics_scid = <32>;
+                freq,threshold_idx = <11>, <10>;
+                freq,threshold_residency = <5000>, <5000>;
+                qcom,scid_heuristics_enabled;
+            };
         };
     };