samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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ARM: dts: msm: Fix the base addresses of LLCC banks for Pineapple SoC

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Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address
used for accessing LLCC banks"), the devicetree needs to be updated with
LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end
LLCC broadcast.

Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d
Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
This commit is contained in:
Unnathi Chalicheemala
2023-09-29 12:18:44 -07:00
parent 989e04083d
commit d9c5c5ed56
1 changed files with 5 additions and 2 deletions
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7
qcom/pineapple.dtsi
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@@ -1816,8 +1816,11 @@
cache-controller@25000000 { cache-controller@25000000 {
compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; compatible = "qcom,pineapple-llcc", "qcom,llcc-v50";
reg = <0x25000000 0x800000> , <0x25800000 0x200000>; reg = <0x25000000 0x200000>, <0x25400000 0x200000>,
reg-names = "llcc_base", "llcc_broadcast_base"; <0x25200000 0x200000>, <0x25600000 0x200000>,
<0x25800000 0x200000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse; cap-based-alloc-and-pwr-collapse;