From d9c5c5ed569598f4a6422dd9a91c4ea8d82c2ccf Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Fri, 29 Sep 2023 12:18:44 -0700 Subject: [PATCH] ARM: dts: msm: Fix the base addresses of LLCC banks for Pineapple SoC Based on upstream commit ee13b50 ("qcom: llcc/edac: Fix the base address used for accessing LLCC banks"), the devicetree needs to be updated with LLCC bank 0 through 3, instead of just the start LLCC bank 0 and the end LLCC broadcast. Change-Id: I7c2b62697721074660c6b7371e0d2b1bf195ba5d Signed-off-by: Unnathi Chalicheemala --- qcom/pineapple.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qcom/pineapple.dtsi b/qcom/pineapple.dtsi index fc538b83..177acf96 100644 --- a/qcom/pineapple.dtsi +++ b/qcom/pineapple.dtsi @@ -1816,8 +1816,11 @@ cache-controller@25000000 { compatible = "qcom,pineapple-llcc", "qcom,llcc-v50"; - reg = <0x25000000 0x800000> , <0x25800000 0x200000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0x25000000 0x200000>, <0x25400000 0x200000>, + <0x25200000 0x200000>, <0x25600000 0x200000>, + <0x25800000 0x200000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; cap-based-alloc-and-pwr-collapse;