samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
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Merge changes Ica46af01,I0f8a2307,I93d85e4b,If01f876b,I3fd06bb2 into kernel.lnx.6.6.r1-rel

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* changes:
  ARM: dts: msm: Add High Speed USB support on Kera
  ARM: dts: msm: Update ref_clk_src for kera UFS 2.x platforms
  ARM: dts: msm: add trusted touch properties for kera
  ARM: dts: msm: Update dispcc clock node as GenPD provider on Kera
  dt-bindings: clock: qcom: add the DISPCC binding for kera
This commit is contained in:
Linux Build Service Account
2024-12-27 10:37:35 -08:00
committed by Gerrit - the friendly Code Review server
parent e659a47fcc 4fabf45b25
commit d8032c8122
7 changed files with 75 additions and 4 deletions
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1
bindings/clock/qcom,dispcc-sm8x50.yaml
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@@ -32,6 +32,7 @@ properties:
- qcom,sun-dispcc
- qcom,tuna-dispcc
- qcom,tuna-dispcc-v1
- qcom,kera-dispcc
clocks:
items:

8
qcom/kera-rumi.dtsi
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@@ -172,3 +172,11 @@
&video_cc_mvs0c_gdsc {
status = "ok";
};
&disp_cc_mdss_core_gdsc {
status = "ok";
};
&disp_cc_mdss_core_int2_gdsc {
status = "ok";
};

2
qcom/kera-usb.dtsi
View File

@@ -73,7 +73,7 @@
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>;
usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;

23
qcom/kera-vm-cdp.dtsi
View File

@@ -5,3 +5,26 @@
&soc {
};
&qupv3_se8_spi {
status = "ok";
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "tvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <653>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
&tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>;
};
};

23
qcom/kera-vm-mtp.dtsi
View File

@@ -5,3 +5,26 @@
&soc {
};
&qupv3_se8_spi {
status = "ok";
goodix-berlin@0 {
compatible = "goodix,gt9916S";
reg = <0>;
spi-max-frequency = <1000000>;
goodix,panel-max-x = <1080>;
goodix,panel-max-y = <2400>;
goodix,panel-max-w = <255>;
goodix,panel-max-p = <4096>;
goodix,touch-type = "primary";
goodix,qts_en;
qts,trusted-touch-mode = "vm_mode";
qts,touch-environment = "tvm";
qts,trusted-touch-type = "primary";
qts,trusted-touch-spi-irq = <653>;
qts,trusted-touch-io-bases = <0xa90000>;
qts,trusted-touch-io-sizes = <0x1000>;
qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0
&tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>;
};
};

5
qcom/kera.dtsi
View File

@@ -1798,7 +1798,7 @@
};
dispcc: clock-controller@af00000 {
compatible = "qcom,tuna-dispcc", "syscon";
compatible = "qcom,kera-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_CX_LEVEL>;
@@ -1814,6 +1814,7 @@
qcom,disp_crm-crmc = <&dispcc_crm>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
gcc: clock-controller@100000 {
@@ -3163,13 +3164,11 @@
&disp_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&disp_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_0_gdsc {

17
qcom/kera_ufs2.dtsi
View File

@@ -2,6 +2,9 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-kera.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-niobe";
@@ -21,6 +24,20 @@
vdda-qref-supply = <&L2B>;
vdda-qref-max-microamp = <1890>;
clock-names = "ref_clk_src",
"ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>;
status = "ok";
};