diff --git a/bindings/clock/qcom,dispcc-sm8x50.yaml b/bindings/clock/qcom,dispcc-sm8x50.yaml index 0d15434e..4c5564e3 100644 --- a/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -32,6 +32,7 @@ properties: - qcom,sun-dispcc - qcom,tuna-dispcc - qcom,tuna-dispcc-v1 + - qcom,kera-dispcc clocks: items: diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 76d7f98c..e05aabe2 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -172,3 +172,11 @@ &video_cc_mvs0c_gdsc { status = "ok"; }; + +&disp_cc_mdss_core_gdsc { + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + status = "ok"; +}; diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index 60032b6f..8e6f20b2 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -73,7 +73,7 @@ dma-coherent; interrupts = ; - usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>; + usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; diff --git a/qcom/kera-vm-cdp.dtsi b/qcom/kera-vm-cdp.dtsi index 1510613d..10bb9113 100644 --- a/qcom/kera-vm-cdp.dtsi +++ b/qcom/kera-vm-cdp.dtsi @@ -5,3 +5,26 @@ &soc { }; + +&qupv3_se8_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/kera-vm-mtp.dtsi b/qcom/kera-vm-mtp.dtsi index 1510613d..10bb9113 100644 --- a/qcom/kera-vm-mtp.dtsi +++ b/qcom/kera-vm-mtp.dtsi @@ -5,3 +5,26 @@ &soc { }; + +&qupv3_se8_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <653>; + qts,trusted-touch-io-bases = <0xa90000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 0 0 &tlmm 1 0 &tlmm 2 0 + &tlmm 3 0 &tlmm 16 0 &tlmm 13 0x2008>; + }; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index ac2ac1de..efcb4f6d 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1798,7 +1798,7 @@ }; dispcc: clock-controller@af00000 { - compatible = "qcom,tuna-dispcc", "syscon"; + compatible = "qcom,kera-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_CX_LEVEL>; @@ -1814,6 +1814,7 @@ qcom,disp_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; gcc: clock-controller@100000 { @@ -3163,13 +3164,11 @@ &disp_cc_mdss_core_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gcc_pcie_0_gdsc { diff --git a/qcom/kera_ufs2.dtsi b/qcom/kera_ufs2.dtsi index 1ed18475..320ed23f 100644 --- a/qcom/kera_ufs2.dtsi +++ b/qcom/kera_ufs2.dtsi @@ -2,6 +2,9 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include +#include &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-niobe"; @@ -21,6 +24,20 @@ vdda-qref-supply = <&L2B>; vdda-qref-max-microamp = <1890>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + status = "ok"; };