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ARM: dts: msm: correct soccp-config offset for Sun SOC

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SOCCP sleep status register is incorrectly set to 0x9a000, correct it.

Change-Id: I8533e9788614dbb4862ddd272caee7e76b96ed7e
Signed-off-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
This commit is contained in:
Satya Durga Srinivasu Prabhala
2023-12-22 10:21:40 -08:00
parent 9217c2fa76
commit d6149c4ac6
1 changed files with 1 additions and 1 deletions
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qcom/sun.dtsi
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@@ -3210,7 +3210,7 @@
clock-names = "xo";
memory-region = <&soccp_mem 0>;
soccp-config = <&tcsr 0x9a000>;
soccp-config = <&tcsr 0x1a000>;
/* Inputs from SOCCP */
interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,