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Merge "ARM: dts: msm: Move SDC2 core_reset to tuna SoC dtsi"

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This commit is contained in:
QCTECMDR Service
2024-10-21 17:07:19 -07:00
committed by Gerrit - the friendly Code Review server
parent d1b840cb53 777901812f
commit d4df8fb626
4 changed files with 3 additions and 12 deletions
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4
qcom/tuna-cdp.dtsi
View File

@@ -4,7 +4,6 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
&qupv3_se4_i2c {
#address-cells = <1>;
@@ -102,9 +101,6 @@
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";

4
qcom/tuna-mtp.dtsi
View File

@@ -4,7 +4,6 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
&qupv3_se4_i2c {
#address-cells = <1>;
@@ -102,9 +101,6 @@
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";

4
qcom/tuna-qrd.dtsi
View File

@@ -3,7 +3,6 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/interrupt-controller/irq.h>
&qupv3_se4_spi {
@@ -113,9 +112,6 @@
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";

3
qcom/tuna.dtsi
View File

@@ -2071,6 +2071,9 @@
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qos0 {
mask = <0xc0>;
vote = <44>;