ARM: dts: msm: Move SDC2 core_reset to tuna SoC dtsi

Move core_reset for SDC2 from platform-specific files to the tuna SoC.
This change ensures that the reset properties are managed centrally in
the SoC file, reducing redundancy and improving maintainability.

Change-Id: If8e6bcdac9b05275d20f1d205dfc7e6461d39b72
Signed-off-by: Manish Pandey <quic_mapa@quicinc.com>

qcom/tuna-cdp.dtsi

@@ -4,7 +4,6 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,gcc-sun.h>
 
 &qupv3_se4_i2c {
 	#address-cells = <1>;
@@ -102,9 +101,6 @@
 
 	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
 
-	resets = <&gcc GCC_SDCC2_BCR>;
-	reset-names = "core_reset";
-
 	qcom,uses_level_shifter;
 
 	status = "ok";

qcom/tuna-mtp.dtsi

@@ -4,7 +4,6 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,gcc-sun.h>
 
 &qupv3_se4_i2c {
 	#address-cells = <1>;
@@ -102,9 +101,6 @@
 
 	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
 
-	resets = <&gcc GCC_SDCC2_BCR>;
-	reset-names = "core_reset";
-
 	qcom,uses_level_shifter;
 
 	status = "ok";

qcom/tuna-qrd.dtsi

@@ -3,7 +3,6 @@
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,gcc-sun.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 &qupv3_se4_spi {
@@ -113,9 +112,6 @@
 
 	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
 
-	resets = <&gcc GCC_SDCC2_BCR>;
-	reset-names = "core_reset";
-
 	qcom,uses_level_shifter;
 
 	status = "ok";

qcom/tuna.dtsi

@@ -2070,6 +2070,9 @@
 		interconnect-names = "sdhc-ddr","cpu-sdhc";
 		operating-points-v2 = <&sdhc2_opp_table>;
 
+		resets = <&gcc GCC_SDCC2_BCR>;
+		reset-names = "core_reset";
+
 		qos0 {
 			mask = <0xc0>;
 			vote = <44>;