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Merge "ARM: dts: msm: Add clock handles to CPU nodes for Sun"

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qctecmdr
2023-12-04 12:16:20 -08:00
committed by Gerrit - the friendly Code Review server
parent 9eabd511d3 37eecd0a8c
commit cb7bf25fb1
1 changed files with 8 additions and 0 deletions
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8
qcom/sun.dtsi
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@@ -63,6 +63,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
L2_0: l2-cache { L2_0: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
cache-level = <2>; cache-level = <2>;
@@ -81,6 +82,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU2: cpu@200 { CPU2: cpu@200 {
@@ -95,6 +97,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU3: cpu@300 { CPU3: cpu@300 {
@@ -109,6 +112,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU4: cpu@400 { CPU4: cpu@400 {
@@ -123,6 +127,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU5: cpu@500 { CPU5: cpu@500 {
@@ -137,6 +142,7 @@
capacity-dmips-mhz = <1792>; capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>; dynamic-power-coefficient = <238>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
clocks = <&scmi_perf 0>;
}; };
CPU6: cpu@10000 { CPU6: cpu@10000 {
@@ -151,6 +157,7 @@
capacity-dmips-mhz = <1894>; capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>; dynamic-power-coefficient = <588>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
clocks = <&scmi_perf 1>;
L2_6: l2-cache { L2_6: l2-cache {
compatible = "arm,arch-cache"; compatible = "arm,arch-cache";
cache-level = <2>; cache-level = <2>;
@@ -169,6 +176,7 @@
capacity-dmips-mhz = <1894>; capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>; dynamic-power-coefficient = <588>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
clocks = <&scmi_perf 1>;
}; };
cpu-map { cpu-map {