From 37eecd0a8c9beb5b9aa77bda89490ffe89ab2ab3 Mon Sep 17 00:00:00 2001
From: Vivek Aknurwar <quic_viveka@quicinc.com>
Date: Tue, 26 Sep 2023 12:04:31 -0700
Subject: [PATCH] ARM: dts: msm: Add clock handles to CPU nodes for Sun

Add clock handles to CPU nodes to enable frequency domains for cpus.

Change-Id: I77dc5dbedbe7704d392c58913647beaa36571872
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
---
 qcom/sun.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index dea5b1b6..97c49acd 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -54,6 +54,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -66,6 +67,7 @@
 			reg = <0x0 0x100>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU2: cpu@200 {
@@ -74,6 +76,7 @@
 			reg = <0x0 0x200>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU3: cpu@300 {
@@ -82,6 +85,7 @@
 			reg = <0x0 0x300>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU4: cpu@400 {
@@ -90,6 +94,7 @@
 			reg = <0x0 0x400>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU5: cpu@500 {
@@ -98,6 +103,7 @@
 			reg = <0x0 0x500>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU6: cpu@10000 {
@@ -106,6 +112,7 @@
 			reg = <0x0 0x10000>;
 			enable-method = "psci";
 			next-level-cache = <&L2_6>;
+			clocks = <&scmi_perf 1>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -118,6 +125,7 @@
 			reg = <0x0 0x10100>;
 			enable-method = "psci";
 			next-level-cache = <&L2_6>;
+			clocks = <&scmi_perf 1>;
 		};
 
 		cpu-map {