diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index e61a5455..b0df993d 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -63,6 +63,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -81,6 +82,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU2: cpu@200 {
@@ -95,6 +97,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU3: cpu@300 {
@@ -109,6 +112,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU4: cpu@400 {
@@ -123,6 +127,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU5: cpu@500 {
@@ -137,6 +142,7 @@
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 			next-level-cache = <&L2_0>;
+			clocks = <&scmi_perf 0>;
 		};
 
 		CPU6: cpu@10000 {
@@ -151,6 +157,7 @@
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <588>;
 			next-level-cache = <&L2_6>;
+			clocks = <&scmi_perf 1>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -169,6 +176,7 @@
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <588>;
 			next-level-cache = <&L2_6>;
+			clocks = <&scmi_perf 1>;
 		};
 
 		cpu-map {