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Change-Id: Idb500f314025d7e8569f9574aa70ee7f42591912
This commit is contained in:
Linux Build Service Account
2025-04-02 01:08:42 -07:00
parent 4b053c109a 7dc162272f
commit c99076b99c
27 changed files with 1509 additions and 13 deletions
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64
bindings/arm/arm,arch-cache.yaml Normal file
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@@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,arch-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Architectural Cache Properties
maintainers:
- Asit Shah <quic_asitshah@quicinc.com>
description: |
Device tree binding for ARM architecture-level cache description.
This is typically used to describe system-wide cache properties
that are not specific to a single CPU core.
properties:
compatible:
enum:
- "arm,arch-cache"
cache-level:
description: The cache level (L1, L2, etc.).
$ref: /schemas/types.yaml#/definitions/uint32
cache-size:
description: Total size of the cache in bytes.
$ref: /schemas/types.yaml#/definitions/uint32
cache-line-size:
description: Cache line size in bytes.
$ref: /schemas/types.yaml#/definitions/uint32
cache-sets:
description: Number of cache sets.
$ref: /schemas/types.yaml#/definitions/uint32
cache-type:
description: Cache type (e.g., "unified", "instruction", "data").
enum:
- "unified"
- "instruction"
- "data"
required:
- compatible
- cache-level
- cache-size
- cache-line-size
- cache-sets
- cache-type
additionalProperties: false
examples:
- |
cache-controller {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <524288>; /* 512 KB */
cache-line-size = <64>; /* 64 bytes */
cache-sets = <512>;
cache-type = "unified";
};

15
bindings/arm/msm/msm.yaml
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@@ -205,4 +205,19 @@ properties:
- qcom,wdp
- const: qcom,monacop
- description: Qualcomm Technologies, Inc. QCS610
items:
- enum:
- qcom,qcs610-iot
- qcom,iot
- qcom,qcs610-ipc
- qcom,ipc
- qcom,qcs610-opk
- qcom,opk
- const: qcom,qcs610
- description: Qualcomm Technologies, Inc. SM6150
items:
- const: qcom,sm6150
additionalProperties: true

53
bindings/edac/kryo-edac.yaml Normal file
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@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/edac/kryo-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Kryo EDAC(Error Detection and Correction) node binding
maintainers:
- Murali Nalajala <mnalajal@quicinc.com>
description: |+
Kryo EDAC node is defined to describe on-chip error detection and correction
for the Kryo core.
Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers:
ERRXSTATUS - Error Record Primary Status Register
ERRXMISC0 - Error Record Miscellaneous Register
Current implementation of Kryo ECC mechanism is based on interrupts.
The following section describes the DT node binding for kryo_cpu_erp.
properties:
compatible:
const: arm,arm64-kryo-cpu-erp
description:
Implements cache error detection and correction for Kryo CPUs.
interrupts:
description: Interrupt-specifier for L1/L2, L3/SCU error IRQ(s)
interrupt-names:
description: Descriptive names of the interrupts
required:
- compatible
- interrupts
- interrupt-names
examples:
- |
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq",
"l1-l2-errirq",
"l3-scu-errirq",
"l3-scu-faultirq";
};

1
bindings/interrupt-controller/qcom,pdc.yaml
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@@ -39,6 +39,7 @@ properties:
- qcom,ravelin-pdc
- qcom,tuna-pdc
- qcom,kera-pdc
- qcom,sm6150-pdc
- const: qcom,pdc
reg:

467
bindings/pci/qcom,msm-ep-pcie.yaml Normal file
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@@ -0,0 +1,467 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,msm-ep-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. (QTI) MSM PCI express Endpoint Controller
maintainers:
- Anvita T <quic_atadepal@quicinc.com>
properties:
compatible:
enum:
- qcom,pcie-ep
reg:
minItems: 7
items:
- description: PCIe MSM MSI address reserved space
- description: DesignWare PCIe core (dm_core) registers
- description: External local bus interface (elbi) registers
- description: Address Translation Unit (ATU) registers
- description: PCIe MSM specific (parf) registers
- description: PCIe Physical layer (phy) registers
- description: BAR memory region
- description: PCIe MSM MSI address reserved space for vf
- description: DesignWare PCIe core (dm_core) registers for vf
- description: DesignWare PCIe EDMA registers
- description: Register to avoid device reset during host reboot
- description: AOSS reset clear register
- description: PCIe RUMI (rumi) registers
reg-names:
minItems: 7
items:
- const: msi
- const: dm_core
- const: elbi
- const: iatu
- const: parf
- const: phy
- const: mmio
- const: msi_vf
- const: dm_core_vf
- const: edma
- const: tcsr_pcie_perst_en
- const: aoss_cc_reset
- const: rumi
interrupts:
minItems: 1
items:
- description: PCIe Global interrupt
- description: PCIe PME turnoff interrupt
- description: PCIe Dstate change interrupt
- description: PCIe L1ss timeout interrupt
- description: PCIe Link up interrupt
- description: PCIe Likk down interrupt
- description: PCIe bridge flush interrupt
- description: PCIe BME interrupt
interrupt-names:
minItems: 1
items:
- const: int_global
- const: int_pm_turnoff
- const: int_dstate_change
- const: int_l1sub_timeout
- const: int_link_up
- const: int_link_down
- const: int_bridge_flush_n
- const: int_bme
pinctrl-names:
description: GPIO configuration at the init time.
items:
- const: default
pinctrl-0:
description: Should contain default pinctrl.
perst-gpio:
description: GPIO used as PERST# input signal
maxItems: 1
wake-gpio:
description: GPIO used as WAKE# output signal
maxItems: 1
clkreq-gpio:
description: GPIO used to wake system in L1ss sleep
maxItems: 1
mdm2apstatus-gpio:
description: GPIO used to indicate mdm to ap status
maxItems: 1
gdsc-vdd-supply:
description: A phandle to the core gdsc power supply
gdsc-phy-vdd-supply:
description: A phandle to the phy gdsc power supply
vreg-1p2-supply:
description: A phandle to the 1.2v power supply
vreg-0p9-supply:
description: A phandle to the 0.9v power supply
vreg-qref-supply:
description: A phandle to the qref power supply
vreg-mx-supply:
description: A phandle to the mx power supply
vreg-cx-supply:
description: A phandle to the cx power supply
qcom,vreg-1p2-voltage-level:
description: Array containing the min, max supported voltage and current for 1.2v power supply.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,vreg-0p9-voltage-level:
description: Array containing the min, max supported voltage and current for 0.9v power supply.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,vreg-qref-voltage-level:
description: Array containing the min, max supported voltage and current for qref power supply.
$ref: /schemas/types.yaml#/definitions/uint32-array
resets:
maxItems: 2
reset-names:
items:
- const: pcie_core_reset
- const: pcie_phy_reset
interconnects:
maxItems: 1
interconnect-names:
items:
- const: icc_path
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
clocks:
description: Phandles to the clocks.
minItems: 1
maxItems: 14
anyOf:
- items:
- description: PCIe PIPE clock
- description: PCIe reference clock source
- description: PCIe Auxiliary clock
- description: PCIe CFG AHB clock
- description: PCIe Master AXI clock
- description: PCIe Slave AXI clock
- description: PCIe low dropout regulator clock
- description: PCIe Slave Q2A AXI clock
- description: PCIe DDRS SF translational buffer unit clock
- description: PCIe aggregation NoC AXI clock
- description: PCIe CNOC SF AXI clock
- description: PCIe Multiplexer clock for the PIPE clock
- description: PCIe external source PIPE clock
- description: PCIe PHY Auxiliary clock
clock-names:
description: Names of the clocks.
minItems: 1
maxItems: 14
anyOf:
- items:
- const: pcie_pipe_clk
- const: pcie_0_ref_clk_src
- const: pcie_aux_clk
- const: pcie_cfg_ahb_clk
- const: pcie_mstr_axi_clk
- const: pcie_slv_axi_clk
- const: pcie_ldo
- const: pcie_slv_q2a_axi_clk
- const: pcie_ddrss_sf_tbu_clk
- const: pcie_aggre_noc_0_axi_clk
- const: gcc_cnoc_pcie_sf_axi_clk
- const: pcie_pipe_clk_mux
- const: pcie_pipe_clk_ext_src
- const: pcie_phy_aux_clk
qcom,pcie-vendor-id:
description: Vendor ID of the endpoint to be exposed
qcom,pcie-device-id:
description: Device ID of the endpoint to be exposed
qcom,pcie-link-speed:
description: This will override the max Gen speed
- 0x1 GEN1
- 0x2 GEN2
- 0x3 GEN3
- 0x4 GEN4
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
qcom,pcie-phy-ver:
description: States the PCIe PHY HSR version.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,no-path-from-ipa-to-pcie:
description: This will configure iatu for IPA transactions as there is no
direct path from the IPA to PCIe.
type: boolean
qcom,pcie-aggregated-irq:
description: This will configure iatu for IPA transactions as there is no
direct path from the IPA to PCIe.
type: boolean
qcom,pcie-mhi-a7-irq:
description: This will configure iatu for IPA transactions as there is no
direct path from the IPA to PCIe.
type: boolean
qcom,tcsr-not-supported:
description: This will configure iatu for IPA transactions as there is no
direct path from the IPA to PCIe.
type: boolean
qcom,phy-status-reg2:
description: Offset from PCIe PHY base to check the PCIe PHY status.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,mhi-soc-reset-offset:
description: Offset from PCIe PHY base to check the PCIe PHY status.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,aux-clk:
description: This sets the aux clock frequency value.
$ref: /schemas/types.yaml#/definitions/uint32
iommu-map:
description: As described in the pci-iommu.txt.
maxItems: 1
qcom,phy-init:
description: PCIe PHY initialization sequence.
$ref: /schemas/types.yaml#/definitions/uint32-array
'#address-cells':
description: Should provide a value of 0.
$ref: /schemas/types.yaml#/definitions/uint32
'#interrupt-cells':
description: Should provide a value of 1.
$ref: /schemas/types.yaml#/definitions/uint32
'#interrupt-map-mask':
description: should provide a value of 0xffffffff.
$ref: /schemas/types.yaml#/definitions/uint32
interrupt-map:
description: Must create mapping for the number of interrupts
that are defined in above interrupts property.
For PCIe device node, it should define 6 mappings for
the corresponding PCIe interrupts supporting the
specification.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,vreg-mx-voltage-level:
description: Support PCIe Gen4 on sdxlemur by scaling MX to
appropriate voltage.
$ref: /schemas/types.yaml#/definitions/uint32
max-clock-frequency-hz:
description: list of the maximum operating frequencies stored
in the same order of clock names.
qcom,tcsr-perst-separation-enable-offset:
description: Offset for TCSR perst seperation enable.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,tcsr-reset-separation-offset:
description: Offset for TCSR reset seperation.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,tcsr-perst-enable-offset:
description: Offset for TCSR perst enable.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,tcsr-hot-reset-offset:
description: Offset for TCSR hot reset enable.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,perst-raw-rst-status-b:
description: Bit for perset raw reset status.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,dbi-base-reg:
description: Register offset for DBI base address.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,slv-space-reg:
description: Register offset for slave address space size.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pcie-active-config:
description: active configuration of PCIe addressing.
type: boolean
qcom,pcie-edma:
description: edma usage for PCIe.
type: boolean
qcom,pcie-cesta-clkreq-offset:
description: Offset from PCIe PARF base to PCIe CESTA CLKREQ register.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pcie-perst-enum:
description: Link enumeration will be triggered by PERST deassertion.
type: boolean
qcom,pcie-m2-autonomous:
description: Enable L1ss sleep/exit to support M2 autonomous mode.
type: boolean
qcom,override-disable-sriov:
description: Set to report as SRIOV capability disable with client (MHI) driver.
type: boolean
nvmem-cells:
description: Phandle of nvmem cell containing the address for boot_config.
$ref: /schemas/types.yaml#/definitions/phandle-array
nvmem-cell-names:
description: nvmem cell name for boot_config.
$ref: /schemas/types.yaml#/definitions/string-array
qcom,fast-boot-mask:
description: Bitmask to read fast_boot value from boot_config cell.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,host-bypass-mask:
description: Bitmask to read host_bypass value from boot_config cell.
Will work only when host_bypass is 1 bit in boot_config.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,fast-boot-values:
description: fast_boot values to check against boot_config based value for confirming
that host-interface is PCIe.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,ep-pcie-num-ipc-pages-dev-fac:
description: If property is present reduce the ep pcie ipc logging size
based on the divisor factor. This property also represents the divisor factor.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pcie-sm-sequence:
description: PCIe State Manager sequence.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,pcie-sm-branch-sequence:
description: PCIe state manager branch sequence.
$ref: /schemas/types.yaml#/definitions/uint32-array
qcom,pcie-sm-branch-offset:
description: Offset from PCIe state manager base to load the branch sequence.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pcie-sm-start-offset:
description: Offset from PCIe state manager base to start/enable the state manager.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,pcie-disconnect-req-reg-b:
description: It specifies the register responsible for handling PCIe disconnect requests.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,aoss-rst-clr:
description: If present, indicates that the reset clear signal is enabled.
It is used to clear and write reset signals to the specified register within the AOSS.
type: boolean
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- pinctrl-names
- pinctrl-0
- perst-gpio
- wake-gpio
- resets
- reset-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
pcie_ep: qcom,pcie@bfffd000 {
compatible = "qcom,pcie-ep";
reg = <0xbfffd000 0x1000>,
<0xbfffe000 0x1000>,
<0xbffff000 0x1000>,
<0xfc520000 0x2000>,
<0xfc526000 0x1000>,
<0xfc527000 0x1000>,
<0x01fcb000 0x1000>;
reg-names = "msi", "dm_core", "elbi", "parf", "phy", "mmio",
"tcsr_pcie_perst";
#address-cells = <0>;
interrupt-parent = <&pcie_ep>;
interrupts = <0 1 2 3 4 5>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 44 0
1 &intc 0 46 0
2 &intc 0 47 0
3 &intc 0 50 0
4 &intc 0 51 0
5 &intc 0 52 0>;
interrupt-names = "int_pm_turnoff", "int_dstate_change",
"int_l1sub_timeout", "int_link_up",
"int_link_down", "int_bridge_flush_n";
perst-gpio = <&msmgpio 65 0>;
wake-gpio = <&msmgpio 61 0>;
clkreq-gpio = <&msmgpio 64 0>;
mdm2apstatus-gpio = <&tlmm_pinmux 16 0>;
gdsc-vdd-supply = <&gdsc_pcie_0>;
vreg-1.8-supply = <&pmd9635_l8>;
vreg-0.9-supply = <&pmd9635_l4>;
qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
qcom,vreg-0.9-voltage-level = <950000 950000 24000>;
clock-names = "pcie_pipe_clk",
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_ldo";
max-clock-frequency-hz = <62500000>, <1000000>,
<0>, <0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_BCR>,
<&clock_gcc GCC_PCIE_PHY_BCR>;
reset-names = "pcie_core_reset", "pcie_phy_reset";
qcom,pcie-link-speed = <1>;
qcom,pcie-active-config;
qcom,pcie-aggregated-irq;
qcom,pcie-mhi-a7-irq;
qcom,pcie-perst-enum;
qcom,phy-status-reg = <0x728>;
qcom,dbi-base-reg = <0x168>;
qcom,slv-space-reg = <0x16c>;
qcom,phy-init = <0x604 0x03 0x0 0x1
0x048 0x08 0x0 0x1
0x64c 0x4d 0x0 0x1
0x600 0x00 0x0 0x1
};

12
qcom/Makefile
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@@ -112,6 +112,18 @@ sun-overlays-dtb-$(CONFIG_ARCH_KERA) += $(KERA_BOARDS) $(NOAPQ_KERA_BOARDS) $(KE
dtb-y += $(sun-dtb-y)
QCS610_BASE_DTB += qcs610.dtb
QCS610_BOARDS += \
qcs610-iot-overlay.dtbo \
qcs610-ipc-overlay.dtbo \
qcs610-opk-overlay.dtbo
qcs610-dtb-$(CONFIG_ARCH_SM6150) += \
$(call add-overlays, $(QCS610_BOARDS),$(QCS610_BASE_DTB))
qcs610-overlays-dtb-$(CONFIG_ARCH_SM6150) += $(QCS610_BOARDS) $(QCS610_BASE_DTB)
dtb-y += $(qcs610-dtb-y)
PINEAPPLE_BASE_DTB += pineapple.dtb pineapple-v2.dtb
PINEAPPLE_APQ_BASE_DTB += pineapplep.dtb pineapplep-v2.dtb

2
qcom/kera-reserved-memory.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&reserved_memory {

2
qcom/kera.dtsi
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@@ -3295,7 +3295,7 @@
qcom,sampling-enabled;
qcom,cpufreq-memfreq-tbl =
< 441600 364800 >,
< 595200 556800 >,
< 595200 518400 >,
< 787200 710400 >,
< 902400 806400 >,
< 1113600 998400 >,

12
qcom/platform_map.bzl
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@@ -127,6 +127,18 @@ _platform_map = {
],
"binary_compatible_with": ["tuna", "kera"],
},
"qcs610": {
"dtb_list": [
# keep sorted
{"name": "qcs610.dtb"},
],
"dtbo_list": [
# keep sorted
{"name": "qcs610-iot-overlay.dtbo"},
{"name": "qcs610-ipc-overlay.dtbo"},
{"name": "qcs610-opk-overlay.dtbo"},
],
},
"tuna": {
"dtb_list": [
{"name": "tuna.dtb"},

15
qcom/qcs610-iot-overlay.dts Normal file
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT Overlay";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 0>;
};

10
qcom/qcs610-iot.dtsi Normal file
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 0>;
};

16
qcom/qcs610-ipc-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-ipc.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT IPC";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 1>;
};

12
qcom/qcs610-ipc.dtsi Normal file
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@@ -0,0 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "qcs610-iot.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 IPC";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 1>;
};

16
qcom/qcs610-opk-overlay.dts Normal file
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@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "qcs610-opk.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Openkit Overlay";
compatible = "qcom,qcs610-opk", "qcom,qcs610", "qcom,opk";
qcom,msm-id = <401 0x0>;
qcom,board-id = <32 3>;
};

14
qcom/qcs610-opk.dtsi Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qualcomm Technologies, Inc. QCS610 IOT";
compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot";
qcom,board-id = <32 0>;
};

14
qcom/qcs610.dts Normal file
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@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "qcs610.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610 SoC";
compatible = "qcom,qcs610";
qcom,board-id = <0 0>;
};

12
qcom/qcs610.dtsi Normal file
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@@ -0,0 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sm6150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS610";
qcom,msm-name = "QCS610";
qcom,msm-id = <401 0>;
};

568
qcom/sm6150.dtsi Normal file
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@@ -0,0 +1,568 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
model = "Qualcomm Technologies, Inc. SM6150";
compatible = "qcom,sm6150";
qcom,msm-name = "SM6150";
qcom,msm-id = <355 0x0>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=2M earlycon=msm_geni_serial,0x880000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
aliases: aliases { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
};
cluster1 {
core0 {
cpu = <&CPU6>;
};
core1 {
cpu = <&CPU7>;
};
};
};
};
soc: soc { };
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_region: hyp_region@85700000 {
no-map;
reg = <0x0 0x85700000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@85e00000 {
no-map;
reg = <0x0 0x85e00000 0x0 0x120000>;
};
aop_cmd_db: memory@85f20000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85f20000 0x0 0x20000>;
no-map;
};
sec_apps_mem: sec_apps_region@85fff000 {
no-map;
reg = <0x0 0x85fff000 0x0 0x1000>;
};
smem_region: smem@86000000 {
no-map;
reg = <0x0 0x86000000 0x0 0x200000>;
};
removed_region: removed_region@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x2d00000>;
};
pil_camera_mem: camera_region@8ab00000 {
no-map;
reg = <0x0 0x8ab00000 0x0 0x500000>;
};
pil_modem_mem: modem_region@8b000000 {
no-map;
reg = <0x0 0x8b000000 0x0 0x8400000>;
};
pil_video_mem: pil_video_region@93400000 {
no-map;
reg = <0x0 0x93400000 0x0 0x500000>;
};
wlan_msa_mem: wlan_msa_region@93900000 {
no-map;
reg = <0x0 0x93900000 0x0 0x200000>;
};
pil_cdsp_mem: cdsp_regions@93b00000 {
no-map;
reg = <0x0 0x93b00000 0x0 0x1e00000>;
};
pil_adsp_mem: pil_adsp_region@95900000 {
no-map;
reg = <0x0 0x95900000 0x0 0x1e00000>;
};
pil_ipa_fw_mem: ips_fw_region@97700000 {
no-map;
reg = <0x0 0x97700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
no-map;
reg = <0x0 0x97710000 0x0 0x5000>;
};
pil_gpu_mem: gpu_region@97715000 {
no-map;
reg = <0x0 0x97715000 0x0 0x2000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x9e400000 0x0 0x1400000>;
};
cdsp_sec_mem: cdsp_sec_regions@9f800000 {
no-map;
reg = <0x0 0x9f800000 0x0 0x1e00000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
sdsp_mem: sdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x1000000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
reusable;
alignment = <0 0x400000>;
size = <0 0x800000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x8c00000>;
};
cont_splash_memory: splash_region {
reg = <0x0 0x9c000000 0x0 0x0f00000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_region@9cf00000 {
reg = <0x0 0x9cf00000 0x0 0x0100000>;
label = "dfps_data_region";
};
disp_rdump_memory: disp_rdump_region@9c000000 {
reg = <0x0 0x9c000000 0x0 0x01000000>;
label = "disp_rdump_region";
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
size = <0 0x2800000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x2000000>;
linux,cma-default;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,drv-count = <3>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>,
<FAST_PATH_TCS 0>;
};
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
qcom,drv-count = <1>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
disp_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x1c00>;
channel@0 {
qcom,tcs-config = <SLEEP_TCS 1>,
<WAKE_TCS 1>,
<ACTIVE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <1 9 4>;
interrupt-parent = <&intc>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6150-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 1 0xf08>,
<1 2 0xf08>,
<1 3 0xf08>,
<1 0 0xf08>;
clock-frequency = <19200000>;
};
timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 6 0x4>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
qcom_tzlog: tz-log@146aa720 {
compatible = "qcom,tz-log";
reg = <0x146aa720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq",
"l1-l2-errirq",
"l3-scu-errirq",
"l3-scu-faultirq";
};
};

8
qcom/sun.dtsi
View File

@@ -2333,15 +2333,15 @@
"ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>;
resets = <&ufshc_mem 0>;
status = "disabled";
};

60
qcom/tuna-atp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-mtp.dtsi"
@@ -14,3 +14,61 @@
&L3G {
regulator-always-on;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

60
qcom/tuna-mtp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -113,3 +113,61 @@
&usb0 {
qcom,wcd_usbss = <&wcd_usbss>;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

14
qcom/tuna-pmic-overlay.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
@@ -120,6 +120,14 @@
nvmem-names = "pon_log0", "pon_log1";
depends-on-supply = <&gh_watchdog>;
};
regulator_ocp_notifier: regulator-ocp-notifier {
compatible = "qcom,regulator-ocp-notifier";
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0x71 0x1 IRQ_TYPE_EDGE_RISING>;
nvmem-cells = <&ocp_log>;
nvmem-cell-names = "ocp_log";
};
};
&thermal_zones {
@@ -435,3 +443,7 @@
io-channels = <&pmk8550_vadc PMXR2230_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&battery_charger {
qcom,ship-mode-immediate;
};

60
qcom/tuna-qrd.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@@ -174,3 +174,61 @@
qcom,wcd_usbss = <&wcd_usbss>;
};
&regulator_ocp_notifier {
periph-1c1-supply = <&L1B>;
periph-1c2-supply = <&L2B>;
periph-1c3-supply = <&L3B>;
periph-1c4-supply = <&L4B>;
periph-1c5-supply = <&L5B>;
periph-1c6-supply = <&L6B>;
periph-1c7-supply = <&L7B>;
periph-1c8-supply = <&L8B>;
periph-1c9-supply = <&L9B>;
periph-1ca-supply = <&L10B>;
periph-1cb-supply = <&L11B>;
periph-1cc-supply = <&L12B>;
periph-1cd-supply = <&L13B>;
periph-1ce-supply = <&L14B>;
periph-1cf-supply = <&L15B>;
periph-1d0-supply = <&L16B>;
periph-1d1-supply = <&L17B>;
periph-1d2-supply = <&L18B>;
periph-1d3-supply = <&L19B>;
periph-1d4-supply = <&L20B>;
periph-1d5-supply = <&L21B>;
periph-1d6-supply = <&L22B>;
periph-1d7-supply = <&L23B>;
periph-19b-supply = <&S1B>;
periph-19e-supply = <&S2B>;
periph-1a1-supply = <&S3B>;
periph-1e4-supply = <&BOB>;
periph-3c1-supply = <&L1D>;
periph-3c2-supply = <&L2D_LEVEL>;
periph-3c3-supply = <&L3D>;
periph-59b-supply = <&S1F_LEVEL>;
periph-5a0-supply = <&S2F_LEVEL>;
periph-5a8-supply = <&S4F>;
periph-5a9-supply = <&S5F_LEVEL>;
periph-5ac-supply = <&S8F_LEVEL>;
periph-5c1-supply = <&L1F>;
periph-5c2-supply = <&L2F_LEVEL>;
periph-5c3-supply = <&L3F>;
periph-6c1-supply = <&L1G>;
periph-6c2-supply = <&L2G>;
periph-6c3-supply = <&L3G>;
periph-c40-supply = <&L1M>;
periph-c41-supply = <&L2M>;
periph-c42-supply = <&L3M>;
periph-c43-supply = <&L4M>;
periph-c44-supply = <&L5M>;
periph-c45-supply = <&L6M>;
periph-c46-supply = <&L7M>;
periph-d40-supply = <&L1N>;
periph-d41-supply = <&L2N>;
periph-d42-supply = <&L3N>;
periph-d43-supply = <&L4N>;
periph-d44-supply = <&L5N>;
periph-d45-supply = <&L6N>;
periph-d46-supply = <&L7N>;
};

4
qcom/tuna-vm-cdp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

4
qcom/tuna-vm-mtp.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

3
qcom/tuna-vm-qrd.dtsi
View File

@@ -13,6 +13,9 @@
st_fts@0 {
compatible = "st,fts";
reg = <0x0>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;

4
qcom/tuna-vm-rcm.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
@@ -13,7 +13,9 @@
st_fts@49 {
compatible = "st,fts";
reg = <0x49>;
st,irq-gpio = <&tlmm 176 0x2008>;
st,irq-flags = <8>;
st,reset-gpio = <&tlmm 189 0x00>;
st,touch-type = "primary";
st,qts_en;