59527e7b02
Add snapshot of DT bindings for kryo edac as of qcom-6.1 commit
bbed6bb2a474 ("Merge "ARM: dts: msm: Add support for
EVACC/LSRCC/VIDEOCC nodes"").
Changes:
-Add missing SPDX licence.
Change-Id: I0359dee838daa70bedc8156b36d3ed125e4195ed
Signed-off-by: Khaja Hussain Shaik Khaji <quic_kshaikkh@quicinc.com>
(cherry picked from commit 9aa68feb0b6e34cae6570cc27a01b6213243998b)
54 lines
1.5 KiB
YAML
54 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bindings/edac/kryo-edac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Kryo EDAC(Error Detection and Correction) node binding
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maintainers:
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- Murali Nalajala <mnalajal@quicinc.com>
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description: |+
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Kryo EDAC node is defined to describe on-chip error detection and correction
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for the Kryo core.
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Kryo will report all SBE and DBE found in L1/L2/L3/SCU caches in two registers:
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ERRXSTATUS - Error Record Primary Status Register
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ERRXMISC0 - Error Record Miscellaneous Register
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Current implementation of Kryo ECC mechanism is based on interrupts.
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The following section describes the DT node binding for kryo_cpu_erp.
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properties:
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compatible:
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const: arm,arm64-kryo-cpu-erp
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description:
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Implements cache error detection and correction for Kryo CPUs.
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interrupts:
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description: Interrupt-specifier for L1/L2, L3/SCU error IRQ(s)
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interrupt-names:
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description: Descriptive names of the interrupts
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required:
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- compatible
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- interrupts
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- interrupt-names
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examples:
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- |
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kryo-erp {
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compatible = "arm,arm64-kryo-cpu-erp";
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interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "l1-l2-faultirq",
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"l1-l2-errirq",
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"l3-scu-errirq",
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"l3-scu-faultirq";
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};
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