227a64ada4
Add device tree bindings for arm,arch-cache node. Change-Id: I46acfdd171e297368d6bedc431af7dd1270909f8 Signed-off-by: Asit Shah <quic_asitshah@quicinc.com>
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,arch-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Architectural Cache Properties
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maintainers:
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- Asit Shah <quic_asitshah@quicinc.com>
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description: |
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Device tree binding for ARM architecture-level cache description.
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This is typically used to describe system-wide cache properties
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that are not specific to a single CPU core.
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properties:
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compatible:
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enum:
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- "arm,arch-cache"
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cache-level:
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description: The cache level (L1, L2, etc.).
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$ref: /schemas/types.yaml#/definitions/uint32
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cache-size:
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description: Total size of the cache in bytes.
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$ref: /schemas/types.yaml#/definitions/uint32
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cache-line-size:
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description: Cache line size in bytes.
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$ref: /schemas/types.yaml#/definitions/uint32
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cache-sets:
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description: Number of cache sets.
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$ref: /schemas/types.yaml#/definitions/uint32
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cache-type:
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description: Cache type (e.g., "unified", "instruction", "data").
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enum:
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- "unified"
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- "instruction"
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- "data"
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required:
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- compatible
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- cache-level
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- cache-size
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- cache-line-size
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- cache-sets
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- cache-type
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additionalProperties: false
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examples:
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- |
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cache-controller {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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cache-size = <524288>; /* 512 KB */
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cache-line-size = <64>; /* 64 bytes */
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cache-sets = <512>;
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cache-type = "unified";
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};
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