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ARM: dts: msm: mm-drivers: support cache coherence with shared memory

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This change enables cache coherency on the carved-out memory region
shared with SOCCP.

Change-Id: If20659b1153a06e42d15105d5ee1837f0356ef04
Signed-off-by: Grace An <quic_gracan@quicinc.com>
This commit is contained in:
Grace An
2023-12-20 13:47:20 -08:00
parent 3bb27e1050
commit c2a2aa549b
1 changed files with 1 additions and 0 deletions
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hw_fence/sun-hw-fence.dtsi
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@@ -15,6 +15,7 @@
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x562 0x1>;
dma-coherent;
soccp_controller = <&soccp_pas>;
qcom,hw-fence-table-entries = <8192>;