From c2a2aa549b76b2cb3aaac0ee622944c9e9e03f01 Mon Sep 17 00:00:00 2001
From: Grace An <quic_gracan@quicinc.com>
Date: Wed, 20 Dec 2023 13:47:20 -0800
Subject: [PATCH] ARM: dts: msm: mm-drivers: support cache coherence with
 shared memory

This change enables cache coherency on the carved-out memory region
shared with SOCCP.

Change-Id: If20659b1153a06e42d15105d5ee1837f0356ef04
Signed-off-by: Grace An <quic_gracan@quicinc.com>
---
 hw_fence/sun-hw-fence.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw_fence/sun-hw-fence.dtsi b/hw_fence/sun-hw-fence.dtsi
index 38832617..e21dd763 100644
--- a/hw_fence/sun-hw-fence.dtsi
+++ b/hw_fence/sun-hw-fence.dtsi
@@ -15,6 +15,7 @@
 		interrupt-controller;
 		#interrupt-cells = <1>;
 		iommus = <&apps_smmu 0x562 0x1>;
+		dma-coherent;
 		soccp_controller = <&soccp_pas>;
 
 		qcom,hw-fence-table-entries = <8192>;