c2a2aa549b
This change enables cache coherency on the carved-out memory region shared with SOCCP. Change-Id: If20659b1153a06e42d15105d5ee1837f0356ef04 Signed-off-by: Grace An <quic_gracan@quicinc.com>
48 lines
1.2 KiB
Plaintext
48 lines
1.2 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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msm_hw_fence: qcom,hw-fence {
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compatible = "qcom,msm-hw-fence";
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status = "ok";
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/* SOCCP properties */
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x562 0x1>;
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dma-coherent;
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soccp_controller = <&soccp_pas>;
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qcom,hw-fence-table-entries = <8192>;
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qcom,hw-fence-queue-entries = <800>;
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qcom,ipcc-reg = <0x400000 0x140000>;
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/* time register */
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qcom,qtime-reg = <0xC221000 0x1000>;
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/* ipc version */
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qcom,hw-fence-ipc-ver = <0x20A02>;
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/* base client queue properties */
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qcom,hw-fence-client-type-dpu = <6 2 128 1>;
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qcom,hw-fence-client-type-ipe = <1 2 800 0>;
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qcom,hw-fence-client-type-vpu = <1 2 800 0>;
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qcom,hw-fence-client-type-ife0 = <1 1 128 1>;
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/* extra client queue properties */
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qcom,hw-fence-client-type-ife0-extra = <20 28 1 1>;
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/* haven io-mem specific */
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hw_fence@1 {
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compatible = "qcom,msm-hw-fence-mem";
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qcom,master;
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shared-buffer = <&hwfence_shbuf>;
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};
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};
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};
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