samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge 459ad4fd04 on remote branch

Browse Source 
Change-Id: Ieded4e10b42aaef59bdecfd0c9d58f29b45d6ede
This commit is contained in:
Linux Build Service Account
2024-11-19 21:48:15 -08:00
parent b65ab3733a 459ad4fd04
commit be87189db5
38 changed files with 3939 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
Kbuild
View File

@@ -30,6 +30,25 @@ dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
display/trustedvm-sun-sde-display-qrd-overlay.dtbo
endif
ifneq ($(CONFIG_ARCH_QTI_VM), y)
dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \
display/tuna-sde-display-atp-overlay.dtbo \
display/tuna-sde-display-cdp-overlay.dtbo \
display/tuna-sde-display-mtp-overlay.dtbo \
display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \
display/tuna-sde-display-qrd-overlay.dtbo \
display/tuna-sde-display-rumi-overlay.dtbo \
display/tuna-sde-display-rcm-overlay.dtbo
else
dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \
display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \
display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \
display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \
display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \
display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \
display/trustedvm-tuna-sde-display-rcm-overlay.dtbo
endif
always-y := $(dtb-y) $(dtbo-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb *.dtbo

8
display/sun-sde-common.dtsi
View File

@@ -13,11 +13,13 @@
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x400000 0x2000>;
<0x400000 0x2000>,
<0x0af50000 0x128>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"ipcc_reg";
"ipcc_reg",
"swfuse_phys";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -108,7 +110,7 @@
qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>;
qcom,sde-dither-off = <0xe0 0xe0 0xe0
0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
qcom,sde-dither-version = <0x00020000>;
qcom,sde-dither-size = <0x20>;

3
display/sun-sde-display-hdk.dtsi
View File

@@ -277,7 +277,8 @@
qcom,display-panels = <&dsi_vtdr6130_amoled_cmd
&dsi_vtdr6130_amoled_video
&dsi_vtdr6130_amoled_120hz_cmd
&dsi_vtdr6130_amoled_120hz_video>;
&dsi_vtdr6130_amoled_120hz_video
&dsi_ext_bridge_1080p>;
};
&qupv3_se4_spi {

2
display/sun-sde.dtsi
View File

@@ -275,7 +275,7 @@
qcom,sde-soccp-controller = <&soccp_pas>;
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys";
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,

22
display/trustedvm-sun-sde-display-cdp.dtsi
View File

@@ -54,6 +54,24 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd_spr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
@@ -166,6 +184,8 @@
&dsi_nt37801_amoled_cmd_cphy
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr
&dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr>;
@@ -179,6 +199,8 @@
&dsi_nt37801_amoled_cmd_cphy
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr>;
};

20
display/trustedvm-sun-sde-display-mtp.dtsi
View File

@@ -41,6 +41,24 @@
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 98 0>;
};
&dsi_sim_panel_au {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
@@ -92,6 +110,8 @@
&dsi_nt37801_amoled_cmd_cphy
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr>;

18
display/trustedvm-tuna-sde-display-atp-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM ATP";
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
"qcom,atp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <33 0>;
};

18
display/trustedvm-tuna-sde-display-cdp-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM CDP";
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
"qcom,cdp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <1 0>;
};

223
display/trustedvm-tuna-sde-display-cdp.dtsi Normal file
View File

@@ -0,0 +1,223 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-tuna-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_spr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_vid_spr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};

18
display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <8 3>;
};

6
display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-tuna-sde-display-mtp.dtsi"

18
display/trustedvm-tuna-sde-display-mtp-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM MTP";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>;
};

156
display/trustedvm-tuna-sde-display-mtp.dtsi Normal file
View File

@@ -0,0 +1,156 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-tuna-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_spr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_vid_spr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};

18
display/trustedvm-tuna-sde-display-qrd-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM QRD";
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
"qcom,qrd";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <11 0>;
};

106
display/trustedvm-tuna-sde-display-qrd.dtsi Normal file
View File

@@ -0,0 +1,106 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-tuna-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_cphy {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd_cphy {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video_cphy {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
};

18
display/trustedvm-tuna-sde-display-rcm-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM RCM";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
"qcom,rcm";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <21 0>, <21 1>;
};

17
display/trustedvm-tuna-sde-display-rumi-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "trustedvm-tuna-sde.dtsi"
#include "trustedvm-tuna-sde-display-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna SVM RUMI";
compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi";
qcom,msm-id = <655 0x10000>, <694 0x10000>;
qcom,board-id = <15 0>;
};

10
display/trustedvm-tuna-sde-display-rumi.dtsi Normal file
View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "trustedvm-tuna-sde-display.dtsi"
&mdss_mdp {
qcom,sde-emulated-env;
};

28
display/trustedvm-tuna-sde-display.dtsi Normal file
View File

@@ -0,0 +1,28 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display-common.dtsi"
&sde_dsi {
clocks = <&clock_cpucc 0>,
<&clock_cpucc 1>,
<&clock_cpucc 2>,
<&clock_cpucc 3>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1";
};
&sde_dsi1 {
clocks = <&clock_cpucc 0>,
<&clock_cpucc 1>,
<&clock_cpucc 2>,
<&clock_cpucc 3>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1";
};
&mdss_mdp {
connectors = <&sde_dsi &sde_dsi1>;
};

81
display/trustedvm-tuna-sde.dtsi Normal file
View File

@@ -0,0 +1,81 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include "tuna-sde-common.dtsi"
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x804 0x2>;
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
qcom,iommu-faults = "non-fatal";
dma-coherent;
};
};
&mdss_mdp {
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x0ae44000 0x02c>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"sid_phys";
qcom,sde-vm-exclude-reg-names = "sid_phys";
qcom,sde-hw-version =<0xC0000000>;
clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
"core_clk", "vsync_clk", "lut_clk";
qcom,sde-trusted-vm-env;
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi1 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};
&mdss_dsi_phy1 {
qcom,dsi-pll-in-trusted-vm;
};

469
display/tuna-sde-common.dtsi Normal file
View File

@@ -0,0 +1,469 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
mdss_mdp: qcom,mdss_mdp@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sde-kms";
reg = <0x0ae00000 0x93800>,
<0x0aeb0000 0x2008>,
<0x0af80000 0x7000>,
<0x400000 0x2000>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"ipcc_reg";
/* interrupt config */
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#cooling-cells = <2>;
/* hw blocks */
qcom,sde-off = <0x1000>;
qcom,sde-len = <0x488>;
qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>;
qcom,sde-ctl-size = <0x1000>;
qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
0x48000 0x0f0f 0x0f0f
0x0f0f 0x0f0f>;
qcom,sde-mixer-size = <0x400>;
qcom,sde-mixer-display-pref = "primary", "primary", "none",
"none", "none", "none", "none", "none";
qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none",
"dcwb", "dcwb", "dcwb", "dcwb";
qcom,sde-dspp-top-off = <0x1300>;
qcom,sde-dspp-top-size = <0x8c>;
qcom,sde-dspp-off = <0x55000 0x57000 0x59000>;
qcom,sde-dspp-size = <0x1800>;
qcom,sde-dspp-rc-version = <0x00010001>;
qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>;
qcom,sde-dspp-rc-size = <0x100>;
qcom,sde-dspp-rc-mem-size = <2720>;
qcom,sde-dspp-rc-min-region-width = <20>;
qcom,sde-dnsc-blur-version = <0x100>;
qcom,sde-dnsc-blur-off = <0x7D000>;
qcom,sde-dnsc-blur-size = <0x40>;
qcom,sde-dnsc-blur-gaus-lut-off = <0x100>;
qcom,sde-dnsc-blur-gaus-lut-size = <0x400>;
qcom,sde-dnsc-blur-dither-off = <0x5E0>;
qcom,sde-dnsc-blur-dither-size = <0x20>;
qcom,sde-dest-scaler-top-off = <0x0008F000>;
qcom,sde-dest-scaler-top-size = <0x1C>;
qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>;
qcom,sde-dest-scaler-size = <0x800>;
qcom,sde-wb-off = <0x65000 0x66000>;
qcom,sde-wb-size = <0x2c8>;
qcom,sde-wb-xin-id = <0xa 6>;
qcom,sde-wb-id = <1 2>;
qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>;
qcom,sde-intf-size = <0x4BC>;
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000
0x67000 0x67400 0x7f000 0x7f400>;
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,sde-pp-size = <0x2c>;
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>;
qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>;
qcom,sde-merge-3d-size = <0x1c>;
qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
qcom,sde-cdm-off = <0x7a200>;
qcom,sde-cdm-size = <0x240>;
qcom,sde-dsc-off = <0x81000 0x81000 0x82000>;
qcom,sde-dsc-size = <0x8>;
qcom,sde-dsc-pair-mask = <2 1 0>;
qcom,sde-dsc-hw-rev = "dsc_1_2";
qcom,sde-dsc-enc = <0x100 0x200 0x100>;
qcom,sde-dsc-enc-size = <0x100>;
qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>;
qcom,sde-dsc-ctl-size = <0x24>;
qcom,sde-dsc-native422-supp = <1 1 1>;
qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
qcom,sde-dither-version = <0x00020000>;
qcom,sde-dither-size = <0x20>;
qcom,sde-sspp-type = "vig", "vig",
"dma", "dma", "dma", "dma", "dma";
qcom,sde-sspp-off = <0x5000 0x7000
0x25000 0x27000 0x29000 0x2b000 0x2d000>;
qcom,sde-sspp-src-size = <0x344>;
qcom,sde-sspp-xin-id = <0 4 1 5 9 13 14>;
qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1>;
qcom,sde-sspp-smart-dma-priority = <6 7 1 2 3 4 5>;
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>;
qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130
0x160 0x190 0x1c0 0x1f0 0x220>;
qcom,sde-max-per-pipe-bw-kbps = <5100000 5100000
5100000 5100000
5100000 5100000
5100000>;
qcom,sde-max-per-pipe-bw-high-kbps = <5100000 5100000
5100000 5100000
5100000 5100000
5100000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-sspp-clk-ctrl =
<0x4330 0>, <0x6330 0>,
<0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>,
<0x2c330 0>;
qcom,sde-sspp-clk-status =
<0x4334 0>, <0x6334 0>,
<0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>,
<0x2c334 0>;
qcom,sde-sspp-csc-off = <0x1a00>;
qcom,sde-csc-type = "csc-10bit";
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
qcom,sde-qseed-scalar-version = <0x3004>;
qcom,sde-sspp-qseed-off = <0xa00>;
qcom,sde-mixer-linewidth = <2560>;
qcom,sde-sspp-linewidth = <5120>;
qcom,sde-wb-linewidth = <4096>;
qcom,sde-dsc-linewidth = <2560>;
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
qcom,sde-wb-linewidth-linear = <8192>;
qcom,sde-mixer-blendstages = <0xb>;
qcom,sde-highest-bank-bit = <0x8 0x3>;
qcom,sde-ubwc-version = <0x50000001>;
qcom,sde-ubwc-swizzle = <0x6>;
qcom,sde-ubwc-bw-calc-version = <0x1>;
qcom,sde-ubwc-static = <0x1>;
qcom,sde-macrotile-mode = <0x1>;
qcom,sde-smart-panel-align-mode = <0xc>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
qcom,sde-pipe-order-version = <0x1>;
qcom,sde-has-dim-layer;
qcom,sde-has-dest-scaler;
qcom,sde-max-trusted-vm-displays = <1>;
qcom,sde-max-bw-low-kbps = <23600000>;
qcom,sde-max-bw-high-kbps = <27800000>;
qcom,sde-min-core-ib-kbps = <2500000>;
qcom,sde-min-llcc-ib-kbps = <0>;
qcom,sde-min-dram-ib-kbps = <800000>;
qcom,sde-dram-channels = <4>;
qcom,sde-num-nrt-paths = <0>;
qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>;
qcom,sde-dspp-spr-size = <0x200>;
qcom,sde-dspp-spr-version = <0x00020000>;
qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>;
qcom,sde-dspp-demura-size = <0x150>;
qcom,sde-dspp-demura-version = <0x00030000>;
qcom,sde-lm-noise-off = <0x320>;
qcom,sde-lm-noise-version = <0x00010000>;
qcom,sde-uidle-off = <0x80000>;
qcom,sde-uidle-size = <0x80>;
qcom,sde-vbif-off = <0>;
qcom,sde-vbif-size = <0x1074>;
qcom,sde-vbif-id = <0>;
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>;
qcom,sde-vbif-default-ot-rd-limit = <40>;
qcom,sde-vbif-default-ot-wr-limit = <32>;
qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;
qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>;
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>;
qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>;
qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0
0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>;
qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001
0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>;
qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666
0x00112233 0x44556666 0x00112233 0x66666666
0x0 0x0 0x0 0x0
0x77776666 0x66666540 0x77776666 0x66666540
0x77776541 0x0 0x77776541 0x0
0x00112233 0x44556666 0x00112233 0x66666666
0x00112233 0x44556666 0x00112233 0x66666666
0x0 0x0 0x0 0x0
0x55555544 0x33221100 0x55555544 0x33221100>;
qcom,sde-cdp-setting = <1 1>, <1 0>;
qcom,sde-qos-cpu-mask = <0x3>;
qcom,sde-qos-cpu-mask-performance = <0x3>;
qcom,sde-qos-cpu-dma-latency = <300>;
qcom,sde-qos-cpu-irq-latency = <300>;
qcom,sde-ipcc-protocol-id = <0x4>;
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
/* offsets are relative to "mdp_phys + qcom,sde-off */
qcom,sde-reg-dma-off = <0 0x800>;
qcom,sde-reg-dma-id = <0 1>;
qcom,sde-reg-dma-version = <0x00030000>;
qcom,sde-reg-dma-trigger-off = <0x119c>;
qcom,sde-reg-dma-xin-id = <7>;
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
qcom,sde-secure-sid-mask = <0x801>;
qcom,sde-reg-bus,vectors-KBps = <0 0>,
<0 14000>,
<0 140000>,
<0 310000>;
qcom,sde-sspp-vig-blocks {
vcm@0 {
cell-index = <0>;
qcom,sde-vig-top-off = <0x700>;
qcom,sde-vig-csc-off = <0x1a00>;
qcom,sde-vig-qseed-off = <0xa00>;
qcom,sde-vig-qseed-size = <0xe0>;
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
qcom,sde-vig-igc = <0x1d00 0x00060000>;
qcom,sde-vig-inverse-pma;
qcom,sde-fp16-igc = <0x200 0x00010000>;
qcom,sde-fp16-unmult = <0x200 0x00010000>;
qcom,sde-fp16-gc = <0x200 0x00010000>;
qcom,sde-fp16-csc = <0x200 0x00010000>;
qcom,sde-ucsc-igc = <0x700 0x00010001>;
qcom,sde-ucsc-unmult = <0x700 0x00010001>;
qcom,sde-ucsc-gc = <0x700 0x00010001>;
qcom,sde-ucsc-csc = <0x700 0x00010001>;
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
};
vcm@1 {
cell-index = <1>;
qcom,sde-fp16-igc = <0x280 0x00010000>;
qcom,sde-fp16-unmult = <0x280 0x00010000>;
qcom,sde-fp16-gc = <0x280 0x00010000>;
qcom,sde-fp16-csc = <0x280 0x00010000>;
qcom,sde-ucsc-igc = <0x1700 0x00010001>;
qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
qcom,sde-ucsc-gc = <0x1700 0x00010001>;
qcom,sde-ucsc-csc = <0x1700 0x00010001>;
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
};
};
qcom,sde-sspp-dma-blocks {
dgm@0 {
cell-index = <0>;
qcom,sde-dma-top-off = <0x700>;
qcom,sde-fp16-igc = <0x200 0x00010000>;
qcom,sde-fp16-unmult = <0x200 0x00010000>;
qcom,sde-fp16-gc = <0x200 0x00010000>;
qcom,sde-fp16-csc = <0x200 0x00010000>;
qcom,sde-ucsc-igc = <0x700 0x00010001>;
qcom,sde-ucsc-unmult = <0x700 0x00010001>;
qcom,sde-ucsc-gc = <0x700 0x00010001>;
qcom,sde-ucsc-csc = <0x700 0x00010001>;
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
};
dgm@1 {
cell-index = <1>;
qcom,sde-fp16-igc = <0x200 0x00010000>;
qcom,sde-fp16-unmult = <0x200 0x00010000>;
qcom,sde-fp16-gc = <0x200 0x00010000>;
qcom,sde-fp16-csc = <0x200 0x00010000>;
qcom,sde-ucsc-igc = <0x1700 0x00010001>;
qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
qcom,sde-ucsc-gc = <0x1700 0x00010001>;
qcom,sde-ucsc-csc = <0x1700 0x00010001>;
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
};
};
qcom,sde-dspp-blocks {
qcom,sde-dspp-igc = <0x1260 0x00050000>;
qcom,sde-dspp-hsic = <0x800 0x00010007>;
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
qcom,sde-dspp-hist = <0x800 0x00010007>;
qcom,sde-dspp-sixzone = <0x900 0x00020000>;
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
qcom,sde-dspp-pcc = <0x1700 0x00060000>;
qcom,sde-dspp-gc = <0x17c0 0x00020000>;
qcom,sde-dspp-dither = <0x82c 0x00010007>;
};
};
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
compatible = "qcom,dsi-ctrl-hw-v2.9";
label = "dsi-ctrl-0";
cell-index = <0>;
frame-threshold-time-us = <800>;
reg = <0xae94000 0x1000>,
<0xaf0f000 0x4>,
<0x0ae36000 0x300>;
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <4 0>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <16600>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
compatible = "qcom,dsi-ctrl-hw-v2.9";
label = "dsi-ctrl-1";
cell-index = <1>;
frame-threshold-time-us = <800>;
reg = <0xae96000 0x1000>,
<0xaf0f000 0x4>,
<0x0ae37000 0x300>;
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
interrupt-parent = <&mdss_mdp>;
interrupts = <5 0>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1200000>;
qcom,supply-enable-load = <16600>;
qcom,supply-disable-load = <0>;
};
};
};
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
compatible = "qcom,dsi-phy-v5.2";
label = "dsi-phy-0";
cell-index = <0>;
#clock-cells = <1>;
reg = <0xae95000 0xa00>,
<0xae95500 0x400>,
<0xae94200 0xa0>;
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
pll-label = "dsi_pll_4nm";
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <950000>;
qcom,supply-enable-load = <98000>;
qcom,supply-disable-load = <96>;
};
};
};
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
compatible = "qcom,dsi-phy-v5.2";
label = "dsi-phy-1";
cell-index = <1>;
#clock-cells = <1>;
reg = <0xae97000 0xa00>,
<0xae97500 0x400>,
<0xae96200 0xa0>;
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
pll-label = "dsi_pll_4nm";
qcom,platform-strength-ctrl = [55 03
55 03
55 03
55 03
55 00];
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
qcom,platform-lane-config = [00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 0a 0a
00 00 8a 8a];
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <950000>;
qcom,supply-enable-load = <98000>;
qcom,supply-disable-load = <96>;
};
};
};
dsi_pll_codes_data:dsi_pll_codes {
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
label = "dsi_pll_codes";
};
};

17
display/tuna-sde-display-atp-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna ATP";
compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap",
"qcom,atp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <33 0>;
};

17
display/tuna-sde-display-cdp-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna CDP";
compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap",
"qcom,cdp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <1 0>;
};

277
display/tuna-sde-display-cdp.dtsi Normal file
View File

@@ -0,0 +1,277 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display.dtsi"
&dsi_vtdr6130_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_120hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_spr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_vid_spr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_120hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_vtdr6130_amoled_qsync_144hz_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};
&qupv3_se4_i2c {
st_fts@49 {
panel = <&dsi_nt37801_amoled_cmd
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_dsc_10b_cmd
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr>;
};
};

1232
display/tuna-sde-display-common.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

17
display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-mtp-kiwi-harmonium.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <8 3>;
};

6
display/tuna-sde-display-mtp-kiwi-harmonium.dtsi Normal file
View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display-mtp.dtsi"

17
display/tuna-sde-display-mtp-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>;
};

202
display/tuna-sde-display-mtp.dtsi Normal file
View File

@@ -0,0 +1,202 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_dsc_10b_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_spr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_vid_spr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_ddicspr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_ddicspr {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
};
&qupv3_se4_i2c {
st_fts@49 {
panel = <&dsi_nt37801_amoled_cmd
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_dsc_10b_cmd
&dsi_nt37801_amoled_dsc_10b_video
&dsi_nt37801_amoled_cmd_spr
&dsi_nt37801_amoled_vid_spr
&dsi_nt37801_amoled_qsync_cmd
&dsi_nt37801_amoled_qsync_video
&dsi_nt37801_amoled_fhd_plus_cmd
&dsi_nt37801_amoled_cmd_ddicspr
&dsi_nt37801_amoled_video_ddicspr>;
};
};

114
display/tuna-sde-display-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,114 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&tlmm {
pmx_sde: pmx_sde {
sde_dsi_active: sde_dsi_active {
mux {
pins = "gpio14";
function = "gpio";
};
config {
pins = "gpio14";
drive-strength = <8>; /* 8 mA */
bias-disable = <0>; /* no pull */
};
};
sde_dsi_suspend: sde_dsi_suspend {
mux {
pins = "gpio14";
function = "gpio";
};
config {
pins = "gpio14";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_dsi1_active: sde_dsi1_active {
mux {
pins = "gpio126";
function = "gpio";
};
config {
pins = "gpio126";
drive-strength = <8>; /* 8 mA */
bias-disable = <0>; /* no pull */
};
};
sde_dsi1_suspend: sde_dsi1_suspend {
mux {
pins = "gpio126";
function = "gpio";
};
config {
pins = "gpio126";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
};
pmx_sde_te: pmx_sde_te {
sde_te_active: sde_te_active {
mux {
pins = "gpio77";
function = "mdp_vsync_p";
};
config {
pins = "gpio77";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_te_suspend: sde_te_suspend {
mux {
pins = "gpio77";
function = "mdp_vsync_p";
};
config {
pins = "gpio77";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_te1_active: sde_te1_active {
mux {
pins = "gpio78";
function = "mdp_vsync_s";
};
config {
pins = "gpio78";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
sde_te1_suspend: sde_te1_suspend {
mux {
pins = "gpio78";
function = "mdp_vsync_s";
};
config {
pins = "gpio78";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
};
};
};
};

17
display/tuna-sde-display-qrd-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna QRD";
compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap",
"qcom,qrd";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <11 0>;
};

137
display/tuna-sde-display-qrd.dtsi Normal file
View File

@@ -0,0 +1,137 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display.dtsi"
&dsi_nt37801_amoled_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_video_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_cmd_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_nt37801_amoled_qsync_video_cphy {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <10>;
qcom,mdss-dsi-bl-max-level = <4095>;
qcom,mdss-brightness-max-level = <8191>;
qcom,mdss-dsi-bl-inverted-dbv;
qcom,platform-reset-gpio = <&tlmm 14 0>;
qcom,platform-sec-reset-gpio = <&tlmm 126 0>;
};
&dsi_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_vid {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_dsc_10b_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_dual_sim_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
};
&dsi_dual_sim_dsc_375_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
};
&dsi_sim_sec_hd_cmd {
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
qcom,mdss-dsi-bl-min-level = <1>;
qcom,mdss-dsi-bl-max-level = <1023>;
};
&sde_dsi {
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
};
&qupv3_se4_spi {
st_fts@0 {
panel = <&dsi_nt37801_amoled_cmd_cphy
&dsi_nt37801_amoled_video_cphy
&dsi_nt37801_amoled_cmd
&dsi_nt37801_amoled_video
&dsi_nt37801_amoled_qsync_cmd_cphy
&dsi_nt37801_amoled_qsync_video_cphy>;
};
};

17
display/tuna-sde-display-rcm-overlay.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM";
compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap",
"qcom,rcm";
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <21 0>, <21 1>;
};

16
display/tuna-sde-display-rumi-overlay.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde-display-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RUMI";
compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi";
qcom,msm-id = <655 0x10000>, <694 0x10000>;
qcom,board-id = <15 0>;
};

11
display/tuna-sde-display-rumi.dtsi Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-sde-display.dtsi"
&mdss_mdp {
qcom,sde-emulated-env;
};

248
display/tuna-sde-display.dtsi Normal file
View File

@@ -0,0 +1,248 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include "tuna-sde-display-common.dtsi"
&soc {
sde_wb1: qcom,wb-display@1 {
compatible = "qcom,wb-display";
cell-index = <0>;
label = "wb_display1";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
sde_wb2: qcom,wb-display@2 {
compatible = "qcom,wb-display";
cell-index = <1>;
label = "wb_display2";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
};
&sde_dsi {
clocks = <&mdss_dsi_phy0 0>,
<&mdss_dsi_phy0 1>,
<&mdss_dsi_phy1 0>,
<&mdss_dsi_phy1 1>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk";
vddio-supply = <&L8B>;
vci-supply = <&L19B>;
vdd-supply = <&L3D>;
};
&sde_dsi1 {
clocks = <&mdss_dsi_phy0 0>,
<&mdss_dsi_phy0 1>,
<&mdss_dsi_phy1 0>,
<&mdss_dsi_phy1 1>,
/*
* Currently the dsi clock handles are under the dsi
* controller DT node. As soon as the controller probe
* finishes, the dispcc sync state can get called before
* the dsi_display probe potentially disturbing the clock
* votes for cont_splash use case. Hence we are no longer
* protected by the component model in this case against the
* disp cc sync state getting triggered after the dsi_ctrl
* probe. To protect against this incorrect sync state trigger
* add this dummy MDP clk vote handle to the dsi_display
* DT node. Since the dsi_display driver does not parse
* MDP clock nodes, no actual vote shall be added and this
* change is done just to satisfy sync state requirements.
*/
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
"pll_byte_clk1", "pll_dsi_clk1",
"mdp_core_clk";
vddio-supply = <&L8B>;
vci-supply = <&L19B>;
vdd-supply = <&L3D>;
};
&mdss_mdp {
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>;
};
&dsi_vtdr6130_amoled_cmd {
qcom,ulps-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
};
timing@3 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
};
};
};
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
qcom,ulps-enabled;
};
&dsi_nt37801_amoled_cmd {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@3 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@4 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
};
};
&dsi_nt37801_amoled_cmd_cphy {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
};
};
&dsi_nt37801_amoled_fhd_plus_cmd {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@1 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@2 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@3 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
timing@4 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
};
};
};
&dsi_nt37801_amoled_cmd_spr {
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,partial-update-enabled = "single_roi";
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
};
};
};
&dsi_sim_cmd {
qcom,ulps-enabled;
qcom,mdss-dsi-display-timings {
timing@0 { /* WQHD 60FPS cmd vid mode*/
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
qcom,partial-update-enabled = "single_roi";
};
timing@2 { /* FHD 60FPS cmd mode*/
qcom,panel-roi-alignment = <540 20 540 20 540 20>;
qcom,partial-update-enabled = "single_roi";
};
timing@3 { /* HD 60FPS cmd mode*/
qcom,panel-roi-alignment = <360 40 360 40 360 40>;
qcom,partial-update-enabled = "single_roi";
};
};
};
&dsi_sim_dsc_375_cmd {
qcom,ulps-enabled;
};
&dsi_sim_dsc_10b_cmd {
qcom,ulps-enabled;
};
&dsi_dual_sim_cmd {
qcom,ulps-enabled;
};
&dsi_dual_sim_dsc_375_cmd {
qcom,ulps-enabled;
};
&dsi_sim_sec_hd_cmd {
qcom,ulps-enabled;
qcom,mdss-dsi-display-timings {
timing@0 {
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
qcom,partial-update-enabled = "single_roi";
};
};
};

14
display/tuna-sde.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-sde.dtsi"
/ {
qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
qcom,board-id = <0 0>;
};

307
display/tuna-sde.dtsi Normal file
View File

@@ -0,0 +1,307 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,dispcc-tuna.h>
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/interconnect/qcom,tuna.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
#include "tuna-sde-common.dtsi"
&soc {
ext_disp: qcom,msm-ext-disp {
compatible = "qcom,msm-ext-disp";
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
compatible = "qcom,msm-ext-disp-audio-codec-rx";
};
};
qcom_msmhdcp: qcom,msm_hdcp {
compatible = "qcom,msm-hdcp";
};
sde_dp_pll: qcom,dp_pll@88ea000 {
compatible = "qcom,dp-pll-4nm-v1.1";
#clock-cells = <1>;
};
sde_dp: qcom,dp_display@af54000 {
cell-index = <0>;
compatible = "qcom,dp-display";
status = "disabled";
//usb-phy = <&usb_qmp_dp_phy>;
qcom,ext-disp = <&ext_disp>;
usb-controller = <&usb0>;
qcom,altmode-dev = <&altmode 0>;
reg = <0xaf54000 0x104>,
<0xaf54200 0x0c0>,
<0xaf55000 0x770>,
<0xaf56000 0x09c>,
<0x88eaa00 0x200>,
<0x88ea200 0x200>,
<0x88ea600 0x200>,
<0x88ea000 0x200>,
<0x88e8000 0x020>,
<0xaee1000 0x034>,
<0xaf57000 0x09c>,
<0xaf09000 0x014>;
reg-names = "dp_ahb", "dp_aux", "dp_link",
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
"dp_pll", "usb3_dp_com", "hdcp_physical",
"dp_p1", "gdsc";
interrupt-parent = <&mdss_mdp>;
interrupts = <12 0>;
#clock-cells = <1>;
clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&sde_dp_pll 0>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&sde_dp_pll 1>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
qcom,dp-pll = <&sde_dp_pll>;
qcom,phy-version = <0x600>;
qcom,aux-cfg0-settings = [20 00];
qcom,aux-cfg1-settings = [24 13];
qcom,aux-cfg2-settings = [28 A4];
qcom,aux-cfg3-settings = [2c 00];
qcom,aux-cfg4-settings = [30 0a];
qcom,aux-cfg5-settings = [34 26];
qcom,aux-cfg6-settings = [38 0a];
qcom,aux-cfg7-settings = [3c 03];
qcom,aux-cfg8-settings = [40 b7];
qcom,aux-cfg9-settings = [44 03];
qcom,max-pclk-frequency-khz = <675000>;
qcom,widebus-enable;
qcom,dsc-feature-enable;
qcom,fec-feature-enable;
qcom,dsc-continuous-pps;
qcom,qos-cpu-mask = <0xf>;
qcom,qos-cpu-latency-us = <300>;
vdda-1p2-supply = <&L4B>;
vdda-0p9-supply = <&L3B>;
vdda_usb-0p9-supply = <&L3B>;
//vdd_mx-supply = <&VDD_MXA_LEVEL>;
dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
<0x11 0x1e 0x1f 0xff>,
<0x16 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
<0x00 0x0e 0x15 0xff>,
<0x00 0x0e 0xff 0xff>,
<0x02 0xff 0xff 0xff>;
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
<0x09 0x19 0x1f 0xff>,
<0x10 0x1f 0xff 0xff>,
<0x1f 0xff 0xff 0xff>;
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
<0x02 0x0e 0x16 0xff>,
<0x02 0x11 0xff 0xff>,
<0x04 0xff 0xff 0xff>;
qcom,ctrl-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,ctrl-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-1p2";
qcom,supply-min-voltage = <1200000>;
qcom,supply-max-voltage = <1300000>;
qcom,supply-enable-load = <30000>;
qcom,supply-disable-load = <0>;
};
};
qcom,phy-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,phy-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdda-0p9";
qcom,supply-min-voltage = <912000>;
qcom,supply-max-voltage = <950000>;
qcom,supply-enable-load = <114000>;
qcom,supply-disable-load = <0>;
};
qcom,phy-supply-entry@1 {
reg = <1>;
qcom,supply-name = "vdda_usb-0p9";
qcom,supply-min-voltage = <880000>;
qcom,supply-max-voltage = <950000>;
qcom,supply-enable-load = <2500>;
qcom,supply-disable-load = <0>;
};
};
qcom,pll-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,pll-supply-entry@0 {
reg = <0>;
qcom,supply-name = "vdd_mx";
qcom,supply-min-voltage =
<RPMH_REGULATOR_LEVEL_TURBO>;
qcom,supply-max-voltage =
<RPMH_REGULATOR_LEVEL_MAX>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
<&smmu_sde_sec 0x0 0x00020000>;
};
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
compatible = "qcom,smmu_sde_unsec";
iommus = <&apps_smmu 0x800 0x2>;
memory-region = <&smmu_sde_iommu_region_partition>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-earlymap; /* for cont-splash */
dma-coherent;
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
smmu_sde_sec: qcom,smmu_sde_sec_cb {
compatible = "qcom,smmu_sde_sec";
iommus = <&apps_smmu 0x801 0x0>;
memory-region = <&smmu_sde_iommu_region_partition>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-vmid = <0xa>;
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "mdp_core_clk";
};
};
&mdss_mdp {
clocks =
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
clock-names = "gcc_bus",
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
"lut_clk";
clock-rate = <0 0 660000000 660000000 19200000 660000000>;
clock-max-rate = <0 0 660000000 660000000 19200000 660000000>;
clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>;
qcom,hw-fence-sw-version = <0x1>;
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
mmcx-supply = <&VDD_MMCX_LEVEL>;
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
/* data and reg bus scale settings */
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_DISPLAY_CFG>;
interconnect-names = "qcom,sde-data-bus0",
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
qcom,sde-has-idle-pc;
qcom,sde-ib-bw-vote = <2500000 0 800000>;
qcom,sde-dspp-ltm-version = <0x00010003>;
/* offsets are based off dspp 0, 1, 2, and 3 */
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>;
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
qcom,platform-supply-entry@0 {
reg = <0>;
qcom,supply-name = "mmcx";
qcom,supply-min-voltage = <0>;
qcom,supply-max-voltage = <0>;
qcom,supply-enable-load = <0>;
qcom,supply-disable-load = <0>;
};
};
};
&mdss_dsi0 {
vdda-1p2-supply = <&L4B>;
qcom,split-link-supported;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
};
&mdss_dsi1 {
vdda-1p2-supply = <&L4B>;
qcom,split-link-supported;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
};
&mdss_dsi_phy0 {
vdda-0p9-supply = <&L2B>;
qcom,panel-allow-phy-poweroff;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
pll_codes_region = <&dsi_pll_codes_data>;
};
&mdss_dsi_phy1 {
vdda-0p9-supply = <&L2B>;
qcom,panel-allow-phy-poweroff;
qcom,dsi-pll-ssc-en;
qcom,dsi-pll-ssc-mode = "down-spread";
pll_codes_region = <&dsi_pll_codes_data>;
};