From d334f234de483b06d30100a3c71455833b14130e Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:55:39 +0530 Subject: [PATCH 01/16] ARM: dts: msm: add DDIC SPR cmd/video mode on sun trustedvm platform Add DDIC SPR cmd/video mode on sun trustedvm platform. Change-Id: Ieae00136db2e76c1119ec42eac89a4c2df51a074 Signed-off-by: Ayushi Makhija --- display/trustedvm-sun-sde-display-cdp.dtsi | 22 ++++++++++++++++++++++ display/trustedvm-sun-sde-display-mtp.dtsi | 20 ++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 13d89f62..cc339fca 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -54,6 +54,24 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd_spr { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -166,6 +184,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; @@ -179,6 +199,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; }; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index d762f789..ea7d79ce 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -41,6 +41,24 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -92,6 +110,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; From 5f9b22a66d8e592a860ed6e7a69884a7177275c2 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Thu, 5 Sep 2024 13:18:08 -0700 Subject: [PATCH 02/16] ARM: dts: msm: add support for sw fuse for Sun target Add sw fuse range to dts file for Sun target. The swfuse_phys is only needed in primary VM. Change-Id: I8a7446c2f6cbf183a7bff6af463ff7f427467628 Signed-off-by: Ping Li --- display/sun-sde-common.dtsi | 6 ++++-- display/sun-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 8a68f314..12270f64 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x128>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 2617a86c..f5dda611 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -275,7 +275,7 @@ qcom,sde-soccp-controller = <&soccp_pas>; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From c6d3648a833818f334d8902baa90cf52fc5b0872 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Tue, 30 Apr 2024 14:54:42 -0700 Subject: [PATCH 03/16] ARM: dts: qcom: update display panel for battery_charger on Sun HDK Update the list of display panels under battery_charger device to support enable/disable notifications from the charger firmware at runtime based on panel event notifications on Sun HDK. Change-Id: I2d025b23915c0ebce4ebb8caafcdec672fed9b2c Signed-off-by: Subbaraman Narayanamurthy --- display/sun-sde-display-hdk.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-hdk.dtsi b/display/sun-sde-display-hdk.dtsi index a5868788..fd5bca06 100644 --- a/display/sun-sde-display-hdk.dtsi +++ b/display/sun-sde-display-hdk.dtsi @@ -277,7 +277,8 @@ qcom,display-panels = <&dsi_vtdr6130_amoled_cmd &dsi_vtdr6130_amoled_video &dsi_vtdr6130_amoled_120hz_cmd - &dsi_vtdr6130_amoled_120hz_video>; + &dsi_vtdr6130_amoled_120hz_video + &dsi_ext_bridge_1080p>; }; &qupv3_se4_spi { From f67e4c69c1b191a36bd8bccfef5514745e071b6a Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Sat, 7 Sep 2024 03:46:16 +0530 Subject: [PATCH 04/16] ARM: dts: msm: add initial dsi display nodes for Tuna Add initial dsi display nodes for Tuna. Change-Id: Iadcf785e9ecdaa8baabe94ce0921190d141170d2 Signed-off-by: Abhinav Saurabh --- display/tuna-sde-common.dtsi | 149 +++++++++++++++++++++++++++++++++++ display/tuna-sde.dts | 14 ++++ display/tuna-sde.dtsi | 57 ++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 display/tuna-sde-common.dtsi create mode 100644 display/tuna-sde.dts create mode 100644 display/tuna-sde.dtsi diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi new file mode 100644 index 00000000..a9d1afed --- /dev/null +++ b/display/tuna-sde-common.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/tuna-sde.dts b/display/tuna-sde.dts new file mode 100644 index 00000000..b9a80b12 --- /dev/null +++ b/display/tuna-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde.dtsi" + +/ { + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi new file mode 100644 index 00000000..04165109 --- /dev/null +++ b/display/tuna-sde.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; From 722ce2c3d0dedad9138ae054575762c12765d3bb Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Wed, 25 Sep 2024 15:07:27 +0530 Subject: [PATCH 05/16] ARM: dts: msm: add initial dp display nodes for Tuna target Add initial dp display nodes for Tuna target. Change-Id: I1ae45cea93d708b0eb76e59a43dd849de536f22c Signed-off-by: Mani Chandana Ballary Kuntumalla --- display/tuna-sde.dtsi | 169 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 04165109..4c964d5b 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -2,11 +2,180 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include +#include #include "tuna-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "disabled"; + + //usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L3B>; + vdda_usb-0p9-supply = <&L3B>; + //vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; }; &mdss_mdp { From a0472afd5fb7f622edcead5517e2a8dfd18ff242 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 17 Sep 2024 10:28:08 +0530 Subject: [PATCH 06/16] ARM: dts: msm: enable display on tuna platforms Enable display on tuna platforms. Change-Id: I039ff6c32febd7b2afebfaa24a921186b5a46f2c Signed-off-by: Abhinav Saurabh --- Kbuild | 11 + display/tuna-sde-display-atp-overlay.dts | 17 + display/tuna-sde-display-cdp-overlay.dts | 17 + display/tuna-sde-display-cdp.dtsi | 192 +++ display/tuna-sde-display-common.dtsi | 1043 +++++++++++++++++ display/tuna-sde-display-mtp-kiwi-overlay.dts | 17 + display/tuna-sde-display-mtp-kiwi.dtsi | 6 + display/tuna-sde-display-mtp-overlay.dts | 17 + display/tuna-sde-display-mtp.dtsi | 186 +++ display/tuna-sde-display-pinctrl.dtsi | 114 ++ display/tuna-sde-display-qrd-overlay.dts | 17 + display/tuna-sde-display-qrd.dtsi | 126 ++ display/tuna-sde-display-rcm-overlay.dts | 17 + display/tuna-sde-display-rumi-overlay.dts | 16 + display/tuna-sde-display-rumi.dtsi | 11 + display/tuna-sde-display.dtsi | 204 ++++ 16 files changed, 2011 insertions(+) create mode 100644 display/tuna-sde-display-atp-overlay.dts create mode 100644 display/tuna-sde-display-cdp-overlay.dts create mode 100644 display/tuna-sde-display-cdp.dtsi create mode 100644 display/tuna-sde-display-common.dtsi create mode 100644 display/tuna-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/tuna-sde-display-mtp-kiwi.dtsi create mode 100644 display/tuna-sde-display-mtp-overlay.dts create mode 100644 display/tuna-sde-display-mtp.dtsi create mode 100644 display/tuna-sde-display-pinctrl.dtsi create mode 100644 display/tuna-sde-display-qrd-overlay.dts create mode 100644 display/tuna-sde-display-qrd.dtsi create mode 100644 display/tuna-sde-display-rcm-overlay.dts create mode 100644 display/tuna-sde-display-rumi-overlay.dts create mode 100644 display/tuna-sde-display-rumi.dtsi create mode 100644 display/tuna-sde-display.dtsi diff --git a/Kbuild b/Kbuild index 1e85878a..dfa6c483 100644 --- a/Kbuild +++ b/Kbuild @@ -30,6 +30,17 @@ dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-qrd-overlay.dtbo endif +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ + display/tuna-sde-display-atp-overlay.dtbo \ + display/tuna-sde-display-cdp-overlay.dtbo \ + display/tuna-sde-display-mtp-overlay.dtbo \ + display/tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/tuna-sde-display-qrd-overlay.dtbo \ + display/tuna-sde-display-rumi-overlay.dtbo \ + display/tuna-sde-display-rcm-overlay.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/display/tuna-sde-display-atp-overlay.dts b/display/tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..87105863 --- /dev/null +++ b/display/tuna-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/tuna-sde-display-cdp-overlay.dts b/display/tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..ac83131c --- /dev/null +++ b/display/tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..3a36881e --- /dev/null +++ b/display/tuna-sde-display-cdp.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi new file mode 100644 index 00000000..11e68080 --- /dev/null +++ b/display/tuna-sde-display-common.dtsi @@ -0,0 +1,1043 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +#include "tuna-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1950000>; + qcom,supply-enable-load = <154000>; + qcom,supply-disable-load = <45000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1000000>; + qcom,supply-max-voltage = <1100000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <471>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3540000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 77 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 78 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YYG with reduced margins */ + +&dsi_nt37801_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 1a 0c 00]; + qcom,display-topology = <1 0 1>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/tuna-sde-display-mtp-kiwi-overlay.dts b/display/tuna-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..e826d973 --- /dev/null +++ b/display/tuna-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/display/tuna-sde-display-mtp-kiwi.dtsi b/display/tuna-sde-display-mtp-kiwi.dtsi new file mode 100644 index 00000000..ddf34dc6 --- /dev/null +++ b/display/tuna-sde-display-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include "tuna-sde-display-mtp.dtsi" diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..277cc2e7 --- /dev/null +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>, <8 1>; +}; diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..cf76078e --- /dev/null +++ b/display/tuna-sde-display-mtp.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/tuna-sde-display-pinctrl.dtsi b/display/tuna-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..dafc8eb9 --- /dev/null +++ b/display/tuna-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/display/tuna-sde-display-qrd-overlay.dts b/display/tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..b422a057 --- /dev/null +++ b/display/tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..5a3f6295 --- /dev/null +++ b/display/tuna-sde-display-qrd.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/display/tuna-sde-display-rcm-overlay.dts b/display/tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..3adf6685 --- /dev/null +++ b/display/tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/display/tuna-sde-display-rumi-overlay.dts b/display/tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..d7f33da6 --- /dev/null +++ b/display/tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/tuna-sde-display-rumi.dtsi b/display/tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..9f4795a1 --- /dev/null +++ b/display/tuna-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi new file mode 100644 index 00000000..12934721 --- /dev/null +++ b/display/tuna-sde-display.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "tuna-sde-display-common.dtsi" + +&soc { +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; From d61e445679c3752a96ad46e50d98d149b0da9ba7 Mon Sep 17 00:00:00 2001 From: Jyothi bommidi Date: Wed, 25 Sep 2024 12:08:44 +0530 Subject: [PATCH 07/16] ARM: dts: msm: enable touch support for tuna display Enable touch support for tuna on CDP, MTP and QRD platforms. Change-Id: I976de6d01cc99bf6698128a121cc43041071461a Signed-off-by: Jyothi bommidi --- display/tuna-sde-display-cdp.dtsi | 15 +++++++++++++++ display/tuna-sde-display-mtp.dtsi | 16 ++++++++++++++++ display/tuna-sde-display-qrd.dtsi | 11 +++++++++++ 3 files changed, 42 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 3a36881e..c275438b 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -190,3 +190,18 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi index cf76078e..e330558d 100644 --- a/display/tuna-sde-display-mtp.dtsi +++ b/display/tuna-sde-display-mtp.dtsi @@ -184,3 +184,19 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 5a3f6295..13de5d6f 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -124,3 +124,14 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; + }; +}; From e1e3bcbddebda5112036ee0004f7a6276c9235a2 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Tue, 24 Sep 2024 13:04:15 +0530 Subject: [PATCH 08/16] ARM: dts: msm: add display dt node for Tuna target This patch adds display device tree support for Tuna target. Change-Id: Ife1ab80dcb78fc7654805ab5bedec76bdd33039d Signed-off-by: Akash Gajjar --- display/trustedvm-tuna-sde.dtsi | 81 ++++++++ display/tuna-sde-common.dtsi | 320 ++++++++++++++++++++++++++++++++ display/tuna-sde.dtsi | 81 ++++++++ 3 files changed, 482 insertions(+) create mode 100644 display/trustedvm-tuna-sde.dtsi diff --git a/display/trustedvm-tuna-sde.dtsi b/display/trustedvm-tuna-sde.dtsi new file mode 100644 index 00000000..79d85eab --- /dev/null +++ b/display/trustedvm-tuna-sde.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version =<0xC0000000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index a9d1afed..be5b2380 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -7,6 +7,326 @@ &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x65000 0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0xa 6>; + qcom,sde-wb-id = <1 2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000 0x2d000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13 14>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <6 7 1 2 3 4 5>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>, + <0x2c330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>, + <0x2c334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x3>; + qcom,sde-ubwc-version = <0x50000001>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <23600000>; + qcom,sde-max-bw-high-kbps = <27800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <4>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 4c964d5b..79fb22e3 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -5,8 +5,10 @@ #include #include #include +#include #include #include +#include #include "tuna-sde-common.dtsi" &soc { @@ -175,10 +177,89 @@ qcom,supply-disable-load = <0>; }; }; + + }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; }; &mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + + qcom,hw-fence-sw-version = <0x1>; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; &mdss_dsi0 { From bfd09f6c6de1bb51669f7263068da1c254a194d7 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 10 Oct 2024 11:33:04 +0530 Subject: [PATCH 09/16] ARM: dts: msm: update dsi supply voltage for tuna Update DSI and panel supply voltage configuration as per the recent change in the supplier regulators. Change-Id: I68f81440637a673810773c5c8790da7bf7db38ba Signed-off-by: Abhinav Saurabh --- display/tuna-sde-common.dtsi | 8 ++++---- display/tuna-sde-display-common.dtsi | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index be5b2380..e2a5d2f5 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -349,7 +349,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -375,7 +375,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -412,7 +412,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; + qcom,supply-max-voltage = <950000>; qcom,supply-enable-load = <98000>; qcom,supply-disable-load = <96>; }; @@ -448,7 +448,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; + qcom,supply-max-voltage = <950000>; qcom,supply-enable-load = <98000>; qcom,supply-disable-load = <96>; }; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 11e68080..21e45a58 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -55,7 +55,7 @@ reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1950000>; + qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <154000>; qcom,supply-disable-load = <45000>; qcom,supply-post-on-sleep = <20>; @@ -64,7 +64,7 @@ qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <1000000>; + qcom,supply-min-voltage = <1030000>; qcom,supply-max-voltage = <1100000>; qcom,supply-enable-load = <220000>; qcom,supply-disable-load = <471>; @@ -75,7 +75,7 @@ reg = <2>; qcom,supply-name = "vci"; qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3540000>; + qcom,supply-max-voltage = <3544000>; qcom,supply-enable-load = <10000>; qcom,supply-disable-load = <300>; qcom,supply-post-on-sleep = <0>; From b37f9177371868805978c0a38747b7e6be6260e3 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Thu, 3 Oct 2024 10:51:13 +0530 Subject: [PATCH 10/16] ARM: dts: msm: enable display connectors on tuna target Add smmu secure, unsecure, wb1, wb2 DT node on tuna target. Change-Id: Iae9cfd130a704773f63e3fbb1ab2f1b20a09681d Signed-off-by: Akash Gajjar --- display/tuna-sde-display.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index 12934721..cbcbda6f 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -7,6 +7,21 @@ #include "tuna-sde-display-common.dtsi" &soc { + sde_wb1: qcom,wb-display@1 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display1"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <1>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &sde_dsi { @@ -68,7 +83,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; }; &dsi_nt37801_amoled_cmd { From 14871db80d3cf61d59d4b5401cff84bd2db7143f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 1 Oct 2024 19:24:50 +0530 Subject: [PATCH 11/16] ARM: dts: msm: enable display on tuna trustedvm platforms Enable display on tuna trustedvm platforms. Change-Id: I0135626484601f55438135f4beeb6d114d50a559 Signed-off-by: Abhinav Saurabh --- ...trustedvm-tuna-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-tuna-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-cdp.dtsi | 161 ++++++++++++++++++ ...edvm-tuna-sde-display-mtp-kiwi-overlay.dts | 18 ++ .../trustedvm-tuna-sde-display-mtp-kiwi.dtsi | 6 + ...trustedvm-tuna-sde-display-mtp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-mtp.dtsi | 156 +++++++++++++++++ ...trustedvm-tuna-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-qrd.dtsi | 106 ++++++++++++ ...trustedvm-tuna-sde-display-rcm-overlay.dts | 18 ++ ...rustedvm-tuna-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-tuna-sde-display-rumi.dtsi | 10 ++ display/trustedvm-tuna-sde-display.dtsi | 28 +++ 13 files changed, 592 insertions(+) create mode 100644 display/trustedvm-tuna-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-qrd.dtsi create mode 100644 display/trustedvm-tuna-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi.dtsi create mode 100644 display/trustedvm-tuna-sde-display.dtsi diff --git a/display/trustedvm-tuna-sde-display-atp-overlay.dts b/display/trustedvm-tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..92d161b3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/display/trustedvm-tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..823d8b0c --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..bd14043b --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..b552bb5d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi new file mode 100644 index 00000000..e9428826 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display-mtp.dtsi" diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..4bd8c860 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>, <8 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp.dtsi b/display/trustedvm-tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..4738255d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/display/trustedvm-tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..5192b5e3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd.dtsi b/display/trustedvm-tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..f456854a --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/display/trustedvm-tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..2f339264 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/display/trustedvm-tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..665cb540 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi.dtsi b/display/trustedvm-tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..e9c1e520 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-tuna-sde-display.dtsi b/display/trustedvm-tuna-sde-display.dtsi new file mode 100644 index 00000000..22b2e5b0 --- /dev/null +++ b/display/trustedvm-tuna-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; From 259a4eb1c2f999cff963a0a33a32f5592f8445e6 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Wed, 23 Oct 2024 10:59:37 +0530 Subject: [PATCH 12/16] ARM: dts: msm: enable display support for vtdr panel on tuna CDP Enable display support for vtdr6130 panel on tuna CDP platform. Change-Id: I38016bc3ab0aaf82c27ae96ba01bd914022d07f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-cdp.dtsi | 62 +++++++ display/tuna-sde-display-cdp.dtsi | 70 ++++++++ display/tuna-sde-display-common.dtsi | 189 ++++++++++++++++++++ display/tuna-sde-display.dtsi | 29 +++ 4 files changed, 350 insertions(+) diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi index bd14043b..06e55839 100644 --- a/display/trustedvm-tuna-sde-display-cdp.dtsi +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -5,6 +5,38 @@ #include "trustedvm-tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -124,6 +156,36 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; }; diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index c275438b..cbc2df0f 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,43 @@ #include "tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -146,6 +183,39 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 21e45a58..beb59396 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -27,6 +27,12 @@ #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "tuna-sde-display-pinctrl.dtsi" @@ -121,6 +127,189 @@ /* PHY TIMINGS REVISION YYG with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index cbcbda6f..a3568aac 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -86,6 +86,35 @@ connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; }; +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-display-timings { timing@0 { From a33ce0f8f4d840e5a5667be57cc67486a4441654 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 11 Oct 2024 16:48:54 +0530 Subject: [PATCH 13/16] ARM: dts: msm: enable compilation for tuna trustedvm platforms Enable compilation for tuna trustedvm platforms. Change-Id: I5cf57ec9141fbf614c6ea99affe289d33db0cf68 Signed-off-by: Abhinav Saurabh --- Kbuild | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Kbuild b/Kbuild index dfa6c483..a9b829d6 100644 --- a/Kbuild +++ b/Kbuild @@ -39,6 +39,14 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ display/tuna-sde-display-qrd-overlay.dtbo \ display/tuna-sde-display-rumi-overlay.dtbo \ display/tuna-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rcm-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) From 7e1a9f881b43ee37c1e7950d8bfca74443c3cb2a Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 22 Oct 2024 13:05:22 +0530 Subject: [PATCH 14/16] ARM: dts: msm: add display support for Tuna MTP platforms Add display device tree support for MTP harmonium and MTP NFC platforms for Tuna. Change-Id: I7f7f935295081aabc227cfafba5ab1e0e87a3508 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 4 ++-- ...ustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} | 6 +++--- ...i => trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi} | 0 display/trustedvm-tuna-sde-display-mtp-overlay.dts | 2 +- ....dts => tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} | 6 +++--- ...p-kiwi.dtsi => tuna-sde-display-mtp-kiwi-harmonium.dtsi} | 2 +- display/tuna-sde-display-mtp-overlay.dts | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) rename display/{trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts => trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} (66%) rename display/{trustedvm-tuna-sde-display-mtp-kiwi.dtsi => trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi} (100%) rename display/{tuna-sde-display-mtp-kiwi-overlay.dts => tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} (66%) rename display/{tuna-sde-display-mtp-kiwi.dtsi => tuna-sde-display-mtp-kiwi-harmonium.dtsi} (76%) diff --git a/Kbuild b/Kbuild index a9b829d6..7d9c2e52 100644 --- a/Kbuild +++ b/Kbuild @@ -35,7 +35,7 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ display/tuna-sde-display-atp-overlay.dtbo \ display/tuna-sde-display-cdp-overlay.dtbo \ display/tuna-sde-display-mtp-overlay.dtbo \ - display/tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ display/tuna-sde-display-qrd-overlay.dtbo \ display/tuna-sde-display-rumi-overlay.dtbo \ display/tuna-sde-display-rcm-overlay.dtbo @@ -43,7 +43,7 @@ else dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \ display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \ display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \ - display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \ display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \ display/trustedvm-tuna-sde-display-rcm-overlay.dtbo diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts similarity index 66% rename from display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts rename to display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index b552bb5d..f5aaca03 100644 --- a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -7,12 +7,12 @@ /plugin/; #include "trustedvm-tuna-sde.dtsi" -#include "trustedvm-tuna-sde-display-mtp-kiwi.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi" / { - model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 2>; + qcom,board-id = <8 3>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi similarity index 100% rename from display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi rename to display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts index 4bd8c860..1aa64b70 100644 --- a/display/trustedvm-tuna-sde-display-mtp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -14,5 +14,5 @@ compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 0>, <8 1>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/tuna-sde-display-mtp-kiwi-overlay.dts b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts similarity index 66% rename from display/tuna-sde-display-mtp-kiwi-overlay.dts rename to display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index e826d973..e06a77e4 100644 --- a/display/tuna-sde-display-mtp-kiwi-overlay.dts +++ b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -6,12 +6,12 @@ /dts-v1/; /plugin/; -#include "tuna-sde-display-mtp-kiwi.dtsi" +#include "tuna-sde-display-mtp-kiwi-harmonium.dtsi" / { - model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 2>; + qcom,board-id = <8 3>; }; diff --git a/display/tuna-sde-display-mtp-kiwi.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi similarity index 76% rename from display/tuna-sde-display-mtp-kiwi.dtsi rename to display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index ddf34dc6..a4b9235b 100644 --- a/display/tuna-sde-display-mtp-kiwi.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -3,4 +3,4 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ - #include "tuna-sde-display-mtp.dtsi" +#include "tuna-sde-display-mtp.dtsi" diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts index 277cc2e7..49eee65c 100644 --- a/display/tuna-sde-display-mtp-overlay.dts +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 0>, <8 1>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; From b721cc974358dedc5079de4d45aa3272fa503c5b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 28 Oct 2024 13:11:42 +0530 Subject: [PATCH 15/16] ARM: dts: msm: add display support for SM8735P variant in tuna Add display support for SM8735P variant, SOC-ID: 694. Change-Id: I8c7a668727b52e67dabf7f0f4a7464f5ec880a84 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-atp-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-cdp-overlay.dts | 2 +- .../trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-mtp-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-qrd-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-rcm-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-rumi-overlay.dts | 2 +- display/tuna-sde-display-atp-overlay.dts | 2 +- display/tuna-sde-display-cdp-overlay.dts | 2 +- display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts | 2 +- display/tuna-sde-display-mtp-overlay.dts | 2 +- display/tuna-sde-display-qrd-overlay.dts | 2 +- display/tuna-sde-display-rcm-overlay.dts | 2 +- display/tuna-sde-display-rumi-overlay.dts | 2 +- display/tuna-sde.dts | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/display/trustedvm-tuna-sde-display-atp-overlay.dts b/display/trustedvm-tuna-sde-display-atp-overlay.dts index 92d161b3..0768b294 100644 --- a/display/trustedvm-tuna-sde-display-atp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", "qcom,atp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <33 0>; }; diff --git a/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/display/trustedvm-tuna-sde-display-cdp-overlay.dts index 823d8b0c..191aa7e0 100644 --- a/display/trustedvm-tuna-sde-display-cdp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", "qcom,cdp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <1 0>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index f5aaca03..9b5b7dab 100644 --- a/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 3>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts index 1aa64b70..f1dfe65f 100644 --- a/display/trustedvm-tuna-sde-display-mtp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/display/trustedvm-tuna-sde-display-qrd-overlay.dts index 5192b5e3..40d830d8 100644 --- a/display/trustedvm-tuna-sde-display-qrd-overlay.dts +++ b/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", "qcom,qrd"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <11 0>; }; diff --git a/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/display/trustedvm-tuna-sde-display-rcm-overlay.dts index 2f339264..c357378d 100644 --- a/display/trustedvm-tuna-sde-display-rcm-overlay.dts +++ b/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 0>, <21 1>; }; diff --git a/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/display/trustedvm-tuna-sde-display-rumi-overlay.dts index 665cb540..80b32374 100644 --- a/display/trustedvm-tuna-sde-display-rumi-overlay.dts +++ b/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <655 0x10000>, <694 0x10000>; qcom,board-id = <15 0>; }; diff --git a/display/tuna-sde-display-atp-overlay.dts b/display/tuna-sde-display-atp-overlay.dts index 87105863..99135b48 100644 --- a/display/tuna-sde-display-atp-overlay.dts +++ b/display/tuna-sde-display-atp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna ATP"; compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", "qcom,atp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <33 0>; }; diff --git a/display/tuna-sde-display-cdp-overlay.dts b/display/tuna-sde-display-cdp-overlay.dts index ac83131c..03f5795b 100644 --- a/display/tuna-sde-display-cdp-overlay.dts +++ b/display/tuna-sde-display-cdp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna CDP"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", "qcom,cdp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <1 0>; }; diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index e06a77e4..d33cda40 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts +++ b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 3>; }; diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts index 49eee65c..46106183 100644 --- a/display/tuna-sde-display-mtp-overlay.dts +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/tuna-sde-display-qrd-overlay.dts b/display/tuna-sde-display-qrd-overlay.dts index b422a057..c650759d 100644 --- a/display/tuna-sde-display-qrd-overlay.dts +++ b/display/tuna-sde-display-qrd-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna QRD"; compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", "qcom,qrd"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <11 0>; }; diff --git a/display/tuna-sde-display-rcm-overlay.dts b/display/tuna-sde-display-rcm-overlay.dts index 3adf6685..a3d546fe 100644 --- a/display/tuna-sde-display-rcm-overlay.dts +++ b/display/tuna-sde-display-rcm-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna RCM"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 0>, <21 1>; }; diff --git a/display/tuna-sde-display-rumi-overlay.dts b/display/tuna-sde-display-rumi-overlay.dts index d7f33da6..d01e5b1d 100644 --- a/display/tuna-sde-display-rumi-overlay.dts +++ b/display/tuna-sde-display-rumi-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna RUMI"; compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <655 0x10000>, <694 0x10000>; qcom,board-id = <15 0>; }; diff --git a/display/tuna-sde.dts b/display/tuna-sde.dts index b9a80b12..e45c8b27 100644 --- a/display/tuna-sde.dts +++ b/display/tuna-sde.dts @@ -9,6 +9,6 @@ #include "tuna-sde.dtsi" / { - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <0 0>; }; From 459ad4fd04044cb8af16f20c7bfd7ce53719db3a Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Mon, 14 Oct 2024 09:39:36 +0530 Subject: [PATCH 16/16] ARM: dts: msm: update dither count as per hw capability This change updates number of pingpong dither supported for sun target. Change-Id: Ie4685d349e8a56b6fb1017409168347b48145992 Signed-off-by: Mahadevan Signed-off-by: lnxdisplay --- display/sun-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 12270f64..0b0c405c 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -110,7 +110,7 @@ qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 - 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; qcom,sde-dither-version = <0x00020000>; qcom,sde-dither-size = <0x20>;