Merge 41d98cfe5d on remote branch

Change-Id: Ibdecae9bc8447539006af0e373f021194ab0efa9
This commit is contained in:
Linux Build Service Account
2025-01-04 07:36:59 -08:00
7 changed files with 43 additions and 8 deletions

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@@ -59,6 +59,7 @@
}; };
&swr0 { &swr0 {
qcom,swr-num-dev = <2>;
wsa884x_0220: wsa884x@02170220 { wsa884x_0220: wsa884x@02170220 {
status = "okay"; status = "okay";
}; };
@@ -68,6 +69,10 @@
}; };
}; };
&swr1 {
qcom,swr-num-dev = <2>;
};
&kera_snd { &kera_snd {
qcom,model = "kera-cdp-snd-card"; qcom,model = "kera-cdp-snd-card";
swr-haptics-unsupported; swr-haptics-unsupported;
@@ -79,7 +84,6 @@
"AMIC3", "Analog Mic3", "AMIC3", "Analog Mic3",
"AMIC3", "MIC BIAS3", "AMIC3", "MIC BIAS3",
"AMIC4", "Analog Mic4", "AMIC4", "Analog Mic4",
"AMIC4", "MIC BIAS4",
"VA AMIC1", "Analog Mic1", "VA AMIC1", "Analog Mic1",
"VA AMIC1", "VA MIC BIAS1", "VA AMIC1", "VA MIC BIAS1",
"VA AMIC2", "Analog Mic2", "VA AMIC2", "Analog Mic2",
@@ -87,7 +91,6 @@
"VA AMIC3", "Analog Mic3", "VA AMIC3", "Analog Mic3",
"VA AMIC3", "VA MIC BIAS3", "VA AMIC3", "VA MIC BIAS3",
"VA AMIC4", "Analog Mic4", "VA AMIC4", "Analog Mic4",
"VA AMIC4", "VA MIC BIAS4",
"TX DMIC0", "Digital Mic0", "TX DMIC0", "Digital Mic0",
"TX DMIC0", "MIC BIAS3", "TX DMIC0", "MIC BIAS3",
"TX DMIC1", "Digital Mic1", "TX DMIC1", "Digital Mic1",

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@@ -25,7 +25,7 @@
}; };
&swr2 { &swr2 {
reg = <0x7630000 0x0>; swrm-io-base = <0x7630000 0x0>;
}; };
&va_macro { &va_macro {

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@@ -30,6 +30,10 @@
}; };
}; };
&cdc_pri_mi2s_gpios {
status = "okay";
};
&swr1 { &swr1 {
qcom,swr-num-dev = <2>; qcom,swr-num-dev = <2>;
}; };

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@@ -417,7 +417,7 @@
qcom,model = "kera-qrd-snd-card"; qcom,model = "kera-qrd-snd-card";
qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>; qcom,mi2s-tdm-is-hw-vote-needed = <1>, <1>, <1>, <1>, <1>, <1>, <1>;
qcom,wcn-bt = <0>; qcom,wcn-bt = <1>;
qcom,ext-disp-audio-rx = <0>; qcom,ext-disp-audio-rx = <0>;
qcom,tdm-max-slots = <8>; qcom,tdm-max-slots = <8>;
qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>; qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
@@ -479,6 +479,8 @@
qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-hphl-swh = <0>;
qcom,msm-mbhc-gnd-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>;
qcom,wsa-max-devs = <1>; qcom,wsa-max-devs = <1>;
qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>, qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
<&lpass_cdc>, <&lpass_bt_swr>; <&lpass_cdc>, <&lpass_bt_swr>;
@@ -489,9 +491,9 @@
compatible = "qcom,msm-cdc-pinctrl"; compatible = "qcom,msm-cdc-pinctrl";
pinctrl-names = "aud_active", "aud_sleep"; pinctrl-names = "aud_active", "aud_sleep";
pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active pinctrl-0 = <&i2s0_sck_active &i2s0_ws_active
&i2s0_sd0_active &i2s0_sd1_active>; &i2s0_sd0_active>;
pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep pinctrl-1 = <&i2s0_sck_sleep &i2s0_ws_sleep
&i2s0_sd0_sleep &i2s0_sd1_sleep>; &i2s0_sd0_sleep>;
#gpio-cells = <0>; #gpio-cells = <0>;
}; };

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@@ -83,4 +83,5 @@
asoc-codec-names = "msm-stub-codec.1", "lpass-cdc", asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
"wcd9378_codec", "wsa-codec1"; "wcd9378_codec", "wsa-codec1";
qcom,wsa-max-devs = <1>; qcom,wsa-max-devs = <1>;
fsa4480-i2c-handle = <&fsa4480>;
}; };

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@@ -35,7 +35,19 @@
reg = <0x7660000 0x0>; reg = <0x7660000 0x0>;
clock-names = "lpass_audio_hw_vote"; clock-names = "lpass_audio_hw_vote";
clocks = <&lpass_audio_hw_vote 0>; clocks = <&lpass_audio_hw_vote 0>;
qcom,va-dmic-sample-rate = <600000>; /*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,va-dmic-clk-div-factor = <16 16 16 16>;
qcom,va-clk-mux-select = <1>; qcom,va-clk-mux-select = <1>;
qcom,default-clk-id = <TX_CORE_CLK>; qcom,default-clk-id = <TX_CORE_CLK>;
qcom,use-clk-id = <VA_CORE_CLK>; qcom,use-clk-id = <VA_CORE_CLK>;
@@ -81,7 +93,19 @@
compatible = "qcom,lpass-cdc-tx-macro"; compatible = "qcom,lpass-cdc-tx-macro";
reg = <0x6AE0000 0x0>; reg = <0x6AE0000 0x0>;
qcom,default-clk-id = <TX_CORE_CLK>; qcom,default-clk-id = <TX_CORE_CLK>;
qcom,tx-dmic-sample-rate = <2400000>; /*
* Clk divding factors for each DMIC pair.
* Valid entries for each DMIC pair:
* 2, 3, 4, 6, 8, 16
*
* These factors are translated to corresponding config values
* for the following registers,
* -- LPASS_VA_TOP_CSR_DMIC0_CTL,
* -- LPASS_VA_TOP_CSR_DMIC1_CTL,
* -- LPASS_VA_TOP_CSR_DMIC2_CTL,
* -- LPASS_VA_TOP_CSR_DMIC3_CTL,
*/
qcom,tx-dmic-clk-div-factor = <4 4 4 4>;
qcom,is-used-swr-gpio = <0>; qcom,is-used-swr-gpio = <0>;
}; };

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@@ -30,6 +30,7 @@
compatible = "qcom,gpr"; compatible = "qcom,gpr";
qcom,glink-channels = "adsp_apps"; qcom,glink-channels = "adsp_apps";
qcom,intents = <0x200 20>; qcom,intents = <0x200 20>;
qcom,ch-sched-rt;
reg = <GPR_DOMAIN_ADSP>; reg = <GPR_DOMAIN_ADSP>;
spf_core { spf_core {