Merge e41cbf21f3 on remote branch
Change-Id: I4480ad09e60854eafd24afba64534e81fdac09eb
This commit is contained in:
Linux Build Service Account
@@ -27,6 +27,7 @@ properties:
|
||||
- qcom,sys-pm-monaco-auto
|
||||
- qcom,sys-pm-sun
|
||||
- qcom,sys-pm-tuna
|
||||
- qcom,sys-pm-kera
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -50,6 +51,7 @@ allOf:
|
||||
enum:
|
||||
- qcom,sys-pm-sun
|
||||
- qcom,sys-pm-tuna
|
||||
- qcom,sys-pm-kera
|
||||
- qcom,sys-pm-pineapple
|
||||
- qcom,sys-pm-parrot
|
||||
- qcom,sys-pm-ravelin
|
||||
|
||||
@@ -20,9 +20,11 @@ properties:
|
||||
- qcom,sun-debugcc
|
||||
- qcom,parrot-debugcc
|
||||
- qcom,sdx75-debugcc
|
||||
- qcom,sdxbaagha-debugcc
|
||||
- qcom,sm4450-debugcc
|
||||
- qcom,monaco-debugcc
|
||||
- qcom,tuna-debugcc
|
||||
- qcom,kera-debugcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@@ -27,6 +27,7 @@ description: |
|
||||
dt-bindings/clock/qcom,gpucc-parrot.h
|
||||
dt-bindings/clock/qcom,gpucc-monaco.h
|
||||
dt-bindings/clock/qcom,gpucc-tuna.h
|
||||
dt-bindings/clock/qcom,gpucc-kera.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@@ -45,6 +46,7 @@ properties:
|
||||
- qcom,parrot-gpucc
|
||||
- qcom,monaco-gpucc
|
||||
- qcom,tuna-gpucc
|
||||
- qcom,kera-gpucc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@@ -15,12 +15,13 @@ description: |
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gxclkctl-sun.h
|
||||
dt-bindings/clock/qcom,gpucc-tuna.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sun-gx_clkctl
|
||||
|
||||
- qcom,tuna-gx_clkctl
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@@ -26,6 +26,7 @@ properties:
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sdx65-rpmh-clk
|
||||
- qcom,sdx75-rpmh-clk
|
||||
- qcom,sdxbaagha-rpmh-clk
|
||||
- qcom,sm4450-rpmh-clk
|
||||
- qcom,sm6350-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
|
||||
60
bindings/clock/qcom,sdxbaagha-gcc.yaml
Normal file
60
bindings/clock/qcom,sdxbaagha-gcc.yaml
Normal file
@@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdxbaagha-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Global Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Global clock control module which supports the clocks, resets and
|
||||
power domains on sdxbaagha
|
||||
|
||||
See also:
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||||
- dt-bindings/clock/qcom,gcc-sdxbaagha.h
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdxbaagha-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: PCIE Pipe clock source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: pcie_pipe_clk
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
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||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@80000 {
|
||||
compatible = "qcom,sdxbaagha-gcc";
|
||||
reg = <0x80000 0x1f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&pcie_pipe_clk>,<&sleep_clk>;
|
||||
clock-names = "bi_tcxo","bi_tcxo_ao",
|
||||
"pcie_pipe_clk","sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -161,6 +161,13 @@ properties:
|
||||
method is used for LRA resonant frequency detection.
|
||||
type: boolean
|
||||
|
||||
qcom,hbst-ovp-trim:
|
||||
description: |
|
||||
Boolean flag indicating that the hBoost OVP trim PBS sequence would be
|
||||
triggered during driver initialization. This is only applicable for HAP530_HV
|
||||
haptics module.
|
||||
type: boolean
|
||||
|
||||
patternProperties:
|
||||
".*hap-swr-slave-reg$":
|
||||
description: |
|
||||
|
||||
@@ -89,6 +89,14 @@ properties:
|
||||
- qcom,sdx65-mc-virt
|
||||
- qcom,sdx65-mem-noc
|
||||
- qcom,sdx65-system-noc
|
||||
- qcom,sdxbaagha-aggre_noc,
|
||||
- qcom,sdxbaagha-cnoc_main,
|
||||
- qcom,sdxbaagha-dc_noc,
|
||||
- qcom,sdxbaagha-mc_virt,
|
||||
- qcom,sdxbaagha-clk_virt,
|
||||
- qcom,sdxbaagha-pcie_anoc,
|
||||
- qcom,sdxbaagha-mem_noc,
|
||||
- qcom,sdxbaagha-system_noc,
|
||||
- qcom,sm8150-aggre1-noc
|
||||
- qcom,sm8150-aggre2-noc
|
||||
- qcom,sm8150-camnoc-noc
|
||||
@@ -198,6 +206,20 @@ properties:
|
||||
- qcom,tuna-nsp_noc
|
||||
- qcom,tuna-pcie_anoc
|
||||
- qcom,tuna-system_noc
|
||||
- qcom,kera-aggre1_noc
|
||||
- qcom,kera-aggre2_noc
|
||||
- qcom,kera-clk_virt
|
||||
- qcom,kera-cnoc_cfg
|
||||
- qcom,kera-cnoc_main
|
||||
- qcom,kera-gem_noc
|
||||
- qcom,kera-lpass_ag_noc
|
||||
- qcom,kera-lpass_lpiaon_noc
|
||||
- qcom,kera-lpass_lpicx_noc
|
||||
- qcom,kera-mc_virt
|
||||
- qcom,kera-mmss_noc
|
||||
- qcom,kera-nsp_noc
|
||||
- qcom,kera-pcie_anoc
|
||||
- qcom,kera-system_noc
|
||||
|
||||
'#interconnect-cells': true
|
||||
|
||||
|
||||
386
bindings/leds/backlight/qcom-spmi-wled.yaml
Normal file
386
bindings/leds/backlight/qcom-spmi-wled.yaml
Normal file
@@ -0,0 +1,386 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/leds/backlight/qcom-spmi-wled.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. WLED (White Light Emitting Diode) driver
|
||||
|
||||
maintainers:
|
||||
- Jishnu Prakash <quic_jprakash@quicinc.com>
|
||||
|
||||
description: >
|
||||
WLED (White Light Emitting Diode) driver is used for controlling display
|
||||
backlight that is part of PMIC on Qualcomm Technologies, Inc. reference
|
||||
platforms. The PMIC is connected to the host processor via SPMI bus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pmi8998-spmi-wled
|
||||
- qcom,pm8150l-spmi-wled
|
||||
- qcom,pm6150l-spmi-wled
|
||||
- qcom,pm660l-spmi-wled
|
||||
- qcom,pm7325b-spmi-wled
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: Base address and size of the WLED modules.
|
||||
|
||||
reg-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Names associated with base addresses. should be
|
||||
"wled-ctrl-base", "wled-sink-base".
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
Interrupts associated with WLED. Interrupts can be specified as per the encoding listed
|
||||
under Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt.
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: sc-irq
|
||||
- const: ovp-irq
|
||||
- const: pre-flash-irq
|
||||
- const: flash-irq
|
||||
|
||||
label: true
|
||||
|
||||
default-brightness:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Brightness value on boot. Default is 2048.
|
||||
For pmi8998, it is 0-4095.
|
||||
For pm8150l, this can vary from 0-4095 or 0-32767 depending
|
||||
on the brightness control mode. If CABC is enabled, 0-4095
|
||||
range is used.
|
||||
|
||||
max-brightness:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Maximum brightness level. Allowed values are
|
||||
For pmi8998, it is 4095.
|
||||
For pm8150l, this can be either 4095 or 32767.
|
||||
If CABC is enabled, this is capped to 4095.
|
||||
|
||||
qcom,fs-current-limit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
per-string full scale current limit in uA. value from
|
||||
0 to 30000 with 5000 uA resolution.
|
||||
default is 25000 uA
|
||||
|
||||
qcom,boost-current-limit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
ILIM threshold in mA. values are 105, 280, 450, 620, 970,
|
||||
1150, 1300, 1500.
|
||||
default is 970 mA
|
||||
|
||||
qcom,switching-freq:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Switching frequency in KHz. values are
|
||||
600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371,
|
||||
1600, 1920, 2400, 3200, 4800, 9600.
|
||||
default is 800 KHz
|
||||
|
||||
qcom,ovp:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Over-voltage protection limit in mV. values are 31100,
|
||||
29600, 19600, 18100.
|
||||
default is 29600 mV
|
||||
|
||||
qcom,string-cfg:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Bit mask of the WLED strings. Bit 0 to 3 indicates strings
|
||||
0 to 3 respectively. WLED module has four strings of leds
|
||||
numbered from 0 to 3. Each string of leds are operated
|
||||
individually. Specify the strings using the bit mask. Any
|
||||
combination of led strings can be used.
|
||||
Default value is 15 (b1111).
|
||||
|
||||
qcom,en-cabc:
|
||||
type: boolean
|
||||
description: |
|
||||
Specify if cabc (content adaptive backlight control) is
|
||||
needed.
|
||||
|
||||
qcom,ext-pfet-sc-pro-en:
|
||||
type: boolean
|
||||
description: |
|
||||
Specify if external PFET control for short circuit
|
||||
protection is needed. This is not applicable for PM8150L.
|
||||
|
||||
qcom,auto-calibration:
|
||||
type: boolean
|
||||
description: |
|
||||
Enables auto-calibration of the WLED sink configuration.
|
||||
|
||||
qcom,modulator-sel:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Selects the modulator used for brightness modulation.
|
||||
Allowed values are
|
||||
0 - Modulator A
|
||||
1 - Modulator B
|
||||
If not specified, then modulator A will be used by default.
|
||||
This property is applicable only to WLED5 peripheral.
|
||||
|
||||
qcom,cabc-sel:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Selects the CABC pin signal used for brightness modulation.
|
||||
Allowed values are
|
||||
0 - CABC disabled
|
||||
1 - CABC 1
|
||||
2 - CABC 2
|
||||
3 - External signal (e.g. LPG) is used for dimming
|
||||
This property is applicable only to WLED5 peripheral.
|
||||
|
||||
qcom,leds-per-string:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
If specified, can be used to calculate available current
|
||||
during selfie flash operation. If not specified, available
|
||||
current calculated is simply the configured threshold.
|
||||
|
||||
io-channels:
|
||||
maxItems: 3
|
||||
description: |
|
||||
IIO channel specifiers for each name in io-channel-names.
|
||||
|
||||
io-channel-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: |
|
||||
Names of the IIO channels that are used by WLED.
|
||||
For details about IIO bindings refer below
|
||||
Documentation/devicetree/bindings/iio/iio-bindings.txt
|
||||
|
||||
qcom,use-exp-dimming:
|
||||
type: boolean
|
||||
description: |
|
||||
Specifies that exponential dimming lookup table values should be used.
|
||||
|
||||
qcom,exp-dimming-map:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
It specifies a table of brightness values that can be programmed
|
||||
into WLED_SINK for exponential dimming which provides smooth brightness
|
||||
change. There should be exactly 256 values in the table and they should
|
||||
be at most 15 bits long. This table would be used only if the
|
||||
"qcom,use-exp-dimming" property is set. This feature is supported from
|
||||
PM7325B onwards.
|
||||
|
||||
qcom,slew-ramp-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Software brightness slew ramp time values in ms. This is supported from
|
||||
PM7325B onwards.
|
||||
Valid values are 2, 4, 8, 64, 128, 192, 256, 320, 384, 448, 512, 704, 896,
|
||||
1024, 2048, 4096.
|
||||
default is 256
|
||||
|
||||
patternProperties:
|
||||
"^wled_torch[0-9a-f]+$":
|
||||
type: object
|
||||
$ref: common.yaml#
|
||||
unevaluatedProperties: false
|
||||
description: Properties for wled_torch.
|
||||
|
||||
properties:
|
||||
label:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Should be "torch".
|
||||
|
||||
qcom,default-led-trigger:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Name for LED trigger. If unspecified, "wled_torch" is used.
|
||||
|
||||
qcom,wled-torch-fsc:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED torch full scale current in mA. This configures the
|
||||
maximum current allowed for torch device. Allowed values
|
||||
are from 5 to 60 mA with a step of 5 mA. If not specified,
|
||||
default value is set to 30 mA.
|
||||
|
||||
qcom,wled-torch-step:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED torch step delay in us. This configures the step delay
|
||||
when the output is ramped up to the desired target current.
|
||||
Allowed values are from 50 to 400 us with a step of 50 us.
|
||||
If not specified, default value is set to 200 us.
|
||||
|
||||
qcom,wled-torch-timer:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED torch safety timer in ms. This configures the safety
|
||||
timer to turn off torch automatically after timer expiry.
|
||||
Allowed values are 50, 100, 200, 400, 600, 800, 1000 and
|
||||
1200. If not specified, default value is set to 1200 ms.
|
||||
|
||||
|
||||
required:
|
||||
- label
|
||||
|
||||
"^wled_flash[0-9a-f]+$":
|
||||
type: object
|
||||
$ref: common.yaml#
|
||||
unevaluatedProperties: false
|
||||
description: wled_flash child subnode properties
|
||||
|
||||
properties:
|
||||
label:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Should be "flash".
|
||||
|
||||
qcom,default-led-trigger:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Name for LED trigger. If unspecified, "wled_flash" is used.
|
||||
|
||||
qcom,wled-flash-fsc:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED flash full scale current in mA. This configures the
|
||||
maximum current allowed for flash device. Allowed values
|
||||
are from 5 to 60 mA with a step of 5 mA. If not specified,
|
||||
default value is set to 40 mA.
|
||||
|
||||
qcom,wled-flash-step:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED flash step delay in us. This configures the step delay
|
||||
when the output is ramped up to the desired target current.
|
||||
Allowed values are from 50 to 400 us with a step of 50 us.
|
||||
If not specified, default value is set to 200 us.
|
||||
|
||||
qcom,wled-flash-timer:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
WLED flash safety timer in ms. This configures the safety
|
||||
timer to turn off flash automatically after timer expiry.
|
||||
Allowed values are 50, 100, 200, 400, 600, 800, 1000 and
|
||||
1200. If not specified, default value is set to 100 ms.
|
||||
|
||||
required:
|
||||
- label
|
||||
|
||||
"^wled_switch[0-9a-f]+$":
|
||||
type: object
|
||||
$ref: common.yaml#
|
||||
unevaluatedProperties: false
|
||||
description: wled_switch child subnode properties
|
||||
|
||||
properties:
|
||||
label:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Should be "switch".
|
||||
|
||||
qcom,default-led-trigger:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: |
|
||||
Name for LED trigger. If unspecified, "wled_switch" is used.
|
||||
|
||||
required:
|
||||
- label
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- label
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
qcom-wled@d800 {
|
||||
compatible = "qcom,pmi8998-spmi-wled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xd800 0xd900>;
|
||||
reg-names = "wled-ctrl-base", "wled-sink-base";
|
||||
label = "backlight";
|
||||
|
||||
interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>,
|
||||
<0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "sc-irq", "ovp-irq";
|
||||
qcom,fs-current-limit = <25000>;
|
||||
qcom,boost-current-limit = <970>;
|
||||
qcom,switching-freq = <800>;
|
||||
qcom,ovp = <29600>;
|
||||
qcom,string-cfg = <15>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/iio/qti_power_supply_iio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
qcom-wled@d800 {
|
||||
compatible = "qcom,pm8150l-spmi-wled";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xd800 0x100>, <0xd900 0x100>;
|
||||
reg-names = "wled-ctrl-base", "wled-sink-base";
|
||||
label = "backlight";
|
||||
|
||||
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ovp-irq";
|
||||
qcom,string-cfg = <7>;
|
||||
|
||||
io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>,
|
||||
<&pm7250b_qg PSY_IIO_VOLTAGE_OCV>,
|
||||
<&pm7250b_qg PSY_IIO_CURRENT_NOW>;
|
||||
|
||||
io-channel-names = "rbatt",
|
||||
"voltage_ocv",
|
||||
"current_now";
|
||||
|
||||
wled_torch: qcom,wled-torch {
|
||||
label = "torch";
|
||||
qcom,wled-torch-fsc = <40>;
|
||||
qcom,wled-torch-step = <300>;
|
||||
qcom,wled-torch-timer = <600>;
|
||||
};
|
||||
|
||||
wled_flash: qcom,wled-flash {
|
||||
label = "flash";
|
||||
qcom,wled-flash-fsc = <60>;
|
||||
qcom,wled-flash-step = <100>;
|
||||
qcom,wled-flash-timer = <200>;
|
||||
};
|
||||
|
||||
wled_switch: qcom,wled-switch {
|
||||
label = "switch";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
qcom,leds@d800 {
|
||||
compatible = "qcom,pm660l-spmi-wled";
|
||||
reg = <0xd800 0x100>,
|
||||
<0xd900 0x100>;
|
||||
reg-names = "qpnp-wled-ctrl-base",
|
||||
"qpnp-wled-sink-base";
|
||||
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ovp-irq";
|
||||
linux,name = "wled";
|
||||
linux,default-led-trigger = "bkl-trigger";
|
||||
|
||||
};
|
||||
190
bindings/pinctrl/qcom,kera-vm-tlmm.yaml
Normal file
190
bindings/pinctrl/qcom,kera-vm-tlmm.yaml
Normal file
@@ -0,0 +1,190 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,kera-vm-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Kera VM TLMM block
|
||||
|
||||
maintainers:
|
||||
- Murali Nalajala <quic_mnalajal@quicinc.com>
|
||||
- Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block for VM.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,kera-vm-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts-extended: true
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
|
||||
gpio-controller: true
|
||||
'#gpio-cells': true
|
||||
gpio-ranges: true
|
||||
gpios:
|
||||
description: array of gpio pin number required by VM TLMM clients
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'-state$':
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-kera-vm-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-kera-vm-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-kera-vm-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
|
||||
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
atest_char_start, atest_usb0, atest_usb00, atest_usb01,
|
||||
atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
|
||||
audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
|
||||
cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
|
||||
cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
|
||||
cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
|
||||
cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
|
||||
cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
|
||||
cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
|
||||
coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
|
||||
ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
|
||||
gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
|
||||
i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
|
||||
i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
|
||||
i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
|
||||
i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
|
||||
i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
|
||||
i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
|
||||
i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
|
||||
mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
|
||||
mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
|
||||
nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
|
||||
phase_flag10, phase_flag11, phase_flag12, phase_flag13,
|
||||
phase_flag14, phase_flag15, phase_flag16, phase_flag17,
|
||||
phase_flag18, phase_flag19, phase_flag2, phase_flag20,
|
||||
phase_flag21, phase_flag22, phase_flag23, phase_flag24,
|
||||
phase_flag25, phase_flag26, phase_flag27, phase_flag28,
|
||||
phase_flag29, phase_flag3, phase_flag30, phase_flag31,
|
||||
phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
|
||||
phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
|
||||
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
|
||||
qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
|
||||
qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
|
||||
qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
|
||||
qlink_big_enable, qlink_big_request, qlink_little_enable,
|
||||
qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
|
||||
qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
|
||||
qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
|
||||
qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
|
||||
qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
|
||||
qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
|
||||
qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
|
||||
qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
|
||||
qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
|
||||
qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
|
||||
qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
|
||||
qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
|
||||
qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
|
||||
qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
|
||||
qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
|
||||
qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
|
||||
sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
|
||||
tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
|
||||
tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
|
||||
uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
|
||||
uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
|
||||
vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]
|
||||
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
|
||||
- if:
|
||||
properties:
|
||||
pins:
|
||||
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
|
||||
then:
|
||||
required:
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pinctrl@f100000 {
|
||||
compatible = "qcom,kera-vm-tlmm";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 211>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts-extended = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-wo-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-state {
|
||||
rx-pins {
|
||||
pins = "gpio26";
|
||||
function = "qup1_se7_l0";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
pins = "gpio27";
|
||||
function = "qup1_se7_l1";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -28,6 +28,7 @@ properties:
|
||||
- qcom,pm6450-gpio
|
||||
- qcom,pm7250b-gpio
|
||||
- qcom,pm7325-gpio
|
||||
- qcom,pm7325b-gpio
|
||||
- qcom,pm7550ba-gpio
|
||||
- qcom,pm8005-gpio
|
||||
- qcom,pm8008-gpio
|
||||
@@ -73,6 +74,7 @@ properties:
|
||||
- qcom,pmx55-gpio
|
||||
- qcom,pmx65-gpio
|
||||
- qcom,pmx75-gpio
|
||||
- qcom,pmx35-gpio
|
||||
- qcom,pmxr2230-gpio
|
||||
|
||||
- enum:
|
||||
@@ -183,8 +185,10 @@ allOf:
|
||||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8550ve-gpio
|
||||
- qcom,pm8950-gpio
|
||||
- qcom,pm7325b-gpio
|
||||
- qcom,pm7550ba-gpio
|
||||
- qcom,pmi632-gpio
|
||||
- qcom,pmx35-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
@@ -441,6 +445,7 @@ $defs:
|
||||
- gpio1-gpio9 for pm6450
|
||||
- gpio1-gpio12 for pm7250b
|
||||
- gpio1-gpio10 for pm7325
|
||||
- gpio1-gpio8 for pm7325b
|
||||
- gpio1-gpio8 for pm7550ba
|
||||
- gpio1-gpio4 for pm8005
|
||||
- gpio1-gpio2 for pm8008
|
||||
@@ -483,6 +488,7 @@ $defs:
|
||||
- gpio1-gpio2 for pmr735d
|
||||
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
|
||||
and gpio10)
|
||||
- gpio1-gpio8 for pmx35
|
||||
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
|
||||
and gpio11)
|
||||
- gpio1-gpio16 for pmx65
|
||||
|
||||
@@ -33,6 +33,11 @@ properties:
|
||||
to be enabled only on platforms where voltage needs to
|
||||
be ramped up with multiple steps.
|
||||
|
||||
qcom,ncp-symmetry:
|
||||
type: boolean
|
||||
description: Enabling this will make NCP voltage follow LDO voltage
|
||||
directly.
|
||||
|
||||
qcom,pwrdn-delay-ms:
|
||||
description: Required to control the LDO power down delay.
|
||||
Possible values are 0, 1, 4, 8.
|
||||
@@ -44,13 +49,30 @@ properties:
|
||||
qcom,pwrup-config:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Controls the order of powering up BOOST, LDO AND NCP
|
||||
blocks. Appilcable for PM7325B. Possible values are 0, 1, 2, 3, 4.
|
||||
blocks. Applicable for PM7325B. Possible values are 0, 1, 2, 3, 4.
|
||||
0 - Boost, LDO, NCP
|
||||
1 - Boost, LDO
|
||||
2 - Boost, NCP
|
||||
3 - Boost only
|
||||
4 - Boost, NCP, LDO
|
||||
|
||||
qcom,high-p2-blank-time-ns:
|
||||
description: Controls the higher clamp threshold for p2 minimum on time.
|
||||
Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,
|
||||
189, 220, 250.
|
||||
|
||||
qcom,low-p2-blank-time-ns:
|
||||
description: Controls the lower clamp threshold for p2 minimum on time.
|
||||
Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,
|
||||
189, 220, 250.
|
||||
|
||||
qcom,mpc-current-thr-ma:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Controls the mpc threshold for inductor current after start up
|
||||
is done. Applicable for PM7325B. Possible values are 160, 200, 240,
|
||||
280, 320, 360, 400, 440.
|
||||
|
||||
|
||||
qcom,ttw-enable:
|
||||
type: boolean
|
||||
description: Touch to wake-up support enabled.
|
||||
|
||||
@@ -79,6 +79,7 @@ properties:
|
||||
- qcom,monaco-modem-pas
|
||||
- qcom,monaco-adsp-pas
|
||||
- qcom,tuna-wpss-pas
|
||||
- qcom,kera-wpss-pas
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -21,6 +21,7 @@ properties:
|
||||
- qcom,sun-pcie-pdc
|
||||
- qcom,pineapple-pcie-pdc
|
||||
- qcom,cliffs-pcie-pdc
|
||||
- qcom,tuna-pcie-pdc
|
||||
- qcom,pcie-pdc
|
||||
|
||||
reg:
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. (QTI) Stats bindings
|
||||
title: Qualcomm Technologies, Inc. SoC LPM stats
|
||||
|
||||
maintainers:
|
||||
- Maulik Shah <mkshah@codeaurora.org>
|
||||
@@ -25,6 +25,7 @@ properties:
|
||||
- qcom,rpmh-stats-v4
|
||||
- qcom,sdm845-rpmh-stats
|
||||
- qcom,rpm-stats
|
||||
- qcom,rpm-stats-v2
|
||||
# For older RPM firmware versions with fixed offset for the sleep stats
|
||||
- qcom,apq8084-rpm-stats
|
||||
- qcom,msm8226-rpm-stats
|
||||
|
||||
@@ -23,8 +23,10 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,bcl-v5
|
||||
description: msm battery state of charge device
|
||||
items:
|
||||
- const: qcom,bcl-v5
|
||||
- const: qcom,pm8550-bcl-v5
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -96,3 +98,16 @@ examples:
|
||||
qcom,bcl-mon-vbat-only;
|
||||
qcom,pmic7-threshold;
|
||||
};
|
||||
|
||||
bcl@4700 {
|
||||
compatible = "qcom,pm8550-bcl-v5";
|
||||
reg = <0x4700 0x100>;
|
||||
interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>,
|
||||
<0x1 0x47 0x1 IRQ_TYPE_NONE>,
|
||||
<0x1 0x47 0x2 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "bcl-lvl0",
|
||||
"bcl-lvl1",
|
||||
"bcl-lvl2";
|
||||
qcom,pmic7-threshold;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
@@ -71,6 +71,11 @@ properties:
|
||||
phandle to eUSB2 repeater for enforcing probe ordering for eUSB2 repeater
|
||||
and eUSB2 PHY driver.
|
||||
|
||||
vdd_refgen-supply:
|
||||
description: |
|
||||
phandle to vote for additional refgen ldo. This is generally board/target
|
||||
specific.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -56,7 +56,9 @@ TUNA_BASE_DTB += tuna.dtb tuna7.dtb
|
||||
NOAPQ_TUNA_BOARDS += \
|
||||
tuna-atp-overlay.dtbo \
|
||||
tuna-cdp-overlay.dtbo \
|
||||
tuna-mtp-kiwi-harmonium-overlay.dtbo \
|
||||
tuna-mtp-kiwi-overlay.dtbo \
|
||||
tuna-mtp-nfc-overlay.dtbo \
|
||||
tuna-mtp-overlay.dtbo \
|
||||
tuna-mtp-qmp1000-overlay.dtbo \
|
||||
tuna-mtp-kiwi-pmd802x-overlay.dtbo \
|
||||
@@ -235,6 +237,14 @@ dtb-y += $(tuna_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_KERA), y)
|
||||
ifeq ($(CONFIG_ARCH_QTI_VM), y)
|
||||
kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb \
|
||||
kera-oemvm-rumi.dtb
|
||||
dtb-y += $(kera_tuivm-dtb-y)
|
||||
endif
|
||||
endif
|
||||
|
||||
MONACO_BASE_DTB += monaco.dtb monacop.dtb
|
||||
|
||||
MONACO_BOARDS += \
|
||||
|
||||
15
qcom/kera-oemvm-rumi.dts
Normal file
15
qcom/kera-oemvm-rumi.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "kera-oemvm.dtsi"
|
||||
#include "kera-oemvm-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera OEMVM RUMI";
|
||||
compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi";
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
8
qcom/kera-oemvm-rumi.dtsi
Normal file
8
qcom/kera-oemvm-rumi.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
218
qcom/kera-oemvm.dtsi
Normal file
218
qcom/kera-oemvm.dtsi
Normal file
@@ -0,0 +1,218 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
qcom,msm-id = <659 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
boot-config = "fdt,unified";
|
||||
os-type = "linux";
|
||||
kernel-entry-segment = "kernel";
|
||||
kernel-entry-offset = <0x0 0x0>;
|
||||
vendor = "QTI";
|
||||
image-name = "qcom,oemvm";
|
||||
qcom,pasid = <0x0 0x22>;
|
||||
qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;";
|
||||
qcom,secdomain-ids = <49>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-uri = "vmuid/oemvm";
|
||||
vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0";
|
||||
qcom,sensitive;
|
||||
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
/*
|
||||
* IPA address linux image is loaded at. Must be within
|
||||
* first 1GB due to memory hotplug requirement.
|
||||
*/
|
||||
base-address = <0x0 0x88800000 >;
|
||||
};
|
||||
|
||||
segments {
|
||||
config_cpio = <2>;
|
||||
};
|
||||
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x0 0x0>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
|
||||
interrupts {
|
||||
config = &vgic;
|
||||
};
|
||||
|
||||
vdevices {
|
||||
generate = "/hypervisor";
|
||||
|
||||
minidump {
|
||||
vdevice-type = "minidump";
|
||||
push-compatible = "qcom,minidump_rm";
|
||||
minidump_allowed;
|
||||
};
|
||||
|
||||
rm-rpc {
|
||||
vdevice-type = "rm-rpc";
|
||||
generate = "/hypervisor/qcom,resource-mgr";
|
||||
console-dev;
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
qcom,label = <0x1>;
|
||||
};
|
||||
|
||||
virtio-mmio@0 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x1>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x0>;
|
||||
memory {
|
||||
qcom,label = <0x16>; //for persist.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFEFC000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@1 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x4000>;
|
||||
memory {
|
||||
qcom,label = <0x13>; //for system.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFF00000>;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
push-compatible = "swiotlb";
|
||||
peer-default;
|
||||
dma_base = <0x0 0x8000>;
|
||||
memory {
|
||||
qcom,label = <0x14>;
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xFFF04000>;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x17100000 0x10000>, /* GICD */
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <512>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
};
|
||||
16
qcom/kera-pmiv0102.dtsi
Normal file
16
qcom/kera-pmiv0102.dtsi
Normal file
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-pmiv0108.dtsi"
|
||||
|
||||
&pmiv010x_amoled {
|
||||
status= "ok";
|
||||
};
|
||||
|
||||
&pmiv010x_amoled_ecm {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
|
||||
@@ -65,6 +65,11 @@
|
||||
reg = <0x0 0x81ce4000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
chipinfo_mem: chipinfo_region@81cf4000 {
|
||||
no-map;
|
||||
reg = <0x0 0x81cf4000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
smem_mem: smem_region@81d00000 {
|
||||
compatible = "qcom,smem";
|
||||
reg = <0x0 0x81d00000 0x0 0x200000>;
|
||||
|
||||
@@ -3,6 +3,9 @@
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
@@ -35,6 +38,83 @@
|
||||
};
|
||||
};
|
||||
|
||||
&ufsphy_mem {
|
||||
compatible = "qcom,ufs-phy-qrbtc-sdm845";
|
||||
|
||||
/* VDDA_UFS_CORE */
|
||||
vdda-phy-supply = <&L6B>;
|
||||
vdda-phy-max-microamp = <211860>;
|
||||
/*
|
||||
* Platforms supporting Gear 5 && Rate B require a different
|
||||
* voltage supply. Check the Power Grid document.
|
||||
*/
|
||||
vdda-phy-min-microvolt = <912000>;
|
||||
|
||||
/* VDDA_UFS_0_1P2 */
|
||||
vdda-pll-supply = <&L4B>;
|
||||
vdda-pll-max-microamp = <18330>;
|
||||
|
||||
/* Phy GDSC for VDD_MX, always on */
|
||||
vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>;
|
||||
|
||||
/* Qref power supply, Refer Qref diagram */
|
||||
vdda-qref-supply = <&L2B>;
|
||||
vdda-qref-max-microamp = <1890>;
|
||||
|
||||
/* Detect whether RH132 card based sequences to be used */
|
||||
qcom,soc_emulation_type_addr = <0x1fc8004>;
|
||||
qcom,soc_emulation_type_bits = <32>;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&ufshc_mem {
|
||||
limit-tx-hs-gear = <1>;
|
||||
limit-rx-hs-gear = <1>;
|
||||
limit-rate = <2>; /* HS Rate-B */
|
||||
rpm-level = <0>;
|
||||
spm-level = <0>;
|
||||
|
||||
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
|
||||
|
||||
vcc-supply = <&L12B>;
|
||||
vcc-max-microamp = <800000>;
|
||||
|
||||
vccq-supply = <&L1D>;
|
||||
vccq-max-microamp = <750000>;
|
||||
|
||||
qcom,vddp-ref-clk-supply = <&L3G>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
qcom,vccq-parent-supply = <&S2B>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
||||
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_PAD_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
|
||||
qcom,disable-lpm;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dwc3@a600000 {
|
||||
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
|
||||
@@ -42,3 +122,39 @@
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
};
|
||||
|
||||
&SILVER_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&SILVER_RAIL_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&GOLD_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&GOLD_RAIL_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&GOLD_PLUS_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&GOLD_PLUS_RAIL_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&CLUSTER_PWR_DN {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&CX_RET {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&APSS_OFF {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
15
qcom/kera-vm-rumi.dts
Normal file
15
qcom/kera-vm-rumi.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "kera-vm.dtsi"
|
||||
#include "kera-vm-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kera SVM RUMI";
|
||||
compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi";
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
8
qcom/kera-vm-rumi.dtsi
Normal file
8
qcom/kera-vm-rumi.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&arch_timer {
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
255
qcom/kera-vm.dtsi
Normal file
255
qcom/kera-vm.dtsi
Normal file
@@ -0,0 +1,255 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-kera.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x2>;
|
||||
qcom,msm-id = <659 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
};
|
||||
|
||||
CPU1: cpu@100 {
|
||||
compatible = "arm,armv8";
|
||||
reg = <0x0 0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_PWR_DWN
|
||||
&CLUSTER_PWR_DWN>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
|
||||
compatible = "arm,idle-state";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
boot-config = "fdt,unified";
|
||||
os-type = "linux";
|
||||
kernel-entry-segment = "kernel";
|
||||
kernel-entry-offset = <0x0 0x0>;
|
||||
vendor = "QTI";
|
||||
image-name = "qcom,trustedvm";
|
||||
qcom,pasid = <0x0 0x1c>;
|
||||
qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
|
||||
qcom,secdomain-ids = <45>;
|
||||
qcom,primary-vm-index = <0>;
|
||||
vm-uri = "vmuid/trusted-ui";
|
||||
vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
|
||||
qcom,sensitive;
|
||||
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
|
||||
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
|
||||
* QUP1_SE4: GPII5 : IRQ_316
|
||||
* QUP2_SE7: GPII5 : IRQ_625
|
||||
*/
|
||||
gic-irq-ranges = <316 316
|
||||
625 625 /* PVM->SVM IRQ transfer */
|
||||
279 279>;
|
||||
|
||||
memory {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
/*
|
||||
* IPA address linux image is loaded at. Must be within
|
||||
* first 1GB due to memory hotplug requirement.
|
||||
*/
|
||||
base-address = <0x0 0x88800000 >;
|
||||
};
|
||||
|
||||
segments {
|
||||
config_cpio = <2>;
|
||||
};
|
||||
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x0 0x0>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
|
||||
interrupts {
|
||||
config = &vgic;
|
||||
};
|
||||
|
||||
vdevices {
|
||||
generate = "/hypervisor";
|
||||
|
||||
minidump {
|
||||
vdevice-type = "minidump";
|
||||
push-compatible = "qcom,minidump_rm";
|
||||
minidump_allowed;
|
||||
};
|
||||
|
||||
rm-rpc {
|
||||
vdevice-type = "rm-rpc";
|
||||
generate = "/hypervisor/qcom,resource-mgr";
|
||||
console-dev;
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
qcom,label = <0x1>;
|
||||
};
|
||||
|
||||
virtio-mmio@0 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x1>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x0>;
|
||||
memory {
|
||||
qcom,label = <0x11>; //for persist.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6F8000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@1 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
generate = "/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x2>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x4000>;
|
||||
memory {
|
||||
qcom,label = <0x10>; //for system.img
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA6FC000>;
|
||||
};
|
||||
};
|
||||
|
||||
virtio-mmio@2 {
|
||||
vdevice-type = "virtio-mmio";
|
||||
patch = "/soc/virtio-mmio";
|
||||
peer-default;
|
||||
vqs-num = <0x3>;
|
||||
push-compatible = "virtio,mmio";
|
||||
dma-coherent;
|
||||
dma_base = <0x0 0x8000>;
|
||||
memory {
|
||||
qcom,label = <0x15>; //for virtio-vsock
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA700000>;
|
||||
};
|
||||
};
|
||||
|
||||
swiotlb-shm {
|
||||
vdevice-type = "shm";
|
||||
generate = "/swiotlb";
|
||||
push-compatible = "swiotlb";
|
||||
peer-default;
|
||||
dma_base = <0x0 0x14000>;
|
||||
memory {
|
||||
qcom,label = <0x12>;
|
||||
#address-cells = <0x2>;
|
||||
base = <0x0 0xDA70c000>;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: qcom_scm {
|
||||
compatible = "qcom,scm";
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
gcc: clock-controller@100000 {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "gcc_clocks";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
virtio-mmio {
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17100000 {
|
||||
compatible = "arm,gic-v3";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x3>;
|
||||
#redistributor-regions = <1>;
|
||||
redistributor-stride = <0x0 0x40000>;
|
||||
reg = <0x17100000 0x10000>, /* GICD */
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <64>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
};
|
||||
|
||||
#include "msm-arm-smmu-kera-vm.dtsi"
|
||||
1138
qcom/kera.dtsi
1138
qcom/kera.dtsi
File diff suppressed because it is too large
Load Diff
@@ -84,6 +84,7 @@
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,lmh-dcvs = <&lmh_dcvs0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L1_I_1: l1-icache {
|
||||
compatible = "cache";
|
||||
@@ -109,6 +110,7 @@
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,lmh-dcvs = <&lmh_dcvs0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L1_I_2: l1-icache {
|
||||
compatible = "cache";
|
||||
@@ -134,6 +136,7 @@
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
qcom,lmh-dcvs = <&lmh_dcvs0>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
L1_I_3: l1-icache {
|
||||
compatible = "cache";
|
||||
@@ -1641,24 +1644,11 @@
|
||||
};
|
||||
|
||||
rpm-sleep-stats@4690000 {
|
||||
/* compatible = "qcom,rpm-sleep-stats"; */
|
||||
compatible = "qcom,rpm-stats-v2";
|
||||
reg = <0x04690000 0x400>;
|
||||
ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss";
|
||||
};
|
||||
|
||||
subsystem-sleep-stats@4690000 {
|
||||
/* compatible = "qcom,subsystem-sleep-stats-v2"; */
|
||||
reg = <0x4690000 0x400>;
|
||||
};
|
||||
|
||||
qcom,rpm-master-stats@45f0150 {
|
||||
/* compatible = "qcom,rpm-master-stats"; */
|
||||
reg = <0x45f0150 0x5000>;
|
||||
qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
|
||||
qcom,master-stats-version = <2>;
|
||||
qcom,master-offset = <4096>;
|
||||
};
|
||||
|
||||
sdhc1_opp_table: sdhc1-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
|
||||
62
qcom/msm-arm-smmu-kera-vm.dtsi
Normal file
62
qcom/msm-arm-smmu-kera-vm.dtsi
Normal file
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
vm-config {
|
||||
vdevices {
|
||||
vsmmu@15000000 {
|
||||
vdevice-type = "vsmmu-v2";
|
||||
smmu-handle = <0x15000000>;
|
||||
num-cbs = <0x7>;
|
||||
num-smrs = <0xe>;
|
||||
patch = "/soc/apps-smmu@15000000";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
apps_smmu: apps-smmu@15000000 {
|
||||
/*
|
||||
* reg, #global-interrupts & interrupts properties will
|
||||
* be added dynamically by bootloader.
|
||||
*/
|
||||
compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
|
||||
#iommu-cells = <2>;
|
||||
qcom,use-3-lvl-tables;
|
||||
dma-coherent;
|
||||
|
||||
qcom,actlr =
|
||||
/* CAM_HF:Camera */
|
||||
<0x1c08 0x0000 0x00000001>,
|
||||
|
||||
/* Mnoc_HF_23:Display */
|
||||
<0x0804 0x0002 0x00000001>,
|
||||
|
||||
/* NSP:Compute */
|
||||
<0x0c0b 0x0000 0x00000303>,
|
||||
|
||||
/* SF:Camera IPE*/
|
||||
<0x1808 0x0020 0x00000001>,
|
||||
|
||||
/* SF:Camera CDM IPE/IFE/OFE*/
|
||||
<0x1841 0x0000 0x00000001>,
|
||||
<0x1861 0x0000 0x00000001>,
|
||||
<0x1881 0x0000 0x00000001>,
|
||||
|
||||
/* SF:Camera ICP*/
|
||||
<0x18c2 0x0000 0x00000001>,
|
||||
<0x1982 0x0000 0x00000001>,
|
||||
|
||||
/* SF:Camera CRE*/
|
||||
<0x18e8 0x0000 0x00000103>,
|
||||
|
||||
/* SF:EVA */
|
||||
<0x1901 0x0020 0x00000103>,
|
||||
<0x1925 0x0000 0x00000103>;
|
||||
};
|
||||
};
|
||||
@@ -17,6 +17,13 @@
|
||||
ranges;
|
||||
dma-coherent;
|
||||
|
||||
qcom,regulator-names = "vdd";
|
||||
vdd-supply = <&gpu_cc_cx_gdsc>;
|
||||
|
||||
clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
||||
clock-names =
|
||||
"gpu_cc_hlos1_vote_gpu_smmu";
|
||||
|
||||
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -53,6 +60,7 @@
|
||||
reg = <0x3de8000 0x1000>;
|
||||
qcom,stream-id-range = <0x0 0x400>;
|
||||
qcom,iova-width = <49>;
|
||||
interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
};
|
||||
@@ -230,6 +238,7 @@
|
||||
reg = <0x16f2000 0x1000>;
|
||||
qcom,stream-id-range = <0x0 0x400>;
|
||||
qcom,iova-width = <36>;
|
||||
interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <1>;
|
||||
};
|
||||
|
||||
@@ -238,6 +247,7 @@
|
||||
reg = <0x171b000 0x1000>;
|
||||
qcom,stream-id-range = <0x400 0x400>;
|
||||
qcom,iova-width = <36>;
|
||||
interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <1>;
|
||||
};
|
||||
|
||||
@@ -246,6 +256,7 @@
|
||||
reg = <0x17f7000 0x1000>;
|
||||
qcom,stream-id-range = <0x1c00 0x400>;
|
||||
qcom,iova-width = <32>;
|
||||
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
|
||||
@@ -254,6 +265,7 @@
|
||||
reg = <0x7d3000 0x1000>;
|
||||
qcom,stream-id-range = <0xc00 0x400>;
|
||||
qcom,iova-width = <32>;
|
||||
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
|
||||
@@ -262,6 +274,7 @@
|
||||
reg = <0x7b3000 0x1000>;
|
||||
qcom,stream-id-range = <0x1000 0x400>;
|
||||
qcom,iova-width = <32>;
|
||||
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <1>;
|
||||
};
|
||||
|
||||
@@ -271,6 +284,7 @@
|
||||
qcom,stream-id-range = <0x1400 0x400>;
|
||||
qcom,iova-width = <32>;
|
||||
qcom,num-qtb-ports = <1>;
|
||||
interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
|
||||
qcom,opt-out-tbu-halting;
|
||||
};
|
||||
|
||||
@@ -279,6 +293,7 @@
|
||||
reg = <0x17b7000 0x1000>;
|
||||
qcom,stream-id-range = <0x1800 0x400>;
|
||||
qcom,iova-width = <32>;
|
||||
interconnects = <&mmss_noc MASTER_VIDEO_MVP &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
|
||||
@@ -287,6 +302,7 @@
|
||||
reg = <0x17f6000 0x1000>;
|
||||
qcom,stream-id-range = <0x800 0x400>;
|
||||
qcom,iova-width = <36>;
|
||||
interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>;
|
||||
qcom,num-qtb-ports = <2>;
|
||||
};
|
||||
|
||||
|
||||
62
qcom/msm-arm-smmu-tuna-vm.dtsi
Normal file
62
qcom/msm-arm-smmu-tuna-vm.dtsi
Normal file
@@ -0,0 +1,62 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
vm-config {
|
||||
vdevices {
|
||||
vsmmu@15000000 {
|
||||
vdevice-type = "vsmmu-v2";
|
||||
smmu-handle = <0x15000000>;
|
||||
num-cbs = <0x7>;
|
||||
num-smrs = <0xe>;
|
||||
patch = "/soc/apps-smmu@15000000";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
apps_smmu: apps-smmu@15000000 {
|
||||
/*
|
||||
* reg, #global-interrupts & interrupts properties will
|
||||
* be added dynamically by bootloader.
|
||||
*/
|
||||
compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
|
||||
#iommu-cells = <2>;
|
||||
qcom,use-3-lvl-tables;
|
||||
dma-coherent;
|
||||
|
||||
qcom,actlr =
|
||||
/* CAM_HF:Camera */
|
||||
<0x1c08 0x0000 0x00000001>,
|
||||
|
||||
/* Mnoc_HF_23:Display */
|
||||
<0x0804 0x0002 0x00000001>,
|
||||
|
||||
/* NSP:Compute */
|
||||
<0x0c0b 0x0000 0x00000303>,
|
||||
|
||||
/* SF:Camera IPE*/
|
||||
<0x1808 0x0020 0x00000001>,
|
||||
|
||||
/* SF:Camera CDM IPE/IFE/OFE*/
|
||||
<0x1841 0x0000 0x00000001>,
|
||||
<0x1861 0x0000 0x00000001>,
|
||||
<0x1881 0x0000 0x00000001>,
|
||||
|
||||
/* SF:Camera ICP*/
|
||||
<0x18c2 0x0000 0x00000001>,
|
||||
<0x1982 0x0000 0x00000001>,
|
||||
|
||||
/* SF:Camera CRE*/
|
||||
<0x18e8 0x0000 0x00000103>,
|
||||
|
||||
/* SF:EVA */
|
||||
<0x1901 0x0020 0x00000103>,
|
||||
<0x1925 0x0000 0x00000103>;
|
||||
};
|
||||
};
|
||||
@@ -36,17 +36,11 @@
|
||||
};
|
||||
|
||||
&soc {
|
||||
|
||||
qcom,guestvm_loader@e0b00000 {
|
||||
gh-secure-vm-loader@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qrtr-gunyah {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qcom,virtio_backend@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@@ -1887,4 +1887,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
compatible = "qcom,tlmm-vm-mem-access";
|
||||
qcom,master;
|
||||
tuivm {
|
||||
qcom,label = <0x08>;
|
||||
qcom,vmid = <45>;
|
||||
tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
|
||||
&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -159,6 +159,13 @@
|
||||
|
||||
goodix,touch-type = "primary";
|
||||
goodix,qts_en;
|
||||
qcom,touch-environment = "pvm";
|
||||
qts,trusted-touch-mode = "vm_mode";
|
||||
qts,touch-environment = "pvm";
|
||||
qts,trusted-touch-type = "primary";
|
||||
qts,trusted-touch-spi-irq = <595>;
|
||||
qts,trusted-touch-io-bases = <0xa8c000>;
|
||||
qts,trusted-touch-io-sizes = <0x1000>;
|
||||
qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0
|
||||
&tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -5,3 +5,25 @@
|
||||
|
||||
&soc {
|
||||
};
|
||||
|
||||
&qupv3_se9_spi {
|
||||
status = "ok";
|
||||
goodix-berlin@0 {
|
||||
compatible = "goodix,gt9916S";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
goodix,panel-max-x = <1080>;
|
||||
goodix,panel-max-y = <2400>;
|
||||
goodix,panel-max-w = <255>;
|
||||
goodix,panel-max-p = <4096>;
|
||||
goodix,touch-type = "primary";
|
||||
goodix,qts_en;
|
||||
qts,trusted-touch-mode = "vm_mode";
|
||||
qts,touch-environment = "tvm";
|
||||
qts,trusted-touch-type = "primary";
|
||||
qts,trusted-touch-spi-irq = <595>;
|
||||
qts,trusted-touch-io-bases = <0xa8c000>;
|
||||
qts,trusted-touch-io-sizes = <0x1000>;
|
||||
qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
|
||||
/ {
|
||||
qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
|
||||
<633 0x10000>, <634 0x10000>, <638 0x10000>;
|
||||
<633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>;
|
||||
interrupt-parent = <&vgic>;
|
||||
|
||||
qcom,vm-config {
|
||||
@@ -53,14 +53,14 @@
|
||||
<0x17260000 0x100000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
pinctrl@f000000 {
|
||||
tlmm: pinctrl@f000000 {
|
||||
compatible = "qcom,parrot-vm-tlmm";
|
||||
gpios = /bits/ 16 <>;
|
||||
qcom,gpios-reserved = <0 1 2 3 38>;
|
||||
gpios = /bits/ 16 <98 99 10 11 12 13 64 65>;
|
||||
};
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
tlmm-vm-gpio-list = <>;
|
||||
tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0
|
||||
&tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>;
|
||||
};
|
||||
|
||||
apps-smmu@15000000 {
|
||||
|
||||
@@ -463,6 +463,12 @@
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
dsi_pll_codes {
|
||||
};
|
||||
|
||||
disp_rdump_region@e1000000 {
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
@@ -2066,6 +2072,16 @@
|
||||
virtio-backends = <&trust_ui_vm_virt_be0>;
|
||||
};
|
||||
|
||||
gh-secure-vm-loader@1 {
|
||||
compatible = "qcom,gh-secure-vm-loader";
|
||||
qcom,pas-id = <35>;
|
||||
qcom,vmid = <50>;
|
||||
qcom,firmware-name = "cpusys_vm";
|
||||
memory-region = <&cpusys_vm_mem>;
|
||||
ext-region = <&chipinfo_mem>;
|
||||
ext-label = <0x7>;
|
||||
};
|
||||
|
||||
qrtr-gunyah {
|
||||
compatible = "qcom,qrtr-gunyah";
|
||||
qcom,master;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/soc/qcom,dcc_v2.h>
|
||||
@@ -10,11 +10,8 @@
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
dump_mem: mem_dump_region {
|
||||
compatible = "shared-dma-pool";
|
||||
dump_mem: dump_mem_region {
|
||||
alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0 0x1800000>;
|
||||
};
|
||||
};
|
||||
@@ -4505,414 +4502,418 @@
|
||||
compatible = "qcom,mem-dump";
|
||||
memory-region = <&dump_mem>;
|
||||
|
||||
c0_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x0>;
|
||||
};
|
||||
|
||||
c100_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x1>;
|
||||
};
|
||||
|
||||
c200_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x2>;
|
||||
};
|
||||
|
||||
c300_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x3>;
|
||||
};
|
||||
|
||||
c400_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x4>;
|
||||
};
|
||||
|
||||
c500_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x5>;
|
||||
};
|
||||
|
||||
c600_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x6>;
|
||||
};
|
||||
|
||||
c700_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x7>;
|
||||
};
|
||||
|
||||
l1_icache0 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x60>;
|
||||
};
|
||||
|
||||
l1_icache100 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x61>;
|
||||
};
|
||||
|
||||
l1_icache200 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x62>;
|
||||
};
|
||||
|
||||
l1_icache300 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x63>;
|
||||
};
|
||||
|
||||
l1_icache400 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x64>;
|
||||
};
|
||||
|
||||
l1_icache500 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x65>;
|
||||
};
|
||||
|
||||
l1_icache600 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x66>;
|
||||
};
|
||||
|
||||
l1_icache700 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x67>;
|
||||
};
|
||||
|
||||
l1_dcache0 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x80>;
|
||||
};
|
||||
|
||||
l1_dcache100 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x81>;
|
||||
};
|
||||
|
||||
l1_dcache200 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x82>;
|
||||
};
|
||||
|
||||
l1_dcache300 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x83>;
|
||||
};
|
||||
|
||||
l1_dcache400 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x84>;
|
||||
};
|
||||
|
||||
l1_dcache500 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x85>;
|
||||
};
|
||||
|
||||
l1_dcache600 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x86>;
|
||||
};
|
||||
|
||||
l1_dcache700 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x87>;
|
||||
};
|
||||
|
||||
l1_itlb700 {
|
||||
qcom,dump-size = <0x600>;
|
||||
qcom,dump-id = <0x27>;
|
||||
};
|
||||
|
||||
l1_dtlb700 {
|
||||
qcom,dump-size = <0xa00>;
|
||||
qcom,dump-id = <0x47>;
|
||||
};
|
||||
|
||||
l2_cache0 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc0>;
|
||||
};
|
||||
|
||||
l2_cache100 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc1>;
|
||||
};
|
||||
|
||||
l2_cache200 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc2>;
|
||||
};
|
||||
|
||||
l2_cache300 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc3>;
|
||||
};
|
||||
|
||||
l2_cache400 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc4>;
|
||||
};
|
||||
|
||||
l2_cache500 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc5>;
|
||||
};
|
||||
|
||||
l2_cache600 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc6>;
|
||||
};
|
||||
|
||||
l2_cache700 {
|
||||
qcom,dump-size = <0x340100>;
|
||||
qcom,dump-id = <0xc7>;
|
||||
};
|
||||
|
||||
l2_tlb0 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x120>;
|
||||
};
|
||||
|
||||
l2_tlb100 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x121>;
|
||||
};
|
||||
|
||||
l2_tlb700 {
|
||||
qcom,dump-size = <0xa900>;
|
||||
qcom,dump-id = <0x127>;
|
||||
};
|
||||
|
||||
l1dcdirty0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x170>;
|
||||
};
|
||||
|
||||
l1dcdirty100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x171>;
|
||||
};
|
||||
|
||||
l1dcmte0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x180>;
|
||||
};
|
||||
|
||||
l1dcmte100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x181>;
|
||||
};
|
||||
|
||||
l2dcmte0 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x190>;
|
||||
};
|
||||
|
||||
l2dcmte100 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x191>;
|
||||
};
|
||||
|
||||
l0mopca700 {
|
||||
qcom,dump-size = <0x4100>;
|
||||
qcom,dump-id = <0x1a7>;
|
||||
};
|
||||
|
||||
l2victim700 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x1e7>;
|
||||
};
|
||||
|
||||
l2tldtcsp200 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x202>;
|
||||
};
|
||||
|
||||
l2tldtcsp300 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x203>;
|
||||
};
|
||||
|
||||
l2tldtcsp400 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x204>;
|
||||
};
|
||||
|
||||
l2tldtcsp500 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x205>;
|
||||
};
|
||||
|
||||
l2tldtcsp600 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x206>;
|
||||
};
|
||||
|
||||
l2tldtcmp200 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x212>;
|
||||
};
|
||||
|
||||
l2tldtcmp300 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x213>;
|
||||
};
|
||||
|
||||
l2tldtcmp400 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x214>;
|
||||
};
|
||||
|
||||
l2tldtcmp500 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x215>;
|
||||
};
|
||||
|
||||
l2tldtcmp600 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x216>;
|
||||
};
|
||||
|
||||
cpuss_reg {
|
||||
qcom,dump-size = <0x36000>;
|
||||
qcom,dump-id = <0xef>;
|
||||
};
|
||||
|
||||
rpmh {
|
||||
qcom,dump-size = <0x400000>;
|
||||
qcom,dump-id = <0xec>;
|
||||
};
|
||||
|
||||
rpm_sw {
|
||||
qcom,dump-size = <0x28000>;
|
||||
qcom,dump-id = <0xea>;
|
||||
};
|
||||
|
||||
pmic {
|
||||
qcom,dump-size = <0x200000>;
|
||||
qcom,dump-id = <0xe4>;
|
||||
};
|
||||
|
||||
fcm {
|
||||
qcom,dump-size = <0x8400>;
|
||||
qcom,dump-id = <0xee>;
|
||||
};
|
||||
|
||||
etf_swao {
|
||||
qcom,dump-size = <0x10000>;
|
||||
qcom,dump-id = <0xf1>;
|
||||
};
|
||||
|
||||
etr_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x100>;
|
||||
};
|
||||
|
||||
etfswao_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x102>;
|
||||
};
|
||||
|
||||
etr1_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x105>;
|
||||
};
|
||||
|
||||
misc_data {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0xe8>;
|
||||
};
|
||||
|
||||
etf_slpi {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf3>;
|
||||
};
|
||||
|
||||
etfslpi_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x103>;
|
||||
};
|
||||
|
||||
etf_lpass {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf4>;
|
||||
};
|
||||
|
||||
etflpass_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x104>;
|
||||
};
|
||||
|
||||
osm_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x163>;
|
||||
};
|
||||
|
||||
pcu_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x164>;
|
||||
};
|
||||
|
||||
fsm_data {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x165>;
|
||||
};
|
||||
|
||||
spr_cpu0 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f0>;
|
||||
};
|
||||
|
||||
spr_cpu1 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f1>;
|
||||
};
|
||||
|
||||
spr_cpu2 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f2>;
|
||||
};
|
||||
|
||||
spr_cpu3 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f3>;
|
||||
};
|
||||
|
||||
spr_cpu4 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f4>;
|
||||
};
|
||||
|
||||
spr_cpu5 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f5>;
|
||||
};
|
||||
|
||||
spr_cpu6 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f6>;
|
||||
};
|
||||
|
||||
spr_cpu7 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f7>;
|
||||
};
|
||||
|
||||
scandump_smmu {
|
||||
qcom,dump-size = <0x40000>;
|
||||
qcom,dump-id = <0x220>;
|
||||
};
|
||||
|
||||
scandump_gpu {
|
||||
qcom,dump-size = <0x300000>;
|
||||
qcom,dump-id = <0x221>;
|
||||
static_dump {
|
||||
qcom,static-mem-dump;
|
||||
|
||||
c0_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x0>;
|
||||
};
|
||||
|
||||
c100_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x1>;
|
||||
};
|
||||
|
||||
c200_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x2>;
|
||||
};
|
||||
|
||||
c300_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x3>;
|
||||
};
|
||||
|
||||
c400_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x4>;
|
||||
};
|
||||
|
||||
c500_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x5>;
|
||||
};
|
||||
|
||||
c600_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x6>;
|
||||
};
|
||||
|
||||
c700_context {
|
||||
qcom,dump-size = <0x800>;
|
||||
qcom,dump-id = <0x7>;
|
||||
};
|
||||
|
||||
l1_icache0 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x60>;
|
||||
};
|
||||
|
||||
l1_icache100 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x61>;
|
||||
};
|
||||
|
||||
l1_icache200 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x62>;
|
||||
};
|
||||
|
||||
l1_icache300 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x63>;
|
||||
};
|
||||
|
||||
l1_icache400 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x64>;
|
||||
};
|
||||
|
||||
l1_icache500 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x65>;
|
||||
};
|
||||
|
||||
l1_icache600 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x66>;
|
||||
};
|
||||
|
||||
l1_icache700 {
|
||||
qcom,dump-size = <0x22100>;
|
||||
qcom,dump-id = <0x67>;
|
||||
};
|
||||
|
||||
l1_dcache0 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x80>;
|
||||
};
|
||||
|
||||
l1_dcache100 {
|
||||
qcom,dump-size = <0x12100>;
|
||||
qcom,dump-id = <0x81>;
|
||||
};
|
||||
|
||||
l1_dcache200 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x82>;
|
||||
};
|
||||
|
||||
l1_dcache300 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x83>;
|
||||
};
|
||||
|
||||
l1_dcache400 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x84>;
|
||||
};
|
||||
|
||||
l1_dcache500 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x85>;
|
||||
};
|
||||
|
||||
l1_dcache600 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x86>;
|
||||
};
|
||||
|
||||
l1_dcache700 {
|
||||
qcom,dump-size = <0x1a100>;
|
||||
qcom,dump-id = <0x87>;
|
||||
};
|
||||
|
||||
l1_itlb700 {
|
||||
qcom,dump-size = <0x600>;
|
||||
qcom,dump-id = <0x27>;
|
||||
};
|
||||
|
||||
l1_dtlb700 {
|
||||
qcom,dump-size = <0xa00>;
|
||||
qcom,dump-id = <0x47>;
|
||||
};
|
||||
|
||||
l2_cache0 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc0>;
|
||||
};
|
||||
|
||||
l2_cache100 {
|
||||
qcom,dump-size = <0x90100>;
|
||||
qcom,dump-id = <0xc1>;
|
||||
};
|
||||
|
||||
l2_cache200 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc2>;
|
||||
};
|
||||
|
||||
l2_cache300 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc3>;
|
||||
};
|
||||
|
||||
l2_cache400 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc4>;
|
||||
};
|
||||
|
||||
l2_cache500 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc5>;
|
||||
};
|
||||
|
||||
l2_cache600 {
|
||||
qcom,dump-size = <0xd0100>;
|
||||
qcom,dump-id = <0xc6>;
|
||||
};
|
||||
|
||||
l2_cache700 {
|
||||
qcom,dump-size = <0x340100>;
|
||||
qcom,dump-id = <0xc7>;
|
||||
};
|
||||
|
||||
l2_tlb0 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x120>;
|
||||
};
|
||||
|
||||
l2_tlb100 {
|
||||
qcom,dump-size = <0xf700>;
|
||||
qcom,dump-id = <0x121>;
|
||||
};
|
||||
|
||||
l2_tlb700 {
|
||||
qcom,dump-size = <0xa900>;
|
||||
qcom,dump-id = <0x127>;
|
||||
};
|
||||
|
||||
l1dcdirty0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x170>;
|
||||
};
|
||||
|
||||
l1dcdirty100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x171>;
|
||||
};
|
||||
|
||||
l1dcmte0 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x180>;
|
||||
};
|
||||
|
||||
l1dcmte100 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x181>;
|
||||
};
|
||||
|
||||
l2dcmte0 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x190>;
|
||||
};
|
||||
|
||||
l2dcmte100 {
|
||||
qcom,dump-size = <0x10100>;
|
||||
qcom,dump-id = <0x191>;
|
||||
};
|
||||
|
||||
l0mopca700 {
|
||||
qcom,dump-size = <0x4100>;
|
||||
qcom,dump-id = <0x1a7>;
|
||||
};
|
||||
|
||||
l2victim700 {
|
||||
qcom,dump-size = <0x2100>;
|
||||
qcom,dump-id = <0x1e7>;
|
||||
};
|
||||
|
||||
l2tldtcsp200 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x202>;
|
||||
};
|
||||
|
||||
l2tldtcsp300 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x203>;
|
||||
};
|
||||
|
||||
l2tldtcsp400 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x204>;
|
||||
};
|
||||
|
||||
l2tldtcsp500 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x205>;
|
||||
};
|
||||
|
||||
l2tldtcsp600 {
|
||||
qcom,dump-size = <0x7900>;
|
||||
qcom,dump-id = <0x206>;
|
||||
};
|
||||
|
||||
l2tldtcmp200 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x212>;
|
||||
};
|
||||
|
||||
l2tldtcmp300 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x213>;
|
||||
};
|
||||
|
||||
l2tldtcmp400 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x214>;
|
||||
};
|
||||
|
||||
l2tldtcmp500 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x215>;
|
||||
};
|
||||
|
||||
l2tldtcmp600 {
|
||||
qcom,dump-size = <0x1300>;
|
||||
qcom,dump-id = <0x216>;
|
||||
};
|
||||
|
||||
cpuss_reg {
|
||||
qcom,dump-size = <0x36000>;
|
||||
qcom,dump-id = <0xef>;
|
||||
};
|
||||
|
||||
rpmh {
|
||||
qcom,dump-size = <0x400000>;
|
||||
qcom,dump-id = <0xec>;
|
||||
};
|
||||
|
||||
rpm_sw {
|
||||
qcom,dump-size = <0x28000>;
|
||||
qcom,dump-id = <0xea>;
|
||||
};
|
||||
|
||||
pmic {
|
||||
qcom,dump-size = <0x200000>;
|
||||
qcom,dump-id = <0xe4>;
|
||||
};
|
||||
|
||||
fcm {
|
||||
qcom,dump-size = <0x8400>;
|
||||
qcom,dump-id = <0xee>;
|
||||
};
|
||||
|
||||
etf_swao {
|
||||
qcom,dump-size = <0x10000>;
|
||||
qcom,dump-id = <0xf1>;
|
||||
};
|
||||
|
||||
etr_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x100>;
|
||||
};
|
||||
|
||||
etfswao_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x102>;
|
||||
};
|
||||
|
||||
etr1_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x105>;
|
||||
};
|
||||
|
||||
misc_data {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0xe8>;
|
||||
};
|
||||
|
||||
etf_slpi {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf3>;
|
||||
};
|
||||
|
||||
etfslpi_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x103>;
|
||||
};
|
||||
|
||||
etf_lpass {
|
||||
qcom,dump-size = <0x4000>;
|
||||
qcom,dump-id = <0xf4>;
|
||||
};
|
||||
|
||||
etflpass_reg {
|
||||
qcom,dump-size = <0x1000>;
|
||||
qcom,dump-id = <0x104>;
|
||||
};
|
||||
|
||||
osm_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x163>;
|
||||
};
|
||||
|
||||
pcu_reg {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x164>;
|
||||
};
|
||||
|
||||
fsm_data {
|
||||
qcom,dump-size = <0x400>;
|
||||
qcom,dump-id = <0x165>;
|
||||
};
|
||||
|
||||
spr_cpu0 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f0>;
|
||||
};
|
||||
|
||||
spr_cpu1 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f1>;
|
||||
};
|
||||
|
||||
spr_cpu2 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f2>;
|
||||
};
|
||||
|
||||
spr_cpu3 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f3>;
|
||||
};
|
||||
|
||||
spr_cpu4 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f4>;
|
||||
};
|
||||
|
||||
spr_cpu5 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f5>;
|
||||
};
|
||||
|
||||
spr_cpu6 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f6>;
|
||||
};
|
||||
|
||||
spr_cpu7 {
|
||||
qcom,dump-size = <0x2000>;
|
||||
qcom,dump-id = <0x1f7>;
|
||||
};
|
||||
|
||||
scandump_smmu {
|
||||
qcom,dump-size = <0x40000>;
|
||||
qcom,dump-id = <0x220>;
|
||||
};
|
||||
|
||||
scandump_gpu {
|
||||
qcom,dump-size = <0x300000>;
|
||||
qcom,dump-id = <0x221>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -85,7 +85,9 @@ _platform_map = {
|
||||
},
|
||||
{"name": "tuna-atp-overlay.dtbo"},
|
||||
{"name": "tuna-cdp-overlay.dtbo"},
|
||||
{"name": "tuna-mtp-kiwi-harmonium-overlay.dtbo"},
|
||||
{"name": "tuna-mtp-kiwi-overlay.dtbo"},
|
||||
{"name": "tuna-mtp-nfc-overlay.dtbo"},
|
||||
{"name": "tuna-mtp-overlay.dtbo"},
|
||||
{"name": "tuna-mtp-qmp1000-overlay.dtbo"},
|
||||
{"name": "tuna-qrd-overlay.dtbo"},
|
||||
@@ -142,7 +144,7 @@ _platform_map = {
|
||||
{"name": "sunp-vm-hdk.dtb"},
|
||||
{"name": "sun-vm-rumi.dtb"},
|
||||
],
|
||||
"binary_compatible_with": ["tuna-tuivm"],
|
||||
"binary_compatible_with": ["tuna-tuivm", "kera-tuivm"],
|
||||
},
|
||||
"sun-oemvm": {
|
||||
"dtb_list": [
|
||||
@@ -162,7 +164,7 @@ _platform_map = {
|
||||
{"name": "sunp-vm-hdk.dtb"},
|
||||
{"name": "sun-vm-rumi.dtb"},
|
||||
],
|
||||
"binary_compatible_with": ["tuna-oemvm"],
|
||||
"binary_compatible_with": ["tuna-oemvm", "kera-oemvm"],
|
||||
},
|
||||
"tuna-tuivm": {
|
||||
"dtb_list": [
|
||||
@@ -210,6 +212,20 @@ _platform_map = {
|
||||
{"name": "tuna-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"kera-tuivm": {
|
||||
"dtb_list": [
|
||||
# keep sorted
|
||||
{"name": "kera-oemvm-rumi.dtb"},
|
||||
{"name": "kera-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"kera-oemvm": {
|
||||
"dtb_list": [
|
||||
# keep sorted
|
||||
{"name": "kera-oemvm-rumi.dtb"},
|
||||
{"name": "kera-vm-rumi.dtb"},
|
||||
],
|
||||
},
|
||||
"pineapple": {
|
||||
"dtb_list": [
|
||||
{"name": "pineapple.dtb"},
|
||||
|
||||
@@ -156,7 +156,7 @@
|
||||
pm7550ba_trip1: trip1 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
pm7550ba_trip2: trip2 {
|
||||
@@ -196,7 +196,7 @@
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl0 {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay-passive = <50>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7550ba_bcl 5>;
|
||||
|
||||
@@ -222,7 +222,7 @@
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl1 {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay-passive = <50>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7550ba_bcl 6>;
|
||||
|
||||
@@ -248,7 +248,7 @@
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl2 {
|
||||
polling-delay-passive = <100>;
|
||||
polling-delay-passive = <50>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7550ba_bcl 7>;
|
||||
|
||||
|
||||
@@ -199,7 +199,7 @@
|
||||
reg = <0xb300>;
|
||||
reg-names = "lpg-base";
|
||||
#pwm-cells = <2>;
|
||||
qcom,num-lpg-channels = <5>;
|
||||
qcom,num-lpg-channels = <3>;
|
||||
nvmem-names = "ppg_sdam";
|
||||
nvmem = <&pmi632_sdam7>;
|
||||
qcom,pbs-client = <&pmi632_pbs_client3>;
|
||||
@@ -235,6 +235,7 @@
|
||||
};
|
||||
|
||||
pmi632_rgb: qcom,leds@d000 {
|
||||
compatible = "qcom,tri-led";
|
||||
reg = <0xd000>;
|
||||
red {
|
||||
label = "red";
|
||||
|
||||
@@ -62,7 +62,6 @@
|
||||
|
||||
hap_swr_slave_reg: qcom,hap-swr-slave-reg {
|
||||
regulator-name = "hap-swr-slave-reg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@@ -30,6 +30,11 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
sm1510_present: sm1510_present@5d {
|
||||
reg = <0x5d 0x1>;
|
||||
bits = <5 5>;
|
||||
};
|
||||
|
||||
ocp_log: ocp-log@76 {
|
||||
reg = <0x76 0x6>;
|
||||
};
|
||||
@@ -58,6 +63,10 @@
|
||||
reg = <0x9a 0x1>;
|
||||
};
|
||||
|
||||
fmd_cont_after_pon: fmd-cont-after-pon@9c {
|
||||
reg = <0x9c 0x1>;
|
||||
};
|
||||
|
||||
fmd_chg_pon: fmd-chg-pon@9f {
|
||||
reg = <0x9f 0x1>;
|
||||
};
|
||||
|
||||
@@ -17,8 +17,10 @@
|
||||
#size-cells = <0>;
|
||||
status = "ok";
|
||||
qcom,touch-active = "goodix,gt9916S";
|
||||
qcom,la-vm;
|
||||
|
||||
goodix-berlin@0 {
|
||||
compatible = "goodix,gt9916S";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
@@ -41,7 +43,8 @@
|
||||
pinctrl-0 = <&ts_spi_active>;
|
||||
pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>;
|
||||
pinctrl-2 = <&ts_spi_release>;
|
||||
|
||||
goodix,touch-type = "primary";
|
||||
goodix,qts_en;
|
||||
qcom,touch-environment = "pvm";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -28,15 +28,11 @@
|
||||
};
|
||||
|
||||
&soc {
|
||||
qcom,guestvm_loader@e0b00000 {
|
||||
gh-secure-vm-loader@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qrtr-gunyah {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qcom,virtio_backend@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -459,6 +459,12 @@
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
dsi_pll_codes {
|
||||
};
|
||||
|
||||
disp_rdump_region@e1000000 {
|
||||
};
|
||||
|
||||
intc: interrupt-controller@17200000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
@@ -2473,6 +2479,16 @@
|
||||
virtio-backends = <&trust_ui_vm_virt_be0>;
|
||||
};
|
||||
|
||||
gh-secure-vm-loader@1 {
|
||||
compatible = "qcom,gh-secure-vm-loader";
|
||||
qcom,pas-id = <35>;
|
||||
qcom,vmid = <50>;
|
||||
qcom,firmware-name = "cpusys_vm";
|
||||
memory-region = <&cpusys_vm_mem>;
|
||||
ext-region = <&chipinfo_mem>;
|
||||
ext-label = <0x7>;
|
||||
};
|
||||
|
||||
vendor_hooks: qcom,cpu-vendor-hooks {
|
||||
compatible = "qcom,cpu-vendor-hooks";
|
||||
};
|
||||
|
||||
@@ -1325,7 +1325,7 @@
|
||||
qcom,msm-imem@14680000 {
|
||||
compatible = "qcom,msm-imem";
|
||||
reg = <0x0 0x14680000 0x0 0x1000>;
|
||||
ranges = <0x0 0x0 0x14680000 0x0 0x1000>;
|
||||
ranges = <0x0 0x0 0x0 0x14680000 0x0 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
@@ -1368,6 +1368,11 @@
|
||||
compatible = "qcom,msm-imem-diag-dload";
|
||||
reg = <0x0 0xc8 0x0 0xc8>;
|
||||
};
|
||||
|
||||
modem_dsm@c98 {
|
||||
compatible = "qcom,msm-imem-mss-dsm";
|
||||
reg = <0x0 0xc98 0x0 0x10>;
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@1f40000 {
|
||||
@@ -2125,3 +2130,19 @@
|
||||
|
||||
#include "sdxkova-usb.dtsi"
|
||||
#include "ipcc-test-sdxkova.dtsi"
|
||||
|
||||
&CPU0 {
|
||||
/delete-property/ clocks;
|
||||
};
|
||||
|
||||
&CPU1 {
|
||||
/delete-property/ clocks;
|
||||
};
|
||||
|
||||
&CPU2 {
|
||||
/delete-property/ clocks;
|
||||
};
|
||||
|
||||
&CPU3 {
|
||||
/delete-property/ clocks;
|
||||
};
|
||||
|
||||
@@ -35,7 +35,7 @@
|
||||
|
||||
|
||||
chosen: chosen {
|
||||
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops";
|
||||
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops slub_debug=-";
|
||||
stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
|
||||
};
|
||||
|
||||
@@ -3651,6 +3651,9 @@
|
||||
<&cnoc_main MASTER_CNOC_CFG &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "rproc_ddr", "rproc_cnoc";
|
||||
|
||||
rproc-ddr-set-icc-low-svs;
|
||||
rproc-ddr-lowsvs-icc-bw = <1200>;
|
||||
|
||||
memory-region = <&soccp_mem 0>;
|
||||
soccp-tcsr = <&tcsr 0x1a000>;
|
||||
soccp-spare = <0xda0024>;
|
||||
|
||||
@@ -4,7 +4,6 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
#address-cells = <1>;
|
||||
@@ -102,9 +101,6 @@
|
||||
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,uses_level_shifter;
|
||||
|
||||
status = "ok";
|
||||
|
||||
@@ -10,6 +10,13 @@
|
||||
compatible = "qcom,dma-heaps";
|
||||
depends-on-supply = <&qcom_scm>;
|
||||
|
||||
qcom,display {
|
||||
qcom,dma-heap-name = "qcom,display";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
qcom,max-align = <9>;
|
||||
memory-region = <&non_secure_display_memory>;
|
||||
};
|
||||
|
||||
qcom,secure_cdsp {
|
||||
qcom,dma-heap-name = "qcom,cma-secure-cdsp";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
|
||||
18
qcom/tuna-mtp-kiwi-harmonium-overlay.dts
Normal file
18
qcom/tuna-mtp-kiwi-harmonium-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-mtp-kiwi-harmonium.dtsi"
|
||||
#include "tuna-pm7550ba.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>;
|
||||
qcom,board-id = <8 3>;
|
||||
};
|
||||
6
qcom/tuna-mtp-kiwi-harmonium.dtsi
Normal file
6
qcom/tuna-mtp-kiwi-harmonium.dtsi
Normal file
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-mtp-kiwi.dtsi"
|
||||
18
qcom/tuna-mtp-nfc-overlay.dts
Normal file
18
qcom/tuna-mtp-nfc-overlay.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "tuna-mtp-nfc.dtsi"
|
||||
#include "tuna-pm7550ba-pmd802x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna MTP + SN220/SN300 NFC";
|
||||
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <681 0x10000>, <655 0x10000>;
|
||||
qcom,board-id = <8 4>;
|
||||
};
|
||||
6
qcom/tuna-mtp-nfc.dtsi
Normal file
6
qcom/tuna-mtp-nfc.dtsi
Normal file
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "tuna-mtp.dtsi"
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include "tuna-thermal-overlay.dtsi"
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
#address-cells = <1>;
|
||||
@@ -102,9 +103,6 @@
|
||||
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,uses_level_shifter;
|
||||
|
||||
status = "ok";
|
||||
|
||||
@@ -87,7 +87,7 @@
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x5 0x6>;
|
||||
affinity-map = <0x0 0x0>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
@@ -157,12 +157,63 @@
|
||||
};
|
||||
};
|
||||
|
||||
qrtr-shm {
|
||||
vdevice-type = "shm-doorbell";
|
||||
generate = "/hypervisor/qrtr-shm";
|
||||
push-compatible = "qcom,qrtr-gunyah-gen";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x8>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
vrtc {
|
||||
vdevice-type = "vrtc-pl031";
|
||||
peer-default;
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
mem-buf-message-queue-pair {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/membuf-msgq-pair";
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
peer-default;
|
||||
qcom,label = <0x000000C>;
|
||||
};
|
||||
|
||||
test-dbl-oemvm {
|
||||
vdevice-type = "doorbell";
|
||||
generate = "/hypervisor/test-dbl-oemvm";
|
||||
qcom,label = <0x5>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-dbl-oemvm-source {
|
||||
vdevice-type = "doorbell-source";
|
||||
generate = "/hypervisor/test-dbl-oemvm-source";
|
||||
qcom,label = <0x5>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-msgq-oemvm {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/test-msgq-oemvm-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0x5>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-large-dmabuf-oemvm {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/test-large-dmabuf-oemvm-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0xe>;
|
||||
peer-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -206,10 +257,66 @@
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
qcom,mem-buf {
|
||||
compatible = "qcom,mem-buf";
|
||||
qcom,mem-buf-capabilities = "consumer";
|
||||
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
||||
qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */
|
||||
qcom,vmid = <49>;
|
||||
};
|
||||
|
||||
qcom,mem-buf-msgq {
|
||||
compatible = "qcom,mem-buf-msgq";
|
||||
qcom,msgq-names = "oem_vm";
|
||||
};
|
||||
|
||||
virtio_mem_device {
|
||||
compatible = "qcom,virtio-mem";
|
||||
/* Must be memory_block_size_bytes() aligned */
|
||||
qcom,max-size = <0x0 0x10000000>;
|
||||
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
||||
qcom,block-size = <0x400000>;
|
||||
};
|
||||
|
||||
qcom,test-dbl-oemvm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x5>;
|
||||
};
|
||||
|
||||
qcom,test-msgq-oemvm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <0x5>;
|
||||
affinity = <0>;
|
||||
};
|
||||
|
||||
qcom,test-large-dmabuf-oemvm {
|
||||
compatible = "qcom,gh-large-dmabuf-test";
|
||||
gunyah-label = <0xe>;
|
||||
};
|
||||
|
||||
qcom,gh-qtimer@1742b000 {
|
||||
compatible = "qcom,gh-qtmr";
|
||||
reg = <0x1742b000 0x1000>;
|
||||
reg-names = "qtmr-base";
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qcom,qtmr-intr";
|
||||
qcom,secondary;
|
||||
};
|
||||
|
||||
qcom_smcinvoke {
|
||||
compatible = "qcom,smcinvoke";
|
||||
};
|
||||
|
||||
qcom,qrtr {
|
||||
compatible = "qcom,qrtr";
|
||||
qcom,node-id = <21>;
|
||||
};
|
||||
|
||||
qrtr-gunyah {
|
||||
compatible = "qcom,qrtr-gunyah";
|
||||
gunyah-label = <8>;
|
||||
};
|
||||
|
||||
qtee_shmbridge {
|
||||
compatible = "qcom,tee-shared-memory-bridge";
|
||||
qcom,custom-bridge-size = <512>;
|
||||
|
||||
@@ -94,6 +94,7 @@
|
||||
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
|
||||
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
|
||||
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
|
||||
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
|
||||
<&pcie_0_pipe_clk>;
|
||||
@@ -104,13 +105,13 @@
|
||||
"pcie_rate_change_clk",
|
||||
"gcc_ddrss_pcie_sf_qtb_clk",
|
||||
"pcie_aggre_noc_axi_clk",
|
||||
"gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk",
|
||||
"pcie_pipe_clk_mux",
|
||||
"gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
|
||||
"pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
|
||||
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>;
|
||||
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
||||
<0>, <0>, <0>, <1>, <0>, <0>, <0>;
|
||||
<0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_PHY_BCR>;
|
||||
|
||||
@@ -224,3 +224,38 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pm7550ba_bcl {
|
||||
nvmem-cells = <&sm1510_present>;
|
||||
nvmem-cell-names = "sm1510_present";
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
pm7550ba-2s-ibat-lvl0 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7550ba_bcl 8>;
|
||||
|
||||
trips {
|
||||
ibat_2s_lvl0: ibat-2s-lvl0 {
|
||||
temperature = <5000>;
|
||||
hysteresis = <200>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pm7550ba-2s-ibat-lvl1 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pm7550ba_bcl 9>;
|
||||
|
||||
trips {
|
||||
ibat_2s_lvl1: ibat-2s-lvl1 {
|
||||
temperature = <7000>;
|
||||
hysteresis = <200>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -113,11 +113,18 @@
|
||||
nvmem-cells = <&restart_reason>;
|
||||
nvmem-cell-names = "restart_reason";
|
||||
};
|
||||
|
||||
pmic-pon-log {
|
||||
compatible = "qcom,pmic-pon-log";
|
||||
nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>;
|
||||
nvmem-names = "pon_log0", "pon_log1";
|
||||
depends-on-supply = <&gh_watchdog>;
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
sys-therm-0 {
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay-passive = <5000>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>;
|
||||
trips {
|
||||
@@ -132,6 +139,48 @@
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip_config0: trip-config0 {
|
||||
temperature = <78000>;
|
||||
hysteresis = <8000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
trip_config1: trip-config1 {
|
||||
temperature = <80000>;
|
||||
hysteresis = <10000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
display_test_config1: display-test-config1 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
display_test_config2: display-test-config2 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
display_test_config3: display-test-config3 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
display_test_config4: display-test-config4 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
display_test_config5: display-test-config5 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <1000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -3,7 +3,8 @@
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "tuna-thermal-overlay.dtsi"
|
||||
|
||||
&qupv3_se4_spi {
|
||||
#address-cells = <1>;
|
||||
@@ -89,6 +90,14 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&wcd_usbss {
|
||||
interrupt-parent = <&spmi_bus>;
|
||||
interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>;
|
||||
interrupt-names = "usb_wcd";
|
||||
nvmem-cells = <&usb_mode>;
|
||||
nvmem-cell-names = "usb_mode";
|
||||
};
|
||||
|
||||
&sdhc_2 {
|
||||
vdd-supply = <&L13B>;
|
||||
qcom,vdd-voltage-level = <2960000 2960000>;
|
||||
@@ -104,9 +113,6 @@
|
||||
|
||||
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,uses_level_shifter;
|
||||
|
||||
status = "ok";
|
||||
|
||||
@@ -47,7 +47,8 @@
|
||||
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x1f>;
|
||||
qcom,static-gpii-mask = <0x1>;
|
||||
qcom,gpii-mask = <0x1e>;
|
||||
qcom,ev-factor = <1>;
|
||||
memory-region = <&qup1_gpi_iommu_region>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
@@ -255,8 +256,8 @@
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0>,
|
||||
<&gpi_dma1 1 4 3 64 0>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 2>,
|
||||
<&gpi_dma1 1 4 3 64 2>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -279,8 +280,8 @@
|
||||
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
|
||||
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 0>,
|
||||
<&gpi_dma1 1 4 1 64 0>;
|
||||
dmas = <&gpi_dma1 0 4 1 64 2>,
|
||||
<&gpi_dma1 1 4 1 64 2>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
@@ -419,7 +420,8 @@
|
||||
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x1f>;
|
||||
qcom,static-gpii-mask = <0x1>;
|
||||
qcom,gpii-mask = <0x1e>;
|
||||
qcom,ev-factor = <1>;
|
||||
memory-region = <&qup2_gpi_iommu_region>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
@@ -749,8 +751,8 @@
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se15_i2c_sleep>;
|
||||
dmas = <&gpi_dma2 0 7 3 64 0>,
|
||||
<&gpi_dma2 1 7 3 64 0>;
|
||||
dmas = <&gpi_dma2 0 7 3 64 2>,
|
||||
<&gpi_dma2 1 7 3 64 2>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -773,8 +775,8 @@
|
||||
pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
|
||||
<&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se15_spi_sleep>;
|
||||
dmas = <&gpi_dma2 0 7 1 64 0>,
|
||||
<&gpi_dma2 1 7 1 64 0>;
|
||||
dmas = <&gpi_dma2 0 7 1 64 2>,
|
||||
<&gpi_dma2 1 7 1 64 2>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
|
||||
@@ -483,6 +483,25 @@
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-bobb1 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "bobb1";
|
||||
qcom,regulator-type = "pmic5-bob";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_PASS
|
||||
RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 1000000 2000000>;
|
||||
BOB:
|
||||
pmxr2230_bob: regulator-pmxr2230-bob1 {
|
||||
regulator-name = "pmxr2230_bob";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
qcom,init-voltage = <3296000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-msslvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "mss.lvl";
|
||||
|
||||
@@ -127,6 +127,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cam_crm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&disp_crm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie_crm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&qupv3_se7_2uart {
|
||||
qcom,rumi_platform;
|
||||
};
|
||||
@@ -196,3 +208,27 @@
|
||||
clock-output-names = "rpmh_clocks";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
&disp_cc_mdss_core_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp_cc_mdss_core_int2_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0c_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gpu_cc_cx_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gx_clkctl_gx_gdsc {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
252
qcom/tuna-thermal-overlay.dtsi
Normal file
252
qcom/tuna-thermal-overlay.dtsi
Normal file
@@ -0,0 +1,252 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal_qti.h>
|
||||
|
||||
&thermal_zones {
|
||||
socd {
|
||||
cooling-maps {
|
||||
socd_apc1 {
|
||||
trip = <&socd_trip>;
|
||||
cooling-device = <&APC1_MX_CX_PAUSE 1 1>;
|
||||
};
|
||||
|
||||
socd_cdsp1 {
|
||||
trip = <&socd_trip>;
|
||||
cooling-device = <&cdsp_sw 4 4>;
|
||||
};
|
||||
|
||||
socd_gpu0 {
|
||||
trip = <&socd_trip>;
|
||||
cooling-device = <&msm_gpu 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmih010x-bcl-lvl0 {
|
||||
cooling-maps {
|
||||
lbat_modem0 {
|
||||
trip = <&b_bcl_lvl0>;
|
||||
cooling-device = <&modem_bcl 1 1>;
|
||||
};
|
||||
|
||||
lbat_gpu0 {
|
||||
trip = <&b_bcl_lvl0>;
|
||||
cooling-device = <&msm_gpu 1 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmih010x-bcl-lvl1 {
|
||||
cooling-maps {
|
||||
lbat_modem1 {
|
||||
trip = <&b_bcl_lvl1>;
|
||||
cooling-device = <&modem_bcl 2 2>;
|
||||
};
|
||||
|
||||
lbat_gpu1 {
|
||||
trip = <&b_bcl_lvl1>;
|
||||
cooling-device = <&msm_gpu 2 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmih010x-bcl-lvl2 {
|
||||
cooling-maps {
|
||||
lbat_gpu2 {
|
||||
trip = <&b_bcl_lvl2>;
|
||||
cooling-device = <&msm_gpu 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl0 {
|
||||
cooling-maps {
|
||||
vph_0_nr_scg {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_nr_scg_dsc 3 3>;
|
||||
};
|
||||
|
||||
vph_0_nr {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_nr_dsc 6 6>;
|
||||
};
|
||||
|
||||
vph_0_mdm_lte {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_lte_dsc 8 8>;
|
||||
};
|
||||
|
||||
vph_gpu0 {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&msm_gpu 2 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl1 {
|
||||
cooling-maps {
|
||||
vph_1_nr_scg {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_nr_scg_dsc 10 10>;
|
||||
};
|
||||
|
||||
vph_1_nr {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_nr_dsc 9 9>;
|
||||
};
|
||||
|
||||
vph_1_mdm_lte {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_lte_dsc 10 10>;
|
||||
};
|
||||
|
||||
vph_gpu1 {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&msm_gpu 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pm7550ba-bcl-lvl2 {
|
||||
cooling-maps {
|
||||
vph_gpu2 {
|
||||
trip = <&bcl_lvl2>;
|
||||
cooling-device = <&msm_gpu 7 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmxr2230-bcl-lvl0 {
|
||||
cooling-maps {
|
||||
lbat_0_nr_scg {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_nr_scg_dsc 3 3>;
|
||||
};
|
||||
|
||||
lbat_0_nr {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_nr_dsc 6 6>;
|
||||
};
|
||||
|
||||
lbat_0_mdm_lte {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&modem_lte_dsc 8 8>;
|
||||
};
|
||||
|
||||
lbat_gpu0 {
|
||||
trip = <&bcl_lvl0>;
|
||||
cooling-device = <&msm_gpu 2 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmxr2230-bcl-lvl1 {
|
||||
cooling-maps {
|
||||
lbat_1_nr_scg {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_nr_scg_dsc 10 10>;
|
||||
};
|
||||
|
||||
lbat_1_nr {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_nr_dsc 9 9>;
|
||||
};
|
||||
|
||||
lbat_1_mdm_lte {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&modem_lte_dsc 10 10>;
|
||||
};
|
||||
|
||||
lbat_gpu1 {
|
||||
trip = <&bcl_lvl1>;
|
||||
cooling-device = <&msm_gpu 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmxr2230-bcl-lvl2 {
|
||||
cooling-maps {
|
||||
lbat_gpu2 {
|
||||
trip = <&bcl_lvl2>;
|
||||
cooling-device = <&msm_gpu 7 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sys-therm-0 {
|
||||
cooling-maps {
|
||||
apc1_cdev {
|
||||
trip = <&trip_config0>;
|
||||
cooling-device = <&APC1_MX_CX_PAUSE 1 1>;
|
||||
};
|
||||
|
||||
apc0_cdev {
|
||||
trip = <&trip_config0>;
|
||||
cooling-device = <&APC0_MX_CX_PAUSE 1 1>;
|
||||
};
|
||||
|
||||
cdsp_cdev {
|
||||
trip = <&trip_config0>;
|
||||
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
|
||||
gpu_cdev {
|
||||
trip = <&trip_config0>;
|
||||
cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
|
||||
cpu3_hot_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&cpu3_hotplug 1 1>;
|
||||
};
|
||||
|
||||
cpu4_hot_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&cpu4_hotplug 1 1>;
|
||||
};
|
||||
|
||||
cpu5_hot_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&cpu5_hotplug 1 1>;
|
||||
};
|
||||
|
||||
cpu6_hot_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&cpu6_hotplug 1 1>;
|
||||
};
|
||||
|
||||
cpu7_hot_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&cpu7_hotplug 1 1>;
|
||||
};
|
||||
|
||||
lte_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&modem_lte_dsc 255 255>;
|
||||
};
|
||||
|
||||
nr_cdev {
|
||||
trip = <&trip_config1>;
|
||||
cooling-device = <&modem_nr_scg_dsc 255 255>;
|
||||
};
|
||||
|
||||
display_cdev1 {
|
||||
trip = <&display_test_config1>;
|
||||
cooling-device = <&display_fps 1 1>;
|
||||
};
|
||||
|
||||
display_cdev2 {
|
||||
trip = <&display_test_config2>;
|
||||
cooling-device = <&display_fps 2 2>;
|
||||
};
|
||||
|
||||
display_cdev3 {
|
||||
trip = <&display_test_config3>;
|
||||
cooling-device = <&display_fps 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -5,6 +5,10 @@
|
||||
|
||||
#include <dt-bindings/thermal/thermal_qti.h>
|
||||
|
||||
&msm_gpu {
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
tsens0: tsens0@c228000 {
|
||||
compatible = "qcom,tsens-v2";
|
||||
@@ -207,6 +211,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
qcom,devfreq-cdev {
|
||||
compatible = "qcom,devfreq-cdev";
|
||||
qcom,devfreq = <&msm_gpu>;
|
||||
};
|
||||
|
||||
qcom,cpufreq-cdev {
|
||||
compatible = "qcom,cpufreq-cdev";
|
||||
|
||||
@@ -236,16 +245,6 @@
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cdsp_sw_hvx: cdsp_sw_hvx {
|
||||
qcom,qmi-dev-name = "cdsp_sw_hvx";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cdsp_sw_hmx: cdsp_sw_hmx {
|
||||
qcom,qmi-dev-name = "cdsp_sw_hmx";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cdsp_hw: cdsp_hw {
|
||||
qcom,qmi-dev-name = "cdsp_hw";
|
||||
#cooling-cells = <2>;
|
||||
@@ -1241,6 +1240,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu0_cdev {
|
||||
trip = <&gpu0_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-1 {
|
||||
@@ -1273,6 +1279,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu1_cdev {
|
||||
trip = <&gpu1_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-2 {
|
||||
@@ -1305,6 +1318,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu2_cdev {
|
||||
trip = <&gpu2_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-3 {
|
||||
@@ -1337,6 +1357,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu3_cdev {
|
||||
trip = <&gpu3_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-4 {
|
||||
@@ -1369,6 +1396,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu4_cdev {
|
||||
trip = <&gpu4_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu-5 {
|
||||
@@ -1401,6 +1435,13 @@
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
gpu5_cdev {
|
||||
trip = <&gpu5_tj_cfg>;
|
||||
cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nsphvx-0 {
|
||||
|
||||
@@ -9,11 +9,13 @@
|
||||
&soc {
|
||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa600000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
reg = <0xa600000 0x100000>,
|
||||
<0x1fc6000 0x4>;
|
||||
reg-names = "core_base",
|
||||
"tcsr_dyn_en_dis";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
|
||||
@@ -28,23 +30,45 @@
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event_irq";
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 14 IRQ_TYPE_EDGE_RISING>,
|
||||
<&pdc 15 IRQ_TYPE_EDGE_RISING>,
|
||||
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq", "ss_phy_irq";
|
||||
|
||||
qcom,use-pdc-interrupts;
|
||||
qcom,use-eusb2-phy;
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,core-clk-rate-disconnected = <133333333>;
|
||||
|
||||
dwc3@a600000 {
|
||||
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
|
||||
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
|
||||
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
|
||||
|
||||
qcom,num-gsi-evt-buffs = <0x3>;
|
||||
qcom,gsi-reg-offset =
|
||||
<0x0fc /* GSI_GENERAL_CFG */
|
||||
0x110 /* GSI_DBL_ADDR_L */
|
||||
0x120 /* GSI_DBL_ADDR_H */
|
||||
0x130 /* GSI_RING_BASE_ADDR_L */
|
||||
0x144 /* GSI_RING_BASE_ADDR_H */
|
||||
0x1a4>; /* GSI_IF_STS */
|
||||
|
||||
dwc3_0: dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa600000 0xd93c>;
|
||||
reg = <0x0 0xa600000 0x0 0xd93c>;
|
||||
|
||||
iommus = <&apps_smmu 0x40 0x0>;
|
||||
qcom,iommu-dma = "atomic";
|
||||
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
||||
memory-region = <&dwc3_mem_region>;
|
||||
dma-coherent;
|
||||
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&eusb2_phy0>, <&usb_nop_phy>;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
@@ -59,4 +83,258 @@
|
||||
usb-role-switch;
|
||||
};
|
||||
};
|
||||
|
||||
dwc3_mem_region: dwc3_mem_region {
|
||||
iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>,
|
||||
<&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>;
|
||||
};
|
||||
|
||||
/* USB port related High Speed PHY */
|
||||
eusb2_phy0: hsphy@88e3000 {
|
||||
compatible = "qcom,usb-snps-eusb2-phy";
|
||||
reg = <0x88e3000 0x154>,
|
||||
<0x088e2000 0x4>,
|
||||
<0x0c278000 0x4>;
|
||||
reg-names = "eusb2_phy_base",
|
||||
"eud_enable_reg",
|
||||
"eud_detect_reg";
|
||||
|
||||
vdd-supply = <&L3B>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
vdda12-supply = <&L4B>;
|
||||
vdd_refgen-supply = <&L2B>;
|
||||
|
||||
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
|
||||
<&tcsrcc TCSR_USB2_CLKREF_EN>;
|
||||
clock-names = "ref_clk_src", "ref_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* USB port related QMP USB DP Combo PHY */
|
||||
usb_qmp_dp_phy: ssphy@88e8000 {
|
||||
compatible = "qcom,usb-ssphy-qmp-dp-combo";
|
||||
reg = <0x88e8000 0x3000>;
|
||||
reg-names = "qmp_phy_base";
|
||||
|
||||
vdd-supply = <&L3B>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
qcom,vdd-max-load-uA = <47000>;
|
||||
core-supply = <&L4B>;
|
||||
vdd_refgen-supply = <&L2B>;
|
||||
|
||||
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
|
||||
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
|
||||
<&rpmhcc RPMH_CXO_PAD_CLK>,
|
||||
<&tcsrcc TCSR_USB3_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
|
||||
"pipe_clk_ext_src", "ref_clk_src",
|
||||
"ref_clk", "com_aux_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
|
||||
<&gcc GCC_USB3_PHY_PRIM_BCR>;
|
||||
reset-names = "global_phy_reset", "phy_reset";
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<USB3_DP_PCS_PCS_STATUS1
|
||||
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||||
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||||
USB3_DP_PCS_POWER_DOWN_CONTROL
|
||||
USB3_DP_PCS_SW_RESET
|
||||
USB3_DP_PCS_START_CONTROL
|
||||
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
|
||||
USB3_DP_COM_POWER_DOWN_CTRL
|
||||
USB3_DP_COM_SW_RESET
|
||||
USB3_DP_COM_RESET_OVRD_CTRL
|
||||
USB3_DP_COM_PHY_MODE_CTRL
|
||||
USB3_DP_COM_TYPEC_CTRL
|
||||
USB3_DP_PCS_AON_CLAMP_ENABLE>;
|
||||
|
||||
qcom,qmp-phy-init-seq =
|
||||
/* <reg_offset, value> based on tsmcn3e_USB3_Gen2_Seq v1.6 */
|
||||
|
||||
<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
|
||||
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
|
||||
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
|
||||
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
|
||||
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
|
||||
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
|
||||
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
|
||||
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
|
||||
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
|
||||
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
|
||||
USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
|
||||
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
|
||||
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
|
||||
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
|
||||
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
|
||||
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
|
||||
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
|
||||
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
|
||||
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
|
||||
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
|
||||
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
|
||||
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
|
||||
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
|
||||
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
|
||||
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
|
||||
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
|
||||
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
|
||||
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
|
||||
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
|
||||
USB3_DP_QSERDES_COM_BG_TIMER 0x0A
|
||||
USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
|
||||
USB3_DP_QSERDES_COM_SSC_PER1 0x62
|
||||
USB3_DP_QSERDES_COM_SSC_PER2 0x02
|
||||
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
|
||||
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
|
||||
USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
|
||||
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
|
||||
USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
|
||||
USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
|
||||
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
|
||||
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4B
|
||||
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x37
|
||||
USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
|
||||
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
|
||||
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
|
||||
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
|
||||
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
|
||||
USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
|
||||
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
|
||||
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x3F
|
||||
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
|
||||
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
|
||||
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
|
||||
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
|
||||
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
|
||||
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
|
||||
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
|
||||
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
|
||||
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
|
||||
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
|
||||
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
|
||||
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
|
||||
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
|
||||
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
|
||||
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
|
||||
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
|
||||
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
|
||||
USB3_DP_QSERDES_RXA_GM_CAL 0x13
|
||||
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
|
||||
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
|
||||
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
|
||||
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
|
||||
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
|
||||
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
||||
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
|
||||
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3F
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xFF
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0xDF
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xED
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x5C
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x9C
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1D
|
||||
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x09
|
||||
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
|
||||
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||||
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
|
||||
USB3_DP_QSERDES_RXA_VTH_CODE 0x10
|
||||
USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
|
||||
USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
|
||||
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
|
||||
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
|
||||
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
|
||||
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
|
||||
USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
|
||||
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
|
||||
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x3F
|
||||
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
|
||||
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
|
||||
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
|
||||
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
|
||||
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
|
||||
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
|
||||
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
|
||||
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
|
||||
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
|
||||
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
|
||||
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
|
||||
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
|
||||
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
|
||||
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
|
||||
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
|
||||
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
|
||||
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
|
||||
USB3_DP_QSERDES_RXB_GM_CAL 0x13
|
||||
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
|
||||
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
|
||||
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
|
||||
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
|
||||
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
|
||||
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
||||
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
|
||||
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBF
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0xDF
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xFD
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x5C
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x9C
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1D
|
||||
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x09
|
||||
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
|
||||
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
|
||||
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
|
||||
USB3_DP_QSERDES_RXB_VTH_CODE 0x10
|
||||
USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
|
||||
USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
|
||||
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
|
||||
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
|
||||
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
|
||||
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
|
||||
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
|
||||
USB3_DP_PCS_RX_SIGDET_LVL 0x99
|
||||
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
|
||||
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
||||
USB3_DP_PCS_CDR_RESET_TIME 0x0A
|
||||
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
|
||||
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
|
||||
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
|
||||
USB3_DP_PCS_EQ_CONFIG1 0x4B
|
||||
USB3_DP_PCS_EQ_CONFIG5 0x10
|
||||
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
|
||||
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
|
||||
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
|
||||
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
|
||||
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
|
||||
};
|
||||
|
||||
usb_audio_qmi_dev {
|
||||
compatible = "qcom,usb-audio-qmi-dev";
|
||||
iommus = <&apps_smmu 0x100b 0x0>;
|
||||
qcom,iommu-dma = "disabled";
|
||||
qcom,usb-audio-stream-id = <0xb>;
|
||||
qcom,usb-audio-intr-num = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@@ -9,6 +9,18 @@
|
||||
compatible = "qcom,dma-heaps";
|
||||
depends-on-supply = <&qcom_scm>;
|
||||
|
||||
qcom,tui {
|
||||
qcom,dma-heap-name = "qcom,tui";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
|
||||
qcom,tui_demura {
|
||||
qcom,dma-heap-name = "qcom,tui_demura";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
|
||||
qcom,dynamic-heap;
|
||||
};
|
||||
|
||||
qcom,ms1 {
|
||||
qcom,dma-heap-name = "qcom,ms1";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_TVM_CARVEOUT>;
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-tuna.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <0x2>;
|
||||
@@ -52,6 +53,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
dmesg-dump {
|
||||
compatible = "qcom,dmesg-dump";
|
||||
gunyah-label = <7>;
|
||||
ddump-pubkey-size = <270>;
|
||||
ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2
|
||||
0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96
|
||||
0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc
|
||||
0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7
|
||||
0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e
|
||||
0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d
|
||||
0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b
|
||||
0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0
|
||||
0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27
|
||||
0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31
|
||||
0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79
|
||||
0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd
|
||||
0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0
|
||||
0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf
|
||||
0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac
|
||||
0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50
|
||||
0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>;
|
||||
};
|
||||
|
||||
qcom,vm-config {
|
||||
compatible = "qcom,vm-1.0";
|
||||
vm-type = "aarch64-guest";
|
||||
@@ -71,6 +95,10 @@
|
||||
|
||||
vm-attrs = "context-dump", "crash-restart";
|
||||
|
||||
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
|
||||
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0
|
||||
0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>;
|
||||
|
||||
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
|
||||
* QUP1_SE4: GPII5 : IRQ_316
|
||||
* QUP2_SE7: GPII5 : IRQ_625
|
||||
@@ -96,7 +124,7 @@
|
||||
vcpus {
|
||||
config = "/cpus";
|
||||
affinity = "proxy";
|
||||
affinity-map = <0x5 0x6>;
|
||||
affinity-map = <0x0 0x0>;
|
||||
sched-priority = <0>; /* relative to PVM */
|
||||
sched-timeslice = <2000>; /* in ms */
|
||||
};
|
||||
@@ -187,6 +215,37 @@
|
||||
allocate-base;
|
||||
};
|
||||
|
||||
mem-buf-message-queue-pair {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/membuf-msgq-pair";
|
||||
message-size = <0x000000f0>;
|
||||
queue-depth = <0x00000008>;
|
||||
peer-default;
|
||||
qcom,label = <0x0000001>;
|
||||
};
|
||||
|
||||
ddump-shm {
|
||||
vdevice-type = "shm-doorbell";
|
||||
generate = "/hypervisor/ddump-shm";
|
||||
push-compatible = "qcom,ddump-gunyah-gen";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x7>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
gunyah-panic-notifier-shm {
|
||||
vdevice-type = "shm-doorbell";
|
||||
generate = "/hypervisor/gpn-shm";
|
||||
push-compatible = "qcom,gunyah-panic-gen";
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x9>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
|
||||
gpiomem0 {
|
||||
vdevice-type = "iomem";
|
||||
patch = "/soc/tlmm-vm-mem-access";
|
||||
@@ -199,6 +258,37 @@
|
||||
};
|
||||
};
|
||||
|
||||
test-dbl-tuivm {
|
||||
vdevice-type = "doorbell";
|
||||
generate = "/hypervisor/test-dbl-tuivm";
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-dbl-tuivm-source {
|
||||
vdevice-type = "doorbell-source";
|
||||
generate = "/hypervisor/test-dbl-tuivm-source";
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-msgq-tuivm {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/test-msgq-tuivm-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0x4>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
test-large-dmabuf-tuivm {
|
||||
vdevice-type = "message-queue-pair";
|
||||
generate = "/hypervisor/test-large-dmabuf-tuivm-pair";
|
||||
message-size = <0xf0>;
|
||||
queue-depth = <0x8>;
|
||||
qcom,label = <0xd>;
|
||||
peer-default;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
@@ -245,15 +335,13 @@
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
/* Valid pins */
|
||||
gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>;
|
||||
gpios = /bits/ 16 <77 78 14 126 16 17 18 19 189 176 44 45 46 47>;
|
||||
};
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
compatible = "qcom,tlmm-vm-mem-access";
|
||||
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
|
||||
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
|
||||
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
|
||||
tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
|
||||
};
|
||||
|
||||
tlmm-vm-test {
|
||||
@@ -261,10 +349,8 @@
|
||||
pinctrl-names = "active", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_7i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
|
||||
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
|
||||
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
|
||||
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
|
||||
tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
|
||||
};
|
||||
|
||||
pinctrl@f000000 {
|
||||
@@ -311,6 +397,15 @@
|
||||
<0x17180000 0x200000>; /* GICR * 8 */
|
||||
};
|
||||
|
||||
ipcc_mproc_ns1: qcom,ipcc@407000 {
|
||||
compatible = "qcom,ipcc";
|
||||
reg = <0x407000 0x1000>;
|
||||
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
arch_timer: timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
always-on;
|
||||
@@ -330,4 +425,251 @@
|
||||
qcom,custom-bridge-size = <64>;
|
||||
qcom,support-hypervisor;
|
||||
};
|
||||
|
||||
qti,smmu-proxy {
|
||||
compatible = "smmu-proxy-receiver";
|
||||
};
|
||||
|
||||
qti,smmu-proxy-camera-cb {
|
||||
compatible = "smmu-proxy-cb";
|
||||
qti,cb-id = <QTI_SMMU_PROXY_CAMERA_CB>;
|
||||
qcom,iommu-defer-smr-config;
|
||||
iommus = <&apps_smmu 0x1810 0x20>,
|
||||
<&apps_smmu 0x1C10 0x0>,
|
||||
<&apps_smmu 0x18F0 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qcom,gunyah-panic-notifier {
|
||||
compatible = "qcom,gh-panic-notifier";
|
||||
gunyah-label = <9>;
|
||||
};
|
||||
|
||||
qcom,test-dbl-tuivm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x4>;
|
||||
};
|
||||
|
||||
qcom,test-msgq-tuivm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <0x4>;
|
||||
affinity = <0>;
|
||||
};
|
||||
|
||||
qcom,test-large-dmabuf-tuivm {
|
||||
compatible = "qcom,gh-large-dmabuf-test";
|
||||
gunyah-label = <0xd>;
|
||||
};
|
||||
|
||||
qcom,gh-qtimer@1742b000 {
|
||||
compatible = "qcom,gh-qtmr";
|
||||
reg = <0x1742b000 0x1000>;
|
||||
reg-names = "qtmr-base";
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qcom,qtmr-intr";
|
||||
qcom,secondary;
|
||||
};
|
||||
|
||||
qti,smmu-proxy-display-cb {
|
||||
compatible = "smmu-proxy-cb";
|
||||
qti,cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
|
||||
qcom,iommu-defer-smr-config;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
iommus = <&apps_smmu 0x801 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qti,smmu-proxy-eva-cb {
|
||||
compatible = "smmu-proxy-cb";
|
||||
qti,cb-id = <QTI_SMMU_PROXY_EVA_CB>;
|
||||
qcom,iommu-defer-smr-config;
|
||||
qcom,iommu-dma-addr-pool = <0x00000000 0xffffffff>;
|
||||
iommus = <&apps_smmu 0x1927 0x0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qcom,mem-buf {
|
||||
compatible = "qcom,mem-buf";
|
||||
qcom,mem-buf-capabilities = "consumer";
|
||||
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
||||
qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */
|
||||
qcom,vmid = <45>;
|
||||
};
|
||||
|
||||
mem_buf_msgq: qcom,mem-buf-msgq {
|
||||
compatible = "qcom,mem-buf-msgq";
|
||||
qcom,msgq-names = "trusted_vm";
|
||||
};
|
||||
|
||||
virtio_mem_device {
|
||||
compatible = "qcom,virtio-mem";
|
||||
depends-on-supply = <&mem_buf_msgq>;
|
||||
/* Must be memory_block_size_bytes() aligned */
|
||||
qcom,max-size = <0x0 0x18000000>;
|
||||
qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>;
|
||||
qcom,block-size = <0x400000>;
|
||||
qcom,initial-movable-zone-size = <0x2000000>;
|
||||
};
|
||||
|
||||
/*
|
||||
* QUP1 : SE4 - Primary touch
|
||||
* QUP2 : SE7 - Secondary touch
|
||||
*/
|
||||
qup_iommu_group: qup_common_iommu_group {
|
||||
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
|
||||
<&qupv3_1 0x00000000 0x00020000>,
|
||||
<&gpi_dma2 0x00000000 0x00020000>,
|
||||
<&qupv3_2 0x00000000 0x00020000>;
|
||||
};
|
||||
|
||||
/* QUPv3_1 GPI Instance */
|
||||
gpi_dma1: qcom,gpi-dma@a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0xa00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0xb8 0x0>;
|
||||
qcom,iommu-group = <&qup_iommu_group>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
qcom,static-gpii-mask = <0x20>;
|
||||
qcom,gpii-mask = <0x0>;
|
||||
qcom,ev-factor = <1>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
qcom,le-vm;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_1 wrapper instance */
|
||||
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0xac0000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0xb8 0x0>;
|
||||
qcom,iommu-group = <&qup_iommu_group>;
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
/* Touchscreen I2C Instance */
|
||||
qupv3_se4_i2c: i2c@a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&gpi_dma1 0 4 3 64 0xc>,
|
||||
<&gpi_dma1 1 4 3 64 0xc>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,le-vm;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Touchscreen SPI Instance */
|
||||
qupv3_se4_spi: spi@a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0xa90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
dmas = <&gpi_dma1 0 4 1 64 0xc>,
|
||||
<&gpi_dma1 1 4 1 64 0xc>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,le-vm;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
/* QUPv3_2 GPI Instance */
|
||||
gpi_dma2: qcom,gpi-dma@800000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x800000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0x438 0x0>;
|
||||
qcom,iommu-group = <&qup_iommu_group>;
|
||||
dma-coherent;
|
||||
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
qcom,static-gpii-mask = <0x20>;
|
||||
qcom,gpii-mask = <0x0>;
|
||||
qcom,ev-factor = <1>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
qcom,le-vm;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_2 wrapper instance */
|
||||
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x8c0000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x438 0x0>;
|
||||
qcom,iommu-group = <&qup_iommu_group>;
|
||||
dma-coherent;
|
||||
ranges;
|
||||
status = "ok";
|
||||
|
||||
/* Secondary Tounch */
|
||||
qupv3_se15_i2c: i2c@89c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x89c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&gpi_dma2 0 7 3 64 0xc>,
|
||||
<&gpi_dma2 1 7 3 64 0xc>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,le-vm;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Secondary Tounch */
|
||||
qupv3_se15_spi: spi@89c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x89c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
dmas = <&gpi_dma2 0 7 1 64 0xc>,
|
||||
<&gpi_dma2 1 7 1 64 0xc>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,le-vm;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "msm-arm-smmu-tuna-vm.dtsi"
|
||||
#include "tuna-vm-dma-heaps.dtsi"
|
||||
|
||||
293
qcom/tuna.dtsi
293
qcom/tuna.dtsi
@@ -20,6 +20,8 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/power/qcom-aoss-qmp.h>
|
||||
#include <dt-bindings/clock/qcom,aop-qmp.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Tuna";
|
||||
@@ -36,7 +38,7 @@
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance";
|
||||
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket";
|
||||
stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
|
||||
};
|
||||
|
||||
@@ -44,11 +46,18 @@
|
||||
|
||||
ddr-regions { };
|
||||
|
||||
mem-offline {
|
||||
compatible = "qcom,mem-offline";
|
||||
offline-sizes = <0x2 0xc0000000 0x1 0x0>;
|
||||
granule = <512>;
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
};
|
||||
|
||||
firmware: firmware {
|
||||
qcom_scm: qcom_scm {};
|
||||
};
|
||||
|
||||
aliases {
|
||||
aliases: aliases {
|
||||
serial0 = &qupv3_se7_2uart;
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
|
||||
mmc1 = &sdhc_2; /* SDC2 SD card slot */
|
||||
@@ -648,6 +657,18 @@
|
||||
|
||||
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cap-based-alloc-and-pwr-collapse;
|
||||
|
||||
llcc_perfmon {
|
||||
compatible = "qcom,llcc-perfmon";
|
||||
clocks = <&aoss_qmp QDSS_CLK>;
|
||||
clock-names = "qdss_clk";
|
||||
};
|
||||
};
|
||||
|
||||
gic-interrupt-router {
|
||||
compatible = "qcom,gic-intr-routing";
|
||||
qcom,gic-class0-cpus = <&CPU0 &CPU1>;
|
||||
qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
|
||||
};
|
||||
|
||||
apps_rsc: rsc@17a00000 {
|
||||
@@ -710,6 +731,7 @@
|
||||
|
||||
qcom,mem-buf-msgq {
|
||||
compatible = "qcom,mem-buf-msgq";
|
||||
qcom,msgq-names = "trusted_vm", "oem_vm";
|
||||
};
|
||||
|
||||
cam_rsc: rsc@adc8000 {
|
||||
@@ -813,6 +835,55 @@
|
||||
};
|
||||
};
|
||||
|
||||
disp_crm: crm@af21000 {
|
||||
label = "disp_crm";
|
||||
compatible = "qcom,disp-crm-v2";
|
||||
reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>,
|
||||
<0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>;
|
||||
reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
|
||||
interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 714 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 96 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "disp_crm_drv0",
|
||||
"disp_crm_drv1",
|
||||
"disp_crm_drv2",
|
||||
"disp_crm_drv3",
|
||||
"disp_crm_drv4",
|
||||
"disp_crm_drv5";
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
|
||||
qcom,hw-drv-ids = <0 1 2 3 4 5>;
|
||||
qcom,sw-drv-ids = <0 1 2 3 4 5>;
|
||||
};
|
||||
|
||||
cam_crm: crm@adcb000 {
|
||||
label = "cam_crm";
|
||||
compatible = "qcom,cam-crm-v2";
|
||||
reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd200 0x400>,
|
||||
<0xadcd600 0x2000>, <0xadcf600 0x700>, <0xadcfd00 0x100>;
|
||||
reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "cam_crm_drv0";
|
||||
clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
|
||||
qcom,hw-drv-ids = <0 1 2>;
|
||||
qcom,sw-drv-ids = <0>;
|
||||
};
|
||||
|
||||
pcie_crm: crm@1d01000 {
|
||||
label = "pcie_crm";
|
||||
compatible = "qcom,pcie-crm-v2";
|
||||
reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>,
|
||||
<0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>;
|
||||
reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common";
|
||||
interrupts = <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "pcie_crm_drv0";
|
||||
clocks = <&pcie_0_pipe_clk>;
|
||||
qcom,hw-drv-ids = <0 1>;
|
||||
qcom,sw-drv-ids = <0>;
|
||||
};
|
||||
|
||||
pdc: interrupt-controller@b220000 {
|
||||
compatible = "qcom,tuna-pdc", "qcom,pdc";
|
||||
reg = <0xb220000 0x10000>, <0x174000f0 0x64>;
|
||||
@@ -835,6 +906,16 @@
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
adsp_sleepmon: adsp-sleepmon {
|
||||
compatible = "qcom,adsp-sleepmon";
|
||||
qcom,rproc-handle = <&adsp_pas>;
|
||||
};
|
||||
|
||||
pcie_pdc: pdc@b360000 {
|
||||
compatible = "qcom,tuna-pcie-pdc", "qcom,pcie-pdc";
|
||||
reg = <0xb360000 0x10000>;
|
||||
};
|
||||
|
||||
adsp_pas: remoteproc-adsp@03000000 {
|
||||
compatible = "qcom,tuna-adsp-pas";
|
||||
reg = <0x03000000 0x10000>;
|
||||
@@ -1059,6 +1140,66 @@
|
||||
};
|
||||
};
|
||||
|
||||
qcom,glinkpkt {
|
||||
compatible = "qcom,glinkpkt";
|
||||
|
||||
qcom,glinkpkt-at-mdm0 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DS";
|
||||
qcom,glinkpkt-dev-name = "at_mdm0";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-apr-apps2 {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "apr_apps2";
|
||||
qcom,glinkpkt-dev-name = "apr_apps2";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data40-cntl {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
||||
qcom,glinkpkt-dev-name = "smdcntl8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data1 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA1";
|
||||
qcom,glinkpkt-dev-name = "smd7";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data4 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA4";
|
||||
qcom,glinkpkt-dev-name = "smd8";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-data11 {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "DATA11";
|
||||
qcom,glinkpkt-dev-name = "smd11";
|
||||
};
|
||||
|
||||
qcom,glinkpkt-qmc-dma {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
|
||||
qcom,glinkpkt-dev-name = "qmc_dma";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-qmc-cma {
|
||||
qcom,glinkpkt-edge = "mpss";
|
||||
qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
|
||||
qcom,glinkpkt-dev-name = "qmc_cma";
|
||||
qcom,glinkpkt-enable-ch-close;
|
||||
};
|
||||
|
||||
qcom,glinkpkt-xpan_control {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "bt_cp_ctrl";
|
||||
qcom,glinkpkt-dev-name = "bt_cp_ctrl";
|
||||
};
|
||||
};
|
||||
|
||||
sys-pm-vx@c320000 {
|
||||
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna";
|
||||
reg = <0xc320000 0x400>;
|
||||
@@ -1083,20 +1224,16 @@
|
||||
tuivm {
|
||||
qcom,label = <0x08>;
|
||||
qcom,vmid = <45>;
|
||||
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
|
||||
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
|
||||
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
|
||||
tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
|
||||
};
|
||||
};
|
||||
|
||||
tlmm-vm-test {
|
||||
compatible = "qcom,tlmm-vm-test";
|
||||
qcom,master;
|
||||
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
|
||||
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
|
||||
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
|
||||
tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>;
|
||||
};
|
||||
|
||||
slimbam: bamdma@6c04000 {
|
||||
@@ -1460,6 +1597,19 @@
|
||||
#size-cells = <1>;
|
||||
read-only;
|
||||
ranges;
|
||||
feat_conf6: feat_conf6@0118 {
|
||||
reg = <0x0118 0x4>;
|
||||
};
|
||||
|
||||
feat_conf18: feat_conf18@0148 {
|
||||
reg = <0x0148 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
qfprom_sys: qfprom@0 {
|
||||
compatible = "qcom,qfprom-sys";
|
||||
nvmem-cells = <&feat_conf6>, <&feat_conf18>;
|
||||
nvmem-cell-names = "feat_conf6", "feat_conf18";
|
||||
};
|
||||
|
||||
clocks {
|
||||
@@ -1544,7 +1694,7 @@
|
||||
|
||||
sram@c3f0000 {
|
||||
compatible = "qcom,rpmh-stats-v4";
|
||||
reg = <0x0c3f0000 0x3ff>;
|
||||
reg = <0x0c3f0000 0x400>;
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
ss-name = "modem", "wpss", "adsp", "adsp_island",
|
||||
"cdsp", "apss";
|
||||
@@ -1577,7 +1727,7 @@
|
||||
<&cpufreq_hw 3>;
|
||||
};
|
||||
|
||||
cam_crm: syscon@adcd600 {
|
||||
camcc_crm: syscon@adcd600 {
|
||||
compatible = "syscon";
|
||||
reg = <0xadcd600 0x2000>;
|
||||
};
|
||||
@@ -1595,7 +1745,7 @@
|
||||
clock-names = "bi_tcxo",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
qcom,cam_crm-crmc = <&cam_crm>;
|
||||
qcom,cam_crm-crmc = <&camcc_crm>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -1619,7 +1769,8 @@
|
||||
"bi_tcxo_ao",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
qcom,dispcc_crm-crmc = <&dispcc_crm>;
|
||||
qcom,disp_crm-crmc = <&dispcc_crm>;
|
||||
#power-domain-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -1680,13 +1831,16 @@
|
||||
"gpll0_out_main_div";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
gxclkctl: clock-controller@3d68024 {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "gxclkctl_clocks";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "qcom,tuna-gx_clkctl";
|
||||
reg = <0x3d68024 0x8>;
|
||||
reg-name = "cc_base";
|
||||
power-domains = <&gpucc GPU_CC_CX_GDSC>;
|
||||
vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
tcsrcc: clock-controller@1fbf000 {
|
||||
@@ -1703,6 +1857,7 @@
|
||||
reg-name = "cc_base";
|
||||
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
||||
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
|
||||
vdd_mm_mxc_voter-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
@@ -1711,6 +1866,7 @@
|
||||
"bi_tcxo_ao",
|
||||
"sleep_clk",
|
||||
"iface";
|
||||
#power-domain-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -1847,6 +2003,10 @@
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
qti,smmu-proxy {
|
||||
compatible = "smmu-proxy-sender";
|
||||
};
|
||||
|
||||
clk_virt: interconnect@0 {
|
||||
compatible = "qcom,tuna-clk_virt";
|
||||
#interconnect-cells = <1>;
|
||||
@@ -2039,6 +2199,9 @@
|
||||
interconnect-names = "sdhc-ddr","cpu-sdhc";
|
||||
operating-points-v2 = <&sdhc2_opp_table>;
|
||||
|
||||
resets = <&gcc GCC_SDCC2_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qos0 {
|
||||
mask = <0xc0>;
|
||||
vote = <44>;
|
||||
@@ -2162,7 +2325,7 @@
|
||||
qcom,bypass-pbl-rst-wa;
|
||||
qcom,max-cpus = <8>;
|
||||
|
||||
reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
@@ -2412,6 +2575,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
qcom,qrtr-gunyah-oemvm {
|
||||
compatible = "qcom,qrtr-gunyah";
|
||||
qcom,master;
|
||||
gunyah-label = <8>;
|
||||
peer-name = <4>;
|
||||
};
|
||||
|
||||
trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring {
|
||||
size = <0x4000>;
|
||||
gunyah-label = <0x11>;
|
||||
@@ -2549,6 +2720,67 @@
|
||||
};
|
||||
};
|
||||
|
||||
qcom,test-dbl-tuivm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x4>;
|
||||
};
|
||||
|
||||
qcom,test-dbl-oemvm {
|
||||
compatible = "qcom,gh-dbl";
|
||||
qcom,label = <0x5>;
|
||||
};
|
||||
|
||||
qcom,test-msgq-tuivm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <0x4>;
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,test-msgq-oemvm {
|
||||
compatible = "qcom,gh-msgq-test";
|
||||
gunyah-label = <0x5>;
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,test-large-dmabuf-tuivm {
|
||||
compatible = "qcom,gh-large-dmabuf-test";
|
||||
gunyah-label = <0xd>;
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,test-large-dmabuf-oemvm {
|
||||
compatible = "qcom,gh-large-dmabuf-test";
|
||||
gunyah-label = <0xe>;
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,gh-qtimer@1742b000 {
|
||||
compatible = "qcom,gh-qtmr";
|
||||
reg = <0x1742b000 0x1000>;
|
||||
reg-names = "qtmr-base";
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "qcom,qtmr-intr";
|
||||
qcom,primary;
|
||||
};
|
||||
|
||||
qcom,gunyah-panic-notifier {
|
||||
compatible = "qcom,gh-panic-notifier";
|
||||
qcom,primary-vm;
|
||||
gunyah-label = <9>;
|
||||
peer-name = <2>;
|
||||
memory-region = <&vm_comm_mem>;
|
||||
shared-buffer-size = <0x1000>;
|
||||
};
|
||||
|
||||
dmesg-dump {
|
||||
compatible = "qcom,dmesg-dump";
|
||||
qcom,primary-vm;
|
||||
gunyah-label = <7>;
|
||||
peer-name = <2>;
|
||||
memory-region = <&vm_comm_mem>;
|
||||
shared-buffer-size = <0x1000>;
|
||||
};
|
||||
|
||||
mmio_sram: mmio-sram@17D09400 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@@ -2981,31 +3213,37 @@
|
||||
#include "ipcc-test-no-slpi.dtsi"
|
||||
|
||||
&cam_cc_ipe_0_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_ofe_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_0_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_1_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_tfe_2_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&cam_cc_titan_top_gdsc {
|
||||
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
||||
compatible = "qcom,gdsc";
|
||||
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
|
||||
interconnect-names = "mmnoc";
|
||||
@@ -3016,13 +3254,11 @@
|
||||
&disp_cc_mdss_core_gdsc {
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&disp_cc_mdss_core_int2_gdsc {
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
||||
parent-supply = <&VDD_MM_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&eva_cc_mvs0_gdsc {
|
||||
@@ -3077,25 +3313,21 @@
|
||||
&gpu_cc_cx_gdsc {
|
||||
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
|
||||
parent-supply = <&VDD_CX_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&gx_clkctl_gx_gdsc {
|
||||
parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&video_cc_mvs0c_gdsc {
|
||||
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
||||
clock-names = "ahb_clk";
|
||||
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&reserved_memory {
|
||||
@@ -3166,6 +3398,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
#include "tuna-coresight.dtsi"
|
||||
#include "tuna-debug.dtsi"
|
||||
#include "tuna-pinctrl.dtsi"
|
||||
#include "tuna-regulators.dtsi"
|
||||
#include "tuna-usb.dtsi"
|
||||
@@ -3178,3 +3412,12 @@
|
||||
&qupv3_se7_2uart {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&qupv3_se3_i2c {
|
||||
status = "ok";
|
||||
wcd_usbss: wcd939x_i2c@e {
|
||||
compatible = "qcom,wcd939x-i2c";
|
||||
reg = <0xe>;
|
||||
vdd-usb-cp-supply = <&L7B>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -8,4 +8,9 @@
|
||||
model = "Qualcomm Technologies, Inc. Tuna 7";
|
||||
compatible = "qcom,tuna";
|
||||
qcom,msm-id = <681 0x10000>;
|
||||
|
||||
};
|
||||
|
||||
&adsp_pas {
|
||||
firmware-name = "adsp2.mdt", "adsp2_dtb.mdt";
|
||||
};
|
||||
|
||||
@@ -210,7 +210,7 @@
|
||||
peer-default;
|
||||
memory {
|
||||
qcom,label = <0x8>;
|
||||
qcom,mem-info-tag = <0x2>;
|
||||
qcom,mem-info-tag = <0x3>;
|
||||
allocate-base;
|
||||
};
|
||||
};
|
||||
@@ -287,7 +287,9 @@
|
||||
|
||||
tlmm-vm-mem-access {
|
||||
compatible = "qcom,tlmm-vm-mem-access";
|
||||
tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>;
|
||||
tlmm-vm-gpio-list = <&tlmm 64 0 &tlmm 65 0 &tlmm 66 0 &tlmm 67 0 &tlmm 0 0
|
||||
&tlmm 4 0 &tlmm 86 0 &tlmm 87 0 &tlmm 16 0 &tlmm 17 0
|
||||
&tlmm 18 0 &tlmm 19 0 &tlmm 20 0 &tlmm 21 0>;
|
||||
};
|
||||
|
||||
vgic: interrupt-controller@17100000 {
|
||||
|
||||
Reference in New Issue
Block a user