From 8d05ccb477a63356593e0b739ad1f9e317156742 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Tue, 3 Sep 2024 16:56:08 +0800 Subject: [PATCH 001/112] ARM: dts: msm: remove always-on for hap-swr-slave regulator Remove regulator-always-on property for hap-swr-slave as the driver has updated to keep the SWR slave always enabled for HAP530_HV haptics module which is inside pmih010x. Change-Id: I15eddff38dcdc25012b944572085add11587903c Signed-off-by: Fenglin Wu --- qcom/pmih010x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/pmih010x.dtsi b/qcom/pmih010x.dtsi index 6f31c3c3..25f79e01 100644 --- a/qcom/pmih010x.dtsi +++ b/qcom/pmih010x.dtsi @@ -62,7 +62,6 @@ hap_swr_slave_reg: qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - regulator-always-on; }; /* From 2af94b67e37a9717d44a5f1282424083b880427c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Wed, 11 Sep 2024 17:48:59 +0530 Subject: [PATCH 002/112] ARM: dts: msm: Remove clocks property form CPU nodes The initialization of the OPP table from the device tree is failing because the OPP framework expects the CPUFreq node to act as a clock provider due to the presence of the clocks property in CPU nodes. However, the qcom-cpufreq-hw scaling driver doesn't have the support for handling the CPUFreq node as a clock provider, resulting in an -EPROBE_DEFER error. Thus, to resolve this issue, remove the clocks property from the CPU nodes. Change-Id: I243807f58dc82c55f4ec390c09752b8652ac2706 Signed-off-by: Imran Shaik --- qcom/sdxkova.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index bb5a6bde..65496054 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -720,3 +720,19 @@ #include "sdxkova-usb.dtsi" #include "ipcc-test-sdxkova.dtsi" + +&CPU0 { + /delete-property/ clocks; +}; + +&CPU1 { + /delete-property/ clocks; +}; + +&CPU2 { + /delete-property/ clocks; +}; + +&CPU3 { + /delete-property/ clocks; +}; From 2b7c0bbfa8debdd2b0ae190dedcf235aa05d85a9 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Fri, 27 Sep 2024 15:20:19 +0530 Subject: [PATCH 003/112] ARM: dts: msm: Define qcom,display heap for tuna The qcom,display heap is used for camera usecases. Change-Id: Ib4cd937450c73cc8440be20912fe864653663577 Signed-off-by: Akash Gajjar --- qcom/tuna-dma-heaps.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/tuna-dma-heaps.dtsi b/qcom/tuna-dma-heaps.dtsi index 9e9b9381..f41a1746 100644 --- a/qcom/tuna-dma-heaps.dtsi +++ b/qcom/tuna-dma-heaps.dtsi @@ -10,6 +10,13 @@ compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = ; From ce5b2d66547f0960db0a09fe843580a0f8fe40ca Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Tue, 1 Oct 2024 11:14:54 +0530 Subject: [PATCH 004/112] ARM: dts: msm: Add smp2p node for Kera Add the smp2p device node to enable smp2p communication with WPSS. Change-Id: I3cd90e4d035fe0ef7d6f5e7480fb3966fd8c6921 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/kera.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d735c7d3..7f827e30 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -608,6 +608,28 @@ }; }; + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + qcom,smp2p-soccp { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; From 12a89c859a3eb590286e47eadb06f9b9cf83e294 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 3 Oct 2024 11:08:29 +0530 Subject: [PATCH 005/112] ARM: dts: msm: Adding memory region for USB Tuna In this change adding memory region for iommu node for tuna. Change-Id: I50bc3d510bfab93bc5bfc22c2e3c44b9c450c8f1 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 88fa476e..c75fe5a6 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -12,8 +12,8 @@ reg = <0xa600000 0x100000>; reg-names = "core_base"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -35,13 +35,13 @@ qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-disconnected = <133333333>; - dwc3@a600000 { + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd93c>; + reg = <0x0 0xa600000 0x0 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; @@ -59,4 +59,10 @@ usb-role-switch; }; }; + + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + }; From d0dd9b24bc25fea7a2a784a1d0089be96135ddcb Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 3 Oct 2024 16:12:51 +0530 Subject: [PATCH 006/112] ARM: dts: msm: Add high speed usb support & interrupts for Tuna The high speed phy is required for USB to support HS usecases. Add eusb node on tuna which includes the necessary resources for the eusb phy to work. Additional: Added interrupts for tuna. Change-Id: Ifa3484bd52f876804b455e46a67a3b7b28fc663d Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index c75fe5a6..574e8c8a 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -28,8 +28,15 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + qcom,use-pdc-interrupts; + qcom,use-eusb2-phy; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; @@ -45,6 +52,7 @@ dma-coherent; interrupts = ; + usb-phy = <&eusb2_phy0>, <&usb_nop_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -65,4 +73,30 @@ <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; }; + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-snps-eusb2-phy"; + reg = <0x88e3000 0x154>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&L3B>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdd_refgen-supply = <&L2B>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + }; From 632193f30be6d625e3a425b91c3517efd6ddf2a2 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 3 Oct 2024 16:17:24 +0530 Subject: [PATCH 007/112] ARM: dts: msm: Added interconnects for Tuna This change adds interconnects on Tuna USB. Change-Id: I2f2a6d5948225dbfeb3d20db7693318977033956 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 574e8c8a..702269d1 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -35,6 +35,11 @@ interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + qcom,use-pdc-interrupts; qcom,use-eusb2-phy; From b3fb8a470a1827554d4857ef746356b8b255cef5 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Wed, 9 Oct 2024 11:06:41 +0530 Subject: [PATCH 008/112] ARM: dts: msm: Add glink egde for adsp, modem and cdsp Add glink adsp, modem and cdsp device tree entries for Kera. Change-Id: I3fad2af52e8068adfbba86418b4f90b0ec362b43 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/kera.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 6ad9f48d..448b6a16 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -438,6 +438,42 @@ /* Outputs to turing */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_adsp_glink: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; + }; }; cdsp_pas: remoteproc-cdsp@32300000 { @@ -480,6 +516,42 @@ /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_cdsp_glink: glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12 + 0xF00 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1>; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; }; modem_pas: remoteproc-mss@04080000 { @@ -521,6 +593,34 @@ /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; }; tlmm: pinctrl@f000000 { From 8954f28a7e68c0833230b037ce5b3abbfd5d19bd Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Wed, 9 Oct 2024 15:01:22 +0530 Subject: [PATCH 009/112] ARM: dts: msm: Set vCPU affinity to CPU0 for VMs on Tuna Even though we use proxy scheduling, during VM bootup hypervisor tries to boot the VMs as per the affinity-map. This may cause panic in case a CPU within affinity-map is unavailable. Affining vCPUs to CPU0 makes sure VM proceeds with powered-ON sequence, assuming CPU0 is always available. Change-Id: Ia6799445891e1b003b5055178adb50778bade863 Signed-off-by: Hrishabh Rajput --- qcom/tuna-oemvm.dtsi | 2 +- qcom/tuna-vm.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 3bbe6c32..74363a94 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -87,7 +87,7 @@ vcpus { config = "/cpus"; affinity = "proxy"; - affinity-map = <0x5 0x6>; + affinity-map = <0x0 0x0>; sched-priority = <0>; /* relative to PVM */ sched-timeslice = <2000>; /* in ms */ }; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 830368e7..ae8c40a9 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -96,7 +96,7 @@ vcpus { config = "/cpus"; affinity = "proxy"; - affinity-map = <0x5 0x6>; + affinity-map = <0x0 0x0>; sched-priority = <0>; /* relative to PVM */ sched-timeslice = <2000>; /* in ms */ }; From 85fd55734a11d769f41718403761e2811e3e164f Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 4 Oct 2024 13:54:50 +0530 Subject: [PATCH 010/112] ARM: dts: qcom: Add QMP DP phy node & init sequence for Tuna QMP phy is used for SS/SSP usb usecases as well as DP use cases in a target. This change adds the basic resources required along with the init sequence for functionality. Note: init sequence is following Kalama QMP init sequence and ref_clk is set to 38.4 Mhz. Change-Id: I9422f9af88801fa0dde4d79a7e72ec74e264420d Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 212 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 212 insertions(+) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 702269d1..be73ee25 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -104,4 +104,216 @@ compatible = "usb-nop-xceiv"; }; + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L3B>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4B>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* based on tsmcn3e_USB3_Gen2_Seq v1.6 */ + + ; + }; + }; From 8f9a845d79007389949af156016c647719453334 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 4 Oct 2024 14:09:08 +0530 Subject: [PATCH 011/112] ARM: dts: msm: Add qmi audio node on Tuna USB Adding the necessary audio node providing the necessary resources of the qmi audio to get probed. Note: SID for usb audio is 100B. Change-Id: Ib55eb5957d38e8551c2a2bda5446fc64539203e1 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index be73ee25..bf875987 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -316,4 +316,12 @@ USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>; }; + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100b 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xb>; + qcom,usb-audio-intr-num = <2>; + }; + }; From a0b0aec77beb19177826198fbcb3f3141a570ffb Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 8 Oct 2024 15:03:15 +0530 Subject: [PATCH 012/112] ARM: dts: msm: Add register entry to ssusb in tuna Adding a 4-byte register entry for tcsr_dyn-en-dis to enable/disable USB dynamically from dwc3-msm-core. Change-Id: I34163cf381ff92d90dc687817612f0f191407501 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index bf875987..59d0d614 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -9,8 +9,10 @@ &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; - reg = <0xa600000 0x100000>; - reg-names = "core_base"; + reg = <0xa600000 0x100000>, + <0x1fc6000 0x4>; + reg-names = "core_base", + "tcsr_dyn_en_dis"; #address-cells = <2>; #size-cells = <2>; From b5c45e7d59e7fe5878ca63fb9d50bda970bedf0d Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 10 Oct 2024 14:48:57 +0800 Subject: [PATCH 013/112] dt-bindings: qcom,hv-haptics: add qcom,hbst-ovp-trim property Add qcom,hbst-ovp-trim property as an option for SW to trigger hBoost OVP trim sequence. The sequence adjusts certain trim registers and reduces hBoost voltage stepper rate. The adjustment can help in preventing hBoost overshoots that might trigger OVP and potentially lead to the shutdown of haptics driver. Change-Id: I8e1e84053015e6aec46d1ba874243e66acb2d23a Signed-off-by: Fenglin Wu --- bindings/input/qcom,hv-haptics.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/input/qcom,hv-haptics.yaml b/bindings/input/qcom,hv-haptics.yaml index 70997a88..4eb33ab5 100644 --- a/bindings/input/qcom,hv-haptics.yaml +++ b/bindings/input/qcom,hv-haptics.yaml @@ -161,6 +161,13 @@ properties: method is used for LRA resonant frequency detection. type: boolean + qcom,hbst-ovp-trim: + description: | + Boolean flag indicating that the hBoost OVP trim PBS sequence would be + triggered during driver initialization. This is only applicable for HAP530_HV + haptics module. + type: boolean + patternProperties: ".*hap-swr-slave-reg$": description: | From e60a33e4795dbdd9f9c9a24bdd8627b28b2c51f5 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Wed, 9 Oct 2024 13:20:18 +0530 Subject: [PATCH 014/112] ARM: dts: qcom: Add few nodes to optimize bootup time Add dsi_pll_codes and disp_rdump_region nodes in the beginning of devicetree to optimize the bootloader search for these nodes during bootup which reduces bootup time. Change-Id: I7b7fe798a9d0daf306d76bc34132574ba6e0e88e Signed-off-by: Saranya R --- qcom/parrot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index 80818f2f..d9660213 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -463,6 +463,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + dsi_pll_codes { + }; + + disp_rdump_region@e1000000 { + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 38a4667930a46dc6c7423fd52b49f74c8219fc7f Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 14 Aug 2024 13:56:47 +0530 Subject: [PATCH 015/112] ARM: dts: msm: Update dispcc clock node as GenPD provider Mark dispcc clock node as GenPD provider and disable the display GDSC regulator nodes for tuna platform. While at it, keep the gdsc regulator nodes as it is on rumi platform. Change-Id: Ia1ee65d9958ba8ab6cb00616a09cd5b2304bc31a Signed-off-by: Anaadi Mishra --- qcom/tuna-rumi.dtsi | 8 ++++++++ qcom/tuna.dtsi | 3 +-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 5f538408..04603181 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -196,3 +196,11 @@ clock-output-names = "rpmh_clocks"; clock-frequency = <19200000>; }; + +&disp_cc_mdss_core_gdsc { + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + status = "ok"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 7fdda1f4..6b8af30b 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1544,6 +1544,7 @@ "sleep_clk", "iface"; qcom,dispcc_crm-crmc = <&dispcc_crm>; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2570,13 +2571,11 @@ &disp_cc_mdss_core_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; - status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; - status = "ok"; }; &eva_cc_mvs0_gdsc { From 42da3aebaa19c4369a29ca9fcafe2b5f26c983c4 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 24 Sep 2024 10:39:04 +0530 Subject: [PATCH 016/112] ARM: dts: msm: Update tlmm-vm-gpio-list for parrot vm Update tlmm-vm-gpio-list for parrot vm. Change-Id: Id050bfd6b26406a6abff3ebbfa92d5a221e8f15b Signed-off-by: Saranya R --- qcom/parrot-pinctrl.dtsi | 9 +++++++++ qcom/parrot-vm.dtsi | 7 +++---- qcom/waipio-vm.dtsi | 6 ++++-- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi index 28d57699..b314a02f 100644 --- a/qcom/parrot-pinctrl.dtsi +++ b/qcom/parrot-pinctrl.dtsi @@ -1887,4 +1887,13 @@ }; }; + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + qcom,master; + tuivm { + qcom,label = <0x08>; + qcom,vmid = <45>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0>; + }; + }; }; diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 82ea3d9d..5ec070cb 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -53,14 +53,13 @@ <0x17260000 0x100000>; /* GICR * 8 */ }; - pinctrl@f000000 { + tlmm: pinctrl@f000000 { compatible = "qcom,parrot-vm-tlmm"; - gpios = /bits/ 16 <>; - qcom,gpios-reserved = <0 1 2 3 38>; + gpios = /bits/ 16 <98 99>; }; tlmm-vm-mem-access { - tlmm-vm-gpio-list = <>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0>; }; apps-smmu@15000000 { diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index a34d5ec9..80e2cdda 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -210,7 +210,7 @@ peer-default; memory { qcom,label = <0x8>; - qcom,mem-info-tag = <0x2>; + qcom,mem-info-tag = <0x3>; allocate-base; }; }; @@ -287,7 +287,9 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; - tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>; + tlmm-vm-gpio-list = <&tlmm 64 0 &tlmm 65 0 &tlmm 66 0 &tlmm 67 0 &tlmm 0 0 + &tlmm 4 0 &tlmm 86 0 &tlmm 87 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 20 0 &tlmm 21 0>; }; vgic: interrupt-controller@17100000 { From 3e2858be878d05bf73404351579dab44ea62940c Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 14 Oct 2024 11:15:43 +0530 Subject: [PATCH 017/112] ARM: dts: msm: Add chipinfo region as ext-region for cpusysvm Add chipinfo region as ext-region for cpusysvm for Kera. Change-Id: Id353eece5d4b825c75775f1c5be7201260007c1c Signed-off-by: Hrishabh Rajput --- qcom/kera-reserved-memory.dtsi | 5 +++++ qcom/kera.dtsi | 2 ++ 2 files changed, 7 insertions(+) diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi index 427aea63..a0c6bbdf 100644 --- a/qcom/kera-reserved-memory.dtsi +++ b/qcom/kera-reserved-memory.dtsi @@ -65,6 +65,11 @@ reg = <0x0 0x81ce4000 0x0 0x10000>; }; + chipinfo_mem: chipinfo_region@81cf4000 { + no-map; + reg = <0x0 0x81cf4000 0x0 0x1000>; + }; + smem_mem: smem_region@81d00000 { compatible = "qcom,smem"; reg = <0x0 0x81d00000 0x0 0x200000>; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..d12ebbfb 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1028,6 +1028,8 @@ qcom,vmid = <50>; qcom,firmware-name = "cpusys_vm"; memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; }; }; From 5acf7ffca0dfff76c4bb6f54fbd811ca38ff7125 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 14 Oct 2024 11:27:47 +0530 Subject: [PATCH 018/112] ARM: dts: msm: Add trustedvm and oemvm support for Kera Add device-tree nodes required to support trustedvm and oemvm on Kera. Change-Id: I7b978c5c166a4e00dcbc68c1ef6884f9ddeba72c Signed-off-by: Hrishabh Rajput --- qcom/kera.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..63dba51e 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1022,6 +1022,104 @@ #reset-cells = <1>; }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x10>; + }; + + + trust_ui_vm_vsock_ring: trust_ui_vm_vsock_ring { + size = <0xc000>; + gunyah-label = <0x15>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb { + size = <0x400000>; + gunyah-label = <0x12>; + }; + + trust_ui_vm: qcom,trust_ui_vm { + vm_name = "trustedvm"; + shared-buffers-size = <0x414000>; + shared-buffers = <&trust_ui_vm_vblk0_ring + &trust_ui_vm_vblk1_ring + &trust_ui_vm_vsock_ring + &trust_ui_vm_swiotlb>; + }; + + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x10>; + }; + + trust_ui_vm_virt_be2: trust_ui_vm_virt_be2@15 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x15>; + }; + + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + qcom,keep-running; + memory-region = <&trust_ui_vm_mem &vm_comm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0 + &trust_ui_vm_virt_be1 + &trust_ui_vm_virt_be2>; + }; + + oem_vm_vblk0_ring: oem_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x16>; + }; + + oem_vm_vblk1_ring: oem_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x13>; + }; + + oem_vm_swiotlb: oem_vm_swiotlb { + size = <0x100000>; + gunyah-label = <0x14>; + }; + + oem_vm: qcom,oem_vm { + vm_name = "oemvm"; + shared-buffers-size = <0x108000>; + shared-buffers = <&oem_vm_vblk0_ring &oem_vm_vblk1_ring &oem_vm_swiotlb>; + }; + + oem_vm_virt_be0: oem_vm_virt_be0@16 { + qcom,vm = <&oem_vm>; + qcom,label = <0x16>; + }; + + oem_vm_virt_be1: oem_vm_virt_be1@13 { + qcom,vm = <&oem_vm>; + qcom,label = <0x13>; + }; + + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <34>; + qcom,vmid = <49>; + qcom,firmware-name = "oemvm"; + qcom,keep-running; + memory-region = <&oem_vm_mem &vm_comm_mem>; + virtio-backends = <&oem_vm_virt_be0 &oem_vm_virt_be1>; + }; + gh-secure-vm-loader@2 { compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <35>; @@ -1150,6 +1248,28 @@ reg = <0x0 0x81c60000 0x0 0x20000>; }; + trust_ui_vm_mem: trust_ui_vm_region@f3800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf3800000 0x0 0x4400000>; + reusable; + alignment = <0x0 0x400000>; + }; + + oem_vm_mem: oem_vm_region@f7c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + reusable; + alignment = <0x0 0x400000>; + }; + + vm_comm_mem: vm_comm_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + adsp_mem_heap: adsp_heap_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; From 19d43b329c527f4757bc8fc5da7729894ef40037 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 14 Oct 2024 10:24:54 +0530 Subject: [PATCH 019/112] ARM: dts: msm: Add BOB regulator for tuna Add BOB regulator for tuna platforms so that clients can access the regulator and vote on it. Change-Id: Idd57e09c29eb1ef0b9a73f2ef9e64beae5040676 Signed-off-by: Kavya Nunna --- qcom/tuna-regulators.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index e0fb9e3d..fd4dd00a 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -483,6 +483,25 @@ }; }; + rpmh-regulator-bobb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobb1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + BOB: + pmxr2230_bob: regulator-pmxr2230-bob1 { + regulator-name = "pmxr2230_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + }; + }; + rpmh-regulator-msslvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "mss.lvl"; From 215c835038b5a9fa0e9db5bb049da0bb0ca203c4 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Wed, 25 Sep 2024 09:16:58 +0530 Subject: [PATCH 020/112] ARM: dts: msm: Add arm-smmu device on tuna-vm Describe the register, interrupts, and settings of the arm-smmu device. Change-Id: I8876e31db9cd232963987599c40d0d1b37e35f08 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-tuna-vm.dtsi | 62 ++++++++++++++++++++++++++++++++++ qcom/tuna-vm.dtsi | 2 ++ 2 files changed, 64 insertions(+) create mode 100644 qcom/msm-arm-smmu-tuna-vm.dtsi diff --git a/qcom/msm-arm-smmu-tuna-vm.dtsi b/qcom/msm-arm-smmu-tuna-vm.dtsi new file mode 100644 index 00000000..f9dabb87 --- /dev/null +++ b/qcom/msm-arm-smmu-tuna-vm.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x7>; + num-smrs = <0xe>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c08 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0804 0x0002 0x00000001>, + + /* NSP:Compute */ + <0x0c0b 0x0000 0x00000303>, + + /* SF:Camera IPE*/ + <0x1808 0x0020 0x00000001>, + + /* SF:Camera CDM IPE/IFE/OFE*/ + <0x1841 0x0000 0x00000001>, + <0x1861 0x0000 0x00000001>, + <0x1881 0x0000 0x00000001>, + + /* SF:Camera ICP*/ + <0x18c2 0x0000 0x00000001>, + <0x1982 0x0000 0x00000001>, + + /* SF:Camera CRE*/ + <0x18e8 0x0000 0x00000103>, + + /* SF:EVA */ + <0x1901 0x0020 0x00000103>, + <0x1925 0x0000 0x00000103>; + }; +}; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index b2f4335d..2fcee9f5 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -331,3 +331,5 @@ qcom,support-hypervisor; }; }; + +#include "msm-arm-smmu-tuna-vm.dtsi" From 689ef8fa7f2ff2d2e28b31c29f0bb67cc02aab3c Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 11:09:04 +0530 Subject: [PATCH 021/112] ARM: dts: msm: Add dma-buf heaps for tuna-vm Describe the available dma-buf memory pools on tuna-vm. Change-Id: Ia2bb3fff1f76a04c4f8a14b51917b59d029f8d5e Signed-off-by: Vijayanand Jitta --- qcom/tuna-vm-dma-heaps.dtsi | 12 ++++++++++++ qcom/tuna-vm.dtsi | 1 + 2 files changed, 13 insertions(+) diff --git a/qcom/tuna-vm-dma-heaps.dtsi b/qcom/tuna-vm-dma-heaps.dtsi index f784d64d..575b2573 100644 --- a/qcom/tuna-vm-dma-heaps.dtsi +++ b/qcom/tuna-vm-dma-heaps.dtsi @@ -9,6 +9,18 @@ compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + qcom,tui { + qcom,dma-heap-name = "qcom,tui"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,tui_demura { + qcom,dma-heap-name = "qcom,tui_demura"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + qcom,ms1 { qcom,dma-heap-name = "qcom,ms1"; qcom,dma-heap-type = ; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 2fcee9f5..7d1f765b 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -333,3 +333,4 @@ }; #include "msm-arm-smmu-tuna-vm.dtsi" +#include "tuna-vm-dma-heaps.dtsi" From e617a3fe0c6f9c10da427ca0a11bcc87b157804f Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 11:49:25 +0530 Subject: [PATCH 022/112] ARM: dts: msm: Add mem-buf device on tuna-vm Describe the properties and msgqs of the mem-buf device. Change-Id: I66e4847e8c141c917f3bda22663fc60e2634917a Signed-off-by: Vijayanand Jitta --- qcom/tuna-vm.dtsi | 20 ++++++++++++++++++++ qcom/tuna.dtsi | 1 + 2 files changed, 21 insertions(+) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 7d1f765b..a57acd86 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -187,6 +187,15 @@ allocate-base; }; + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + gpiomem0 { vdevice-type = "iomem"; patch = "/soc/tlmm-vm-mem-access"; @@ -330,6 +339,17 @@ qcom,custom-bridge-size = <64>; qcom,support-hypervisor; }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,vmid = <45>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; + }; }; #include "msm-arm-smmu-tuna-vm.dtsi" diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1a106540..00412bab 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -710,6 +710,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; }; cam_rsc: rsc@adc8000 { From eb791d346ba6e8993e165ceaba2d0282adf709a1 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 12:31:09 +0530 Subject: [PATCH 023/112] ARM: dts: msm: Add mem-buf device on oemvm Describe the properties and msgqs of the mem-buf device. Change-Id: Ie05f273fd3747d4bf7a071ad5addae285ab612b4 Signed-off-by: Vijayanand Jitta --- qcom/tuna-oemvm.dtsi | 19 +++++++++++++++++++ qcom/tuna.dtsi | 2 +- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 3bbe6c32..6b8f899a 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -163,6 +163,14 @@ allocate-base; }; + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x000000C>; + }; }; }; @@ -206,6 +214,17 @@ clock-frequency = <19200000>; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,vmid = <49>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "oem_vm"; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 00412bab..028f99f5 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -710,7 +710,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; - qcom,msgq-names = "trusted_vm"; + qcom,msgq-names = "trusted_vm", "oem_vm"; }; cam_rsc: rsc@adc8000 { From 3c86c8cc2a78f5462cc98503c361af17d16358db Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 12:41:23 +0530 Subject: [PATCH 024/112] ARM: dts: msm: Enable virtio-mem device for tuna-vm Describe the properties of the memory region virtio-mem supports. Also reserve the IPA space for dmabuf buffers. Change-Id: Iad6b41033884828a734aa8562dc3e4d45997968b Signed-off-by: Vijayanand Jitta --- qcom/tuna-vm.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index a57acd86..2cde4080 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -343,13 +343,25 @@ qcom,mem-buf { compatible = "qcom,mem-buf"; qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ qcom,vmid = <45>; }; - qcom,mem-buf-msgq { + mem_buf_msgq: qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; qcom,msgq-names = "trusted_vm"; }; + + virtio_mem_device { + compatible = "qcom,virtio-mem"; + depends-on-supply = <&mem_buf_msgq>; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x18000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + qcom,initial-movable-zone-size = <0x2000000>; + }; }; #include "msm-arm-smmu-tuna-vm.dtsi" From a7ce6b1cb4637af22ea32693cbdfe895303031b7 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 12:44:47 +0530 Subject: [PATCH 025/112] ARM: dts: msm: Enable virtio-mem device for oemvm on tuna Describe the properties of the memory region virtio-mem supports. Also reserve the IPA space for dmabuf buffers. Change-Id: I6baa1a7d00b26f1a885e9c85c57b7c30745dd5f6 Signed-off-by: Vijayanand Jitta --- qcom/tuna-oemvm.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 6b8f899a..e62fb3ab 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -217,6 +217,8 @@ qcom,mem-buf { compatible = "qcom,mem-buf"; qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ qcom,vmid = <49>; }; @@ -225,6 +227,14 @@ qcom,msgq-names = "oem_vm"; }; + virtio_mem_device { + compatible = "qcom,virtio-mem"; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x10000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; }; From 756274e4cc8aa70778d9dc9aa053bccf22b3f46e Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 16:37:53 +0530 Subject: [PATCH 026/112] ARM: dts: msm: Add clock and regulator for kgsl-smmu for kera Add clock and regulator which would be required for register accesses of kgsl-smmu for kera. Change-Id: I27045fc113f9bc2aa56455caae568f66253adf62 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-kera.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi index 106a073f..36319d07 100644 --- a/qcom/msm-arm-smmu-kera.dtsi +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -17,6 +17,13 @@ ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = + "gpu_cc_hlos1_vote_gpu_smmu"; + interrupts = , , , From db4d2f168b16b9f1a7b63870cd51bd3e61a66782 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 21:42:07 +0530 Subject: [PATCH 027/112] ARM: dts: msm: disable slub debug for sun Disable slub debug option through command line for sun. Change-Id: Ide22d13c6a39e9a6ade53435c3e1072efd493206 Signed-off-by: Vijayanand Jitta --- qcom/sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 045ed6b9..4e90f290 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -35,7 +35,7 @@ chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops slub_debug=-"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; From 61d2ada8fdb3fde4e64162960ddeb9eeb5529067 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Mon, 14 Oct 2024 14:54:44 +0530 Subject: [PATCH 028/112] ARM: dts: qcom: Add PMIC PON log device for tuna Add a PMIC PON log parser device which reads the log stored in PMK8550 SDAM5 and SDAM6. while at it add a dependency between the gh-watchdog and pmic-pon-log devices for tuna boards. This ensures that during system boot-up, the driver responsible for the gh-watchdog device initializes before the one responsible for the pmic-pon-log device. Change-Id: I5e2c13807570e5a2e1740e9160cce626fa9004c6 Signed-off-by: Kavya Nunna --- qcom/tuna-pmic-overlay.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi index 6fe5a0e0..379dc61b 100644 --- a/qcom/tuna-pmic-overlay.dtsi +++ b/qcom/tuna-pmic-overlay.dtsi @@ -113,6 +113,13 @@ nvmem-cells = <&restart_reason>; nvmem-cell-names = "restart_reason"; }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>; + nvmem-names = "pon_log0", "pon_log1"; + depends-on-supply = <&gh_watchdog>; + }; }; &thermal_zones { From 0e8dcbc9fe73e0c8838ef03b5cea97c3081d3751 Mon Sep 17 00:00:00 2001 From: Minghao Zhang Date: Fri, 27 Sep 2024 10:10:22 +0800 Subject: [PATCH 029/112] dt-bindings: thermal: Document pm8550 compatible for bcl pmic5 This change documents pm8550 compatible for bcl pmic5. Change-Id: Ie3528f91d5ebec8c601ec4fc9bbd8037df824b3c Signed-off-by: Minghao Zhang --- bindings/thermal/qcom-bcl-pmic5.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/bindings/thermal/qcom-bcl-pmic5.yaml b/bindings/thermal/qcom-bcl-pmic5.yaml index a0c67869..5bfb1a83 100644 --- a/bindings/thermal/qcom-bcl-pmic5.yaml +++ b/bindings/thermal/qcom-bcl-pmic5.yaml @@ -23,8 +23,10 @@ description: | properties: compatible: - const: qcom,bcl-v5 description: msm battery state of charge device + items: + - const: qcom,bcl-v5 + - const: qcom,pm8550-bcl-v5 reg: maxItems: 1 @@ -96,3 +98,16 @@ examples: qcom,bcl-mon-vbat-only; qcom,pmic7-threshold; }; + + bcl@4700 { + compatible = "qcom,pm8550-bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>, + <0x1 0x47 0x1 IRQ_TYPE_NONE>, + <0x1 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; From 01b2b643b15cab8a183903a10769ad850afa4bd0 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Mon, 14 Oct 2024 16:44:17 +0530 Subject: [PATCH 030/112] ARM: dts: msm: Add interconnect properties for smmus for kera Enable bus bandwidth voting by adding interconnect properties for kgsl and apps smmu on kera. Change-Id: If660a410212cc6f4ad8e304ba47123bab11e9439 Signed-off-by: Vijayanand Jitta --- qcom/msm-arm-smmu-kera.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi index 36319d07..c3fe3578 100644 --- a/qcom/msm-arm-smmu-kera.dtsi +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -60,6 +60,7 @@ reg = <0x3de8000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <49>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; }; @@ -237,6 +238,7 @@ reg = <0x16f2000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -245,6 +247,7 @@ reg = <0x171b000 0x1000>; qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -253,6 +256,7 @@ reg = <0x17f7000 0x1000>; qcom,stream-id-range = <0x1c00 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -261,6 +265,7 @@ reg = <0x7d3000 0x1000>; qcom,stream-id-range = <0xc00 0x400>; qcom,iova-width = <32>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -269,6 +274,7 @@ reg = <0x7b3000 0x1000>; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <32>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -278,6 +284,7 @@ qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <32>; qcom,num-qtb-ports = <1>; + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; qcom,opt-out-tbu-halting; }; @@ -286,6 +293,7 @@ reg = <0x17b7000 0x1000>; qcom,stream-id-range = <0x1800 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_VIDEO_MVP &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -294,6 +302,7 @@ reg = <0x17f6000 0x1000>; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; + interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; From 1402955d211202c9593a04f35d9e9cacbb1ec39d Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Fri, 11 Oct 2024 16:55:17 +0530 Subject: [PATCH 031/112] ARM: dts: qcom: Add cooling-cells for cpu in monaco Add cooling-cells for the CPU sensors in monaco. Change-Id: I6ef6acac51952effd6de820b6384401feeb610b4 Signed-off-by: Nitesh Kumar --- qcom/monaco.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index bfcaacb2..4a5663f9 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -84,6 +84,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_1: l1-icache { compatible = "cache"; @@ -109,6 +110,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_2: l1-icache { compatible = "cache"; @@ -134,6 +136,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_3: l1-icache { compatible = "cache"; From 8d54d3baa827afcfda0a323876a6cba900dc112d Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Tue, 15 Oct 2024 12:00:44 +0530 Subject: [PATCH 032/112] ARM: dts: msm: Add mem-offline device for tuna Add the device-tree node for the mem-offline driver to enable memory offlining and convey the sizes of the offlineable memory. Describe the communication channel used to communicate with the firmware which supports onlining and offlining of memory. Change-Id: I448969b10b0e29f44ca2b7949472ea21c63ffb3a Signed-off-by: Vijayanand Jitta --- qcom/tuna.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 028f99f5..60ca71d4 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -44,6 +44,13 @@ ddr-regions { }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x0>; + granule = <512>; + qcom,qmp = <&aoss_qmp>; + }; + firmware: firmware { qcom_scm: qcom_scm {}; }; From 42ef810658c6e6621451452bef3896dfe493a288 Mon Sep 17 00:00:00 2001 From: Yingchao Deng Date: Tue, 15 Oct 2024 14:30:18 +0800 Subject: [PATCH 033/112] ARM: dts: msm: Use reserved memory instead of CMA On qcom-6.6, the memory reserved for memory_dump_v2 should be configured as reserved memory instead of CMA. Change-Id: I181b9fc4431838879d3bb99ceafd4512bcf5914e Signed-off-by: Yingchao Deng --- qcom/pineapple-debug.dtsi | 827 +++++++++++++++++++------------------- 1 file changed, 414 insertions(+), 413 deletions(-) diff --git a/qcom/pineapple-debug.dtsi b/qcom/pineapple-debug.dtsi index 7b272c0d..144efbab 100644 --- a/qcom/pineapple-debug.dtsi +++ b/qcom/pineapple-debug.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -10,11 +10,8 @@ #size-cells = <2>; ranges; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; + dump_mem: dump_mem_region { alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; size = <0 0x1800000>; }; }; @@ -4505,414 +4502,418 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; - }; - - c100_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; - - c200_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; - - c300_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; - - c400_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x4>; - }; - - c500_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x5>; - }; - - c600_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x6>; - }; - - c700_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x7>; - }; - - l1_icache0 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x60>; - }; - - l1_icache100 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x61>; - }; - - l1_icache200 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x62>; - }; - - l1_icache300 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x63>; - }; - - l1_icache400 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x64>; - }; - - l1_icache500 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x65>; - }; - - l1_icache600 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x66>; - }; - - l1_icache700 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x67>; - }; - - l1_dcache0 { - qcom,dump-size = <0x12100>; - qcom,dump-id = <0x80>; - }; - - l1_dcache100 { - qcom,dump-size = <0x12100>; - qcom,dump-id = <0x81>; - }; - - l1_dcache200 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x82>; - }; - - l1_dcache300 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x83>; - }; - - l1_dcache400 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x84>; - }; - - l1_dcache500 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x85>; - }; - - l1_dcache600 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x86>; - }; - - l1_dcache700 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x87>; - }; - - l1_itlb700 { - qcom,dump-size = <0x600>; - qcom,dump-id = <0x27>; - }; - - l1_dtlb700 { - qcom,dump-size = <0xa00>; - qcom,dump-id = <0x47>; - }; - - l2_cache0 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc0>; - }; - - l2_cache100 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc1>; - }; - - l2_cache200 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc2>; - }; - - l2_cache300 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc3>; - }; - - l2_cache400 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc4>; - }; - - l2_cache500 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc5>; - }; - - l2_cache600 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc6>; - }; - - l2_cache700 { - qcom,dump-size = <0x340100>; - qcom,dump-id = <0xc7>; - }; - - l2_tlb0 { - qcom,dump-size = <0xf700>; - qcom,dump-id = <0x120>; - }; - - l2_tlb100 { - qcom,dump-size = <0xf700>; - qcom,dump-id = <0x121>; - }; - - l2_tlb700 { - qcom,dump-size = <0xa900>; - qcom,dump-id = <0x127>; - }; - - l1dcdirty0 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x170>; - }; - - l1dcdirty100 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x171>; - }; - - l1dcmte0 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x180>; - }; - - l1dcmte100 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x181>; - }; - - l2dcmte0 { - qcom,dump-size = <0x10100>; - qcom,dump-id = <0x190>; - }; - - l2dcmte100 { - qcom,dump-size = <0x10100>; - qcom,dump-id = <0x191>; - }; - - l0mopca700 { - qcom,dump-size = <0x4100>; - qcom,dump-id = <0x1a7>; - }; - - l2victim700 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x1e7>; - }; - - l2tldtcsp200 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x202>; - }; - - l2tldtcsp300 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x203>; - }; - - l2tldtcsp400 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x204>; - }; - - l2tldtcsp500 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x205>; - }; - - l2tldtcsp600 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x206>; - }; - - l2tldtcmp200 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x212>; - }; - - l2tldtcmp300 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x213>; - }; - - l2tldtcmp400 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x214>; - }; - - l2tldtcmp500 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x215>; - }; - - l2tldtcmp600 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x216>; - }; - - cpuss_reg { - qcom,dump-size = <0x36000>; - qcom,dump-id = <0xef>; - }; - - rpmh { - qcom,dump-size = <0x400000>; - qcom,dump-id = <0xec>; - }; - - rpm_sw { - qcom,dump-size = <0x28000>; - qcom,dump-id = <0xea>; - }; - - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; - - fcm { - qcom,dump-size = <0x8400>; - qcom,dump-id = <0xee>; - }; - - etf_swao { - qcom,dump-size = <0x10000>; - qcom,dump-id = <0xf1>; - }; - - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; - - etfswao_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x102>; - }; - - etr1_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x105>; - }; - - misc_data { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0xe8>; - }; - - etf_slpi { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf3>; - }; - - etfslpi_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x103>; - }; - - etf_lpass { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf4>; - }; - - etflpass_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x104>; - }; - - osm_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x163>; - }; - - pcu_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x164>; - }; - - fsm_data { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x165>; - }; - - spr_cpu0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f0>; - }; - - spr_cpu1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f1>; - }; - - spr_cpu2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f2>; - }; - - spr_cpu3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f3>; - }; - - spr_cpu4 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f4>; - }; - - spr_cpu5 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f5>; - }; - - spr_cpu6 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f6>; - }; - - spr_cpu7 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f7>; - }; - - scandump_smmu { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x220>; - }; - - scandump_gpu { - qcom,dump-size = <0x300000>; - qcom,dump-id = <0x221>; + static_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb700 { + qcom,dump-size = <0x600>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb700 { + qcom,dump-size = <0xa00>; + qcom,dump-id = <0x47>; + }; + + l2_cache0 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc0>; + }; + + l2_cache100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc1>; + }; + + l2_cache200 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc2>; + }; + + l2_cache300 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc3>; + }; + + l2_cache400 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x340100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x121>; + }; + + l2_tlb700 { + qcom,dump-size = <0xa900>; + qcom,dump-id = <0x127>; + }; + + l1dcdirty0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x170>; + }; + + l1dcdirty100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x171>; + }; + + l1dcmte0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x180>; + }; + + l1dcmte100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x181>; + }; + + l2dcmte0 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x190>; + }; + + l2dcmte100 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x191>; + }; + + l0mopca700 { + qcom,dump-size = <0x4100>; + qcom,dump-id = <0x1a7>; + }; + + l2victim700 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x1e7>; + }; + + l2tldtcsp200 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x202>; + }; + + l2tldtcsp300 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x203>; + }; + + l2tldtcsp400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x204>; + }; + + l2tldtcsp500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x205>; + }; + + l2tldtcsp600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x206>; + }; + + l2tldtcmp200 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x212>; + }; + + l2tldtcmp300 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x213>; + }; + + l2tldtcmp400 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x214>; + }; + + l2tldtcmp500 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x215>; + }; + + l2tldtcmp600 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x216>; + }; + + cpuss_reg { + qcom,dump-size = <0x36000>; + qcom,dump-id = <0xef>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; }; }; }; From 1076194f9901742cdf093ebfb33455c320f88b67 Mon Sep 17 00:00:00 2001 From: Sayantan Chakraborty Date: Mon, 14 Oct 2024 11:26:04 +0530 Subject: [PATCH 034/112] ARM: dts: msm: Add CPUCP/SCMI node for Kera Add device nodes for the cpucp mailbox, cpucp logs, and SCMI nodes for Kera. Change-Id: Ia787f5f2b6fd739df0be380946beadef1963a0e9 Signed-off-by: Sayantan Chakraborty --- qcom/kera.dtsi | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 1b2c6bcc..1ccb0038 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1029,6 +1029,60 @@ qcom,firmware-name = "cpusys_vm"; memory-region = <&cpusys_vm_mem>; }; + + mmio_sram: mmio-sram@17D09400 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09400 0x0 0x400>; + ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>; + + cpu_scp_lpri: scmi-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x17D09400 0x0 0x400>; + }; + }; + + cpucp: qcom,cpucp@17400000 { + compatible = "qcom,cpucp"; + reg = <0x17d90000 0x2000>, + <0x17400000 0x10>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_qcom: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@d8140000 { + compatible = "qcom,cpucp-log"; + reg = <0x81200000 0x10000>, <0x81210000 0x10000>; + mboxes = <&cpucp 1>; + }; + + qcom_c1dcvs: qcom,c1dcvs { + compatible = "qcom,c1dcvs-v2"; + }; + + qcom_dynpf: qcom,dynpf { + compatible = "qcom,dynpf"; + }; + + qcom_cpufreq_stats: qcom,cpufreq_stats { + compatible = "qcom,cpufreq-stats-v2"; + }; }; #include "tuna-gdsc.dtsi" From d6f1bceb5c7440444f302eddeb566c7947d9192a Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Tue, 24 Sep 2024 03:51:52 -0700 Subject: [PATCH 035/112] ARM: dts: msm: Add gic-interrupt-router for kera and tuna Add the gic-interrupt-router for kera and tuna. Change-Id: I86164eed35857f93eabe32c1383733a723929920 Signed-off-by: Souradeep Chowdhury Signed-off-by: Mukesh Ojha --- qcom/kera.dtsi | 8 +++++++- qcom/tuna.dtsi | 6 ++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..773b8326 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -31,7 +31,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8"; }; @@ -629,6 +629,12 @@ cap-based-alloc-and-pwr-collapse; }; + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + qcom,gic-class0-cpus = <&CPU0 &CPU1 &CPU2>; + qcom,gic-class1-cpus = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + }; + tcsr: syscon@1fc0000 { compatible = "syscon"; reg = <0x1fc0000 0x30000>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 028f99f5..36201a02 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -650,6 +650,12 @@ cap-based-alloc-and-pwr-collapse; }; + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + }; + apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From f1bff316cc8401207553f781f150988f5b8498bd Mon Sep 17 00:00:00 2001 From: Prasanna S Date: Wed, 16 Oct 2024 11:05:00 +0530 Subject: [PATCH 036/112] ARM: dts: msm: Add spi, i2c, gpi nodes for SVM tuna Adding spi, i2c, gsi nodes for SVM tuna. Change-Id: I3c534c3e68573e34541c5681bea609ac44f28af2 Signed-off-by: Prasanna S --- qcom/tuna-qupv3.dtsi | 22 +++--- qcom/tuna-vm.dtsi | 162 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+), 10 deletions(-) diff --git a/qcom/tuna-qupv3.dtsi b/qcom/tuna-qupv3.dtsi index 8e7e3077..4ad94442 100644 --- a/qcom/tuna-qupv3.dtsi +++ b/qcom/tuna-qupv3.dtsi @@ -47,7 +47,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup1_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -255,8 +256,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; pinctrl-1 = <&qupv3_se4_i2c_sleep>; - dmas = <&gpi_dma1 0 4 3 64 0>, - <&gpi_dma1 1 4 3 64 0>; + dmas = <&gpi_dma1 0 4 3 64 2>, + <&gpi_dma1 1 4 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -279,8 +280,8 @@ pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; pinctrl-1 = <&qupv3_se4_spi_sleep>; - dmas = <&gpi_dma1 0 4 1 64 0>, - <&gpi_dma1 1 4 1 64 0>; + dmas = <&gpi_dma1 0 4 1 64 2>, + <&gpi_dma1 1 4 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; @@ -419,7 +420,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup2_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -749,8 +751,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; pinctrl-1 = <&qupv3_se15_i2c_sleep>; - dmas = <&gpi_dma2 0 7 3 64 0>, - <&gpi_dma2 1 7 3 64 0>; + dmas = <&gpi_dma2 0 7 3 64 2>, + <&gpi_dma2 1 7 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -773,8 +775,8 @@ pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; pinctrl-1 = <&qupv3_se15_spi_sleep>; - dmas = <&gpi_dma2 0 7 1 64 0>, - <&gpi_dma2 1 7 1 64 0>; + dmas = <&gpi_dma2 0 7 1 64 2>, + <&gpi_dma2 1 7 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 2cde4080..0ee42c6d 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -71,6 +71,9 @@ vm-attrs = "context-dump", "crash-restart"; + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>; + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. * QUP1_SE4: GPII5 : IRQ_316 * QUP2_SE7: GPII5 : IRQ_625 @@ -362,6 +365,165 @@ qcom,block-size = <0x400000>; qcom,initial-movable-zone-size = <0x2000000>; }; + + /* + * QUP1 : SE4 - Primary touch + * QUP2 : SE7 - Secondary touch + */ + qup_iommu_group: qup_common_iommu_group { + iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>, + <&qupv3_1 0x00000000 0x00020000>, + <&gpi_dma2 0x00000000 0x00020000>, + <&qupv3_2 0x00000000 0x00020000>; + }; + + /* QUPv3_1 GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Touchscreen I2C Instance */ + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 4 3 64 0xc>, + <&gpi_dma1 1 4 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 4 1 64 0xc>, + <&gpi_dma1 1 4 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + /* QUPv3_2 GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Secondary Tounch */ + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma2 0 7 3 64 0xc>, + <&gpi_dma2 1 7 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Secondary Tounch */ + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma2 0 7 1 64 0xc>, + <&gpi_dma2 1 7 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; }; #include "msm-arm-smmu-tuna-vm.dtsi" From 84e0391a4e61e70570f0ce96845e91a150d0dd23 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Wed, 21 Aug 2024 15:28:20 +0530 Subject: [PATCH 037/112] ARM: dts: msm: Update qcom stats node for Monaco This change updates the qcom stats node with proper compatible string. Also, removes the subsystem-sleep-stats and qcom,rpm-master-stats nodes which are deprecated. Change-Id: I71b653ef539ccc757f4fb79413c539bbdee56d53 Signed-off-by: Raghavendra Kakarla --- qcom/monaco.dtsi | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index bfcaacb2..50eeb7bb 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -1641,24 +1641,11 @@ }; rpm-sleep-stats@4690000 { - /* compatible = "qcom,rpm-sleep-stats"; */ + compatible = "qcom,rpm-stats-v2"; reg = <0x04690000 0x400>; ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; - subsystem-sleep-stats@4690000 { - /* compatible = "qcom,subsystem-sleep-stats-v2"; */ - reg = <0x4690000 0x400>; - }; - - qcom,rpm-master-stats@45f0150 { - /* compatible = "qcom,rpm-master-stats"; */ - reg = <0x45f0150 0x5000>; - qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; - qcom,master-stats-version = <2>; - qcom,master-offset = <4096>; - }; - sdhc1_opp_table: sdhc1-opp-table { compatible = "operating-points-v2"; From 88163abf2ec945882efc7a066100a5d10daafd60 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 16 Oct 2024 15:21:03 +0530 Subject: [PATCH 038/112] ARM: dts: msm: Modify PDC node for kera This change corrects the PDC irq mapping configuration. Change-Id: Ia0fc89d2ac90cf1e5ebf07f28e6ab042202fd41d Signed-off-by: Sneh Mankad --- qcom/kera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..fd1b12e0 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -401,7 +401,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,kera-pdc", "qcom,pdc"; - reg = <0xb220000 0x10000>, <0x17c000f0 0x60>; + reg = <0xb220000 0x10000>, <0x174000f0 0x64>; qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, <10 230 1>, <11 724 1>, <12 716 1>, <13 727 1>, <14 720 1>, <15 726 1>, From aa7d69fbcdac4a9a23f65b9fa3443f1545854a58 Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Fri, 31 May 2024 17:45:39 +0530 Subject: [PATCH 039/112] dt-bindings: interconnect: Add interconnect bindings for KERA Add interconnect device bindings for KERA SoC. These devices can be used to describe any RPMH and NoC based interconnect devices. Change-Id: I757a0dd285190be94f2aafa15daf70218121bb03 Signed-off-by: Raviteja Laggyshetty --- bindings/interconnect/qcom,rpmh.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index 02e1536b..15d8319a 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -198,6 +198,20 @@ properties: - qcom,tuna-nsp_noc - qcom,tuna-pcie_anoc - qcom,tuna-system_noc + - qcom,kera-aggre1_noc + - qcom,kera-aggre2_noc + - qcom,kera-clk_virt + - qcom,kera-cnoc_cfg + - qcom,kera-cnoc_main + - qcom,kera-gem_noc + - qcom,kera-lpass_ag_noc + - qcom,kera-lpass_lpiaon_noc + - qcom,kera-lpass_lpicx_noc + - qcom,kera-mc_virt + - qcom,kera-mmss_noc + - qcom,kera-nsp_noc + - qcom,kera-pcie_anoc + - qcom,kera-system_noc '#interconnect-cells': true From b813022cd551e295565a749e1f039c804793cec0 Mon Sep 17 00:00:00 2001 From: Raghavendra Kakarla Date: Fri, 13 Sep 2024 10:00:41 +0530 Subject: [PATCH 040/112] dt-bindings: Add rpm-stats-v2 dt binding This change adds the rpm-stats-v2 to the rpm-stats dt binding. Change-Id: I02d04d33347ea73ee29f59e0ca5691ecbb5b96fd Signed-off-by: Raghavendra Kakarla --- bindings/soc/qcom/qcom-stats.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/soc/qcom/qcom-stats.yaml b/bindings/soc/qcom/qcom-stats.yaml index 64948af2..61c21ff3 100644 --- a/bindings/soc/qcom/qcom-stats.yaml +++ b/bindings/soc/qcom/qcom-stats.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. (QTI) Stats bindings +title: Qualcomm Technologies, Inc. SoC LPM stats maintainers: - Maulik Shah @@ -25,6 +25,7 @@ properties: - qcom,rpmh-stats-v4 - qcom,sdm845-rpmh-stats - qcom,rpm-stats + - qcom,rpm-stats-v2 # For older RPM firmware versions with fixed offset for the sleep stats - qcom,apq8084-rpm-stats - qcom,msm8226-rpm-stats From dc5d86c9d333e3ff045c5d3ca594230d6ce3591f Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 16 Oct 2024 16:26:42 +0530 Subject: [PATCH 041/112] ARM: dts: msm: Update subsystem stats node for tuna This change updates subsystem stats node according to latest version. Change-Id: I638652beb177156d73fd1608f69d956b54b75cae Signed-off-by: Sneh Mankad --- qcom/tuna.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1a106540..463deb09 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1544,7 +1544,7 @@ sram@c3f0000 { compatible = "qcom,rpmh-stats-v4"; - reg = <0x0c3f0000 0x3ff>; + reg = <0x0c3f0000 0x400>; qcom,qmp = <&aoss_qmp>; ss-name = "modem", "wpss", "adsp", "adsp_island", "cdsp", "apss"; From 63a7ad9b5397391b3052f82652172e0de45ba444 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 16 Oct 2024 16:35:24 +0530 Subject: [PATCH 042/112] bindings: arm: msm: Document sys-pm-violators compatible for kera Document sys-pm-violators compatible for kera. Change-Id: I86fe8ca8e49bf7f8e8e78983f74e58eb838ad6d2 Signed-off-by: Sneh Mankad --- bindings/arm/msm/sys-pm-violators.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/arm/msm/sys-pm-violators.yaml b/bindings/arm/msm/sys-pm-violators.yaml index a498fea3..3883054a 100644 --- a/bindings/arm/msm/sys-pm-violators.yaml +++ b/bindings/arm/msm/sys-pm-violators.yaml @@ -27,6 +27,7 @@ properties: - qcom,sys-pm-monaco-auto - qcom,sys-pm-sun - qcom,sys-pm-tuna + - qcom,sys-pm-kera reg: maxItems: 1 @@ -50,6 +51,7 @@ allOf: enum: - qcom,sys-pm-sun - qcom,sys-pm-tuna + - qcom,sys-pm-kera - qcom,sys-pm-pineapple - qcom,sys-pm-parrot - qcom,sys-pm-ravelin From b89277fa9f978eb4e3072912ba9502bf2c0ad1bb Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 16 Oct 2024 16:37:11 +0530 Subject: [PATCH 043/112] ARM: dts: msm: Add stats and sys-pm-vx nodes for kera Add qcom sleep stats, rpmh stats nodes to enable cpu and soc stats. Also add sys-pm-vx node. Change-Id: If29d34169b2adeab6843d010325f59787727f999 Signed-off-by: Sneh Mankad --- qcom/kera.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..80a0102a 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -549,6 +549,12 @@ qcom,smem-state-names = "stop"; }; + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kera"; + reg = <0xc320000 0x400>; + qcom,qmp = <&aoss_qmp>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,kera-tlmm"; reg = <0xf000000 0x1000000>; @@ -980,6 +986,28 @@ #reset-cells = <1>; }; + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x178b0098 0x4>, + <0x178c0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v4"; + reg = <0x0c3f0000 0x400>; + qcom,qmp = <&aoss_qmp>; + ss-name = "modem", "wpss", "adsp", "adsp_island", + "cdsp", "apss"; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,dummycc"; clock-output-names = "camcc_clocks"; From 167166ab429dcaf632cece3e82f6566f761b6c0c Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 16 Sep 2024 17:45:11 +0530 Subject: [PATCH 044/112] ARM: dts: msm: Add medium cluster to perf core Currently cpufreq delayed work is queued with delayed timer as 30ms. On expiry, we monitor load and then enable storage boost feature if load exceeds certain predefined threshold. Unlike pineapple, we are monitoring the load request only on prime/large cluster and not on medium cluster. This is causing some additional delay to reach the threshold required to enable storage boost feature. Benchmark tools like Antutu completes read or write IO within 120-130ms which mean any small delay can impact Antutu to large extent. Hence add medium clusters to perf score similar to pineapple so that load on medium cluster along with large cluster is considered. This will decrease the window time to reach the threshold to start the storage boost and hence improve Storage benchmark performance. Change-Id: I8563cffc4da8fa7729d38fc71c8996b20b79b1ec Signed-off-by: Nitin Rawat --- qcom/sun.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 045ed6b9..7a8ea877 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2498,6 +2498,7 @@ qos1 { mask = <0x3f>; vote = <44>; + perf; /* Set CPU0 to fmax, and CPU[0-5] will run at fmax */ cpu_freq_vote = <0>; }; From ecf75bb5d7cc8ecd5cf36ef658d3fab05cba3ca4 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 16 Oct 2024 20:53:39 +0530 Subject: [PATCH 045/112] ARM: dts: msm: Add qfprom node for kera and tuna Add qfprom node for kera and tuna. Change-Id: I2fc32aebc58b6793cb9be896b4dd1dc8734a05a8 Signed-off-by: Souradeep Chowdhury --- qcom/kera.dtsi | 9 +++++++++ qcom/tuna.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..63f28f23 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -906,6 +906,15 @@ #size-cells = <1>; read-only; ranges; + feat_conf6: feat_conf6@0118 { + reg = <0x0118 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf6>; + nvmem-cell-names = "feat_conf6"; }; clocks { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1a106540..a0552593 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1460,6 +1460,15 @@ #size-cells = <1>; read-only; ranges; + feat_conf6: feat_conf6@0118 { + reg = <0x0118 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf6>; + nvmem-cell-names = "feat_conf6"; }; clocks { From d3c5fd0500fec42644d85c51200cffff76fe5d4b Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 13 Aug 2024 15:50:28 +0530 Subject: [PATCH 046/112] ARM: dts: msm: add primary SPMI Arbiter and SPMI debug bus for kera boards Add spmi-pmic-arb devices for the primary and secondary SPMI buses found on kera. The primary bus operates at 19.2 MHz and is used for most of the PMICs. The secondary bus operates at 4.8 MHz and is used exclusively for charging PMICs. Note that the secondary bus is not used so it is kept disabled. Add SPMI debug device and associated child devices for the primary SPMI interface. This provides consumers with unrestricted access to the PMIC registers on pre-production devices. This helps make debugging easier. Change-Id: Idbb39999b00dd296419eb570b30083e208cf2bce Signed-off-by: Kavya Nunna --- qcom/kera.dtsi | 139 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index caf61737..3665d86b 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Kera"; @@ -1189,6 +1190,144 @@ qcom_cpufreq_stats: qcom,cpufreq_stats { compatible = "qcom,cpufreq-stats-v2"; }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi1_bus: qcom,spmi@c432000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc432000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4d0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <1>; + depends-on-supply = <&spmi0_bus>; + status = "disabled"; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + pmk8550@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmxr2230@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmd802x@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmr735d@a { + compatible = "qcom,spmi-pmic"; + reg = <10 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@d { + compatible = "qcom,spmi-pmic"; + reg = <13 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + thermal_zones: thermal-zones { + }; + }; #include "tuna-gdsc.dtsi" From 23ea0a9998553ce59acf0fb8ef54880365e0ab33 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Tue, 8 Oct 2024 20:28:38 +0530 Subject: [PATCH 047/112] ARM: dts: qcom: add support for wcd usbss i2c slave on tuna add support for wcd_usbss i2c slave and sdam interrupt registration. Change-Id: I03369812d52781c96a86922eb92a930da08f7833 Signed-off-by: Prasad Kumpatla --- qcom/tuna-qrd.dtsi | 9 +++++++++ qcom/tuna.dtsi | 11 ++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index 86cea255..a5251301 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -4,6 +4,7 @@ */ #include #include +#include &qupv3_se4_spi { #address-cells = <1>; @@ -89,6 +90,14 @@ status = "ok"; }; +&wcd_usbss { + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_wcd"; + nvmem-cells = <&usb_mode>; + nvmem-cell-names = "usb_mode"; +}; + &sdhc_2 { vdd-supply = <&L13B>; qcom,vdd-voltage-level = <2960000 2960000>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 028f99f5..6c9ad3d8 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -48,7 +48,7 @@ qcom_scm: qcom_scm {}; }; - aliases { + aliases: aliases { serial0 = &qupv3_se7_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ @@ -3179,3 +3179,12 @@ &qupv3_se7_2uart { status = "ok"; }; + +&qupv3_se3_i2c { + status = "ok"; + wcd_usbss: wcd939x_i2c@e { + compatible = "qcom,wcd939x-i2c"; + reg = <0xe>; + vdd-usb-cp-supply = <&L7B>; + }; +}; From e72923880954e59ab4c732a253e334d0fca63b1e Mon Sep 17 00:00:00 2001 From: Prem Sai Grandhi Date: Tue, 15 Oct 2024 17:38:32 +0530 Subject: [PATCH 048/112] ARM: dts: msm: Add llcc perfmon node for tuna SOC Add llcc perfmon entry, qdss clock node to llcc perfmon driver and aoss_qmp headers. Change-Id: I8f3b823f754bcf505c8441820cddfa03b5782305 Signed-off-by: Prem Sai Grandhi --- qcom/tuna.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 217a3488..9bae067a 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -20,6 +20,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -648,6 +650,12 @@ interrupts = ; cap-based-alloc-and-pwr-collapse; + + llcc_perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; }; gic-interrupt-router { From 8892bda7c1acb502c07dca316d33c57a4d04e167 Mon Sep 17 00:00:00 2001 From: Khaja Hussain Shaik Khaji Date: Thu, 17 Oct 2024 18:53:46 +0530 Subject: [PATCH 049/112] ARM: dts: msm: Correct imem child bus address map Change imem node ranges to map imem address space to the child node's address space correctly. Change-Id: Ic4ec5cbf233011f48341b7c2788e1cf983a2dc7b Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdxkova.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 1d253345..831f79ad 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1325,7 +1325,7 @@ qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x0 0x14680000 0x0 0x1000>; - ranges = <0x0 0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x14680000 0x0 0x1000>; #address-cells = <2>; #size-cells = <2>; From cdd788bd9e96a4a63b0a6a712580ff42dc98eb2f Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 14 Oct 2024 19:19:20 +0530 Subject: [PATCH 050/112] ARM: dts: msm: Add initial devicetree for Kera VM Add initial devicetree files for trustedvm for RUMI platform on Kera SoC. Change-Id: I8028e413de1935d8363edc49a13bf7a722432892 Signed-off-by: Hrishabh Rajput --- qcom/Makefile | 7 ++ qcom/kera-vm-rumi.dts | 15 +++ qcom/kera-vm-rumi.dtsi | 8 ++ qcom/kera-vm.dtsi | 246 +++++++++++++++++++++++++++++++++++++++++ qcom/platform_map.bzl | 8 +- 5 files changed, 283 insertions(+), 1 deletion(-) create mode 100644 qcom/kera-vm-rumi.dts create mode 100644 qcom/kera-vm-rumi.dtsi create mode 100644 qcom/kera-vm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 3f8b30be..238d5ca7 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -235,6 +235,13 @@ dtb-y += $(tuna_tuivm-dtb-y) endif endif +ifeq ($(CONFIG_ARCH_KERA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb +dtb-y += $(kera_tuivm-dtb-y) +endif +endif + MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ diff --git a/qcom/kera-vm-rumi.dts b/qcom/kera-vm-rumi.dts new file mode 100644 index 00000000..6c653ef1 --- /dev/null +++ b/qcom/kera-vm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/kera-vm-rumi.dtsi b/qcom/kera-vm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/kera-vm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi new file mode 100644 index 00000000..a40e16dc --- /dev/null +++ b/qcom/kera-vm.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <659 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;"; + qcom,secdomain-ids = <45>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/trusted-ui"; + vm-guid = "598085da-c516-5b25-a9c1-927a02819770"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. + * QUP1_SE4: GPII5 : IRQ_316 + * QUP2_SE7: GPII5 : IRQ_625 + */ + gic-irq-ranges = <316 316 + 625 625 /* PVM->SVM IRQ transfer */ + 279 279>; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x0 0x0>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x11>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xDA6F8000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x10>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xDA6FC000>; + }; + }; + + virtio-mmio@2 { + vdevice-type = "virtio-mmio"; + patch = "/soc/virtio-mmio"; + peer-default; + vqs-num = <0x3>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x15>; //for virtio-vsock + #address-cells = <0x2>; + base = <0x0 0xDA700000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x14000>; + memory { + qcom,label = <0x12>; + #address-cells = <0x2>; + base = <0x0 0xDA70c000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: qcom_scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + virtio-mmio { + wakeup-source; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <64>; + qcom,support-hypervisor; + }; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 74b784bc..f47b15e6 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -142,7 +142,7 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], - "binary_compatible_with": ["tuna-tuivm"], + "binary_compatible_with": ["tuna-tuivm", "kera-tuivm"], }, "sun-oemvm": { "dtb_list": [ @@ -210,6 +210,12 @@ _platform_map = { {"name": "tuna-vm-rumi.dtb"}, ], }, + "kera-tuivm": { + "dtb_list": [ + # keep sorted + {"name": "kera-vm-rumi.dtb"}, + ], + }, "pineapple": { "dtb_list": [ {"name": "pineapple.dtb"}, From 3a5024df85492ae09c99cce1d2590e0c7546964a Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Mon, 14 Oct 2024 19:40:00 +0530 Subject: [PATCH 051/112] ARM: dts: msm: Add initial devicetree for Kera OEMVM Add initial devicetree files for OEMVM for RUMI platform on Kera SoC. Change-Id: I92019de68818c03dce6c93bba96902b071bb5785 Signed-off-by: Hrishabh Rajput --- qcom/Makefile | 3 +- qcom/kera-oemvm-rumi.dts | 15 +++ qcom/kera-oemvm-rumi.dtsi | 8 ++ qcom/kera-oemvm.dtsi | 218 ++++++++++++++++++++++++++++++++++++++ qcom/platform_map.bzl | 10 +- 5 files changed, 252 insertions(+), 2 deletions(-) create mode 100644 qcom/kera-oemvm-rumi.dts create mode 100644 qcom/kera-oemvm-rumi.dtsi create mode 100644 qcom/kera-oemvm.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 238d5ca7..bb164de8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -237,7 +237,8 @@ endif ifeq ($(CONFIG_ARCH_KERA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) -kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb +kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb \ + kera-oemvm-rumi.dtb dtb-y += $(kera_tuivm-dtb-y) endif endif diff --git a/qcom/kera-oemvm-rumi.dts b/qcom/kera-oemvm-rumi.dts new file mode 100644 index 00000000..8d4a30b6 --- /dev/null +++ b/qcom/kera-oemvm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/kera-oemvm-rumi.dtsi b/qcom/kera-oemvm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/kera-oemvm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/kera-oemvm.dtsi b/qcom/kera-oemvm.dtsi new file mode 100644 index 00000000..cd6f0bf4 --- /dev/null +++ b/qcom/kera-oemvm.dtsi @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <659 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,oemvm"; + qcom,pasid = <0x0 0x22>; + qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;"; + qcom,secdomain-ids = <49>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/oemvm"; + vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x0 0x0>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x16>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xFFEFC000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x13>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xFFF00000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x14>; + #address-cells = <0x2>; + base = <0x0 0xFFF04000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <512>; + qcom,support-hypervisor; + }; +}; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index f47b15e6..a7f9db89 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -162,7 +162,7 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], - "binary_compatible_with": ["tuna-oemvm"], + "binary_compatible_with": ["tuna-oemvm", "kera-oemvm"], }, "tuna-tuivm": { "dtb_list": [ @@ -213,6 +213,14 @@ _platform_map = { "kera-tuivm": { "dtb_list": [ # keep sorted + {"name": "kera-oemvm-rumi.dtb"}, + {"name": "kera-vm-rumi.dtb"}, + ], + }, + "kera-oemvm": { + "dtb_list": [ + # keep sorted + {"name": "kera-oemvm-rumi.dtb"}, {"name": "kera-vm-rumi.dtb"}, ], }, From 0273c1dd4c60853dade74f2e2d168f1c807d819d Mon Sep 17 00:00:00 2001 From: Sumadhura Kalyan Singamchetti Date: Wed, 16 Oct 2024 17:34:41 +0530 Subject: [PATCH 052/112] ARM: dts: msm: Update touch tlmm for parrot vm Update touch tlmm for parrot vm. Change-Id: Ibea4d9cc5dd415d750eec9c1b0e18ad13a491406 Signed-off-by: Sumadhura Kalyan Singamchetti --- qcom/parrot-pinctrl.dtsi | 3 ++- qcom/parrot-qrd.dtsi | 9 ++++++++- qcom/parrot-vm-qrd.dtsi | 22 ++++++++++++++++++++++ qcom/parrot-vm.dtsi | 5 +++-- 4 files changed, 35 insertions(+), 4 deletions(-) diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi index b314a02f..7d9220df 100644 --- a/qcom/parrot-pinctrl.dtsi +++ b/qcom/parrot-pinctrl.dtsi @@ -1893,7 +1893,8 @@ tuivm { qcom,label = <0x08>; qcom,vmid = <45>; - tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; }; }; }; diff --git a/qcom/parrot-qrd.dtsi b/qcom/parrot-qrd.dtsi index c537398e..aa7b33d2 100644 --- a/qcom/parrot-qrd.dtsi +++ b/qcom/parrot-qrd.dtsi @@ -159,6 +159,13 @@ goodix,touch-type = "primary"; goodix,qts_en; - qcom,touch-environment = "pvm"; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <595>; + qts,trusted-touch-io-bases = <0xa8c000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 + &tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>; }; }; diff --git a/qcom/parrot-vm-qrd.dtsi b/qcom/parrot-vm-qrd.dtsi index 1510613d..a6f2eb6a 100644 --- a/qcom/parrot-vm-qrd.dtsi +++ b/qcom/parrot-vm-qrd.dtsi @@ -5,3 +5,25 @@ &soc { }; + +&qupv3_se9_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <595>; + qts,trusted-touch-io-bases = <0xa8c000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>; + }; +}; diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 5ec070cb..5374ca14 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -55,11 +55,12 @@ tlmm: pinctrl@f000000 { compatible = "qcom,parrot-vm-tlmm"; - gpios = /bits/ 16 <98 99>; + gpios = /bits/ 16 <98 99 10 11 12 13 64 65>; }; tlmm-vm-mem-access { - tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; }; apps-smmu@15000000 { From 9d441e95f5b774bd4aa71eca8fdf235dbc344b94 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Fri, 18 Oct 2024 16:10:14 +0530 Subject: [PATCH 053/112] ARM: dts: msm: Add mem-buf device for kera The mem-buf device provides memory related services for shared memory between host and guest VMs. Change-Id: Ib29a426101ef274106b71ef613ca83f1577cf142 Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index f6eeb5b9..bbb1e381 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -351,6 +351,16 @@ qcom,vmid-cp-camera-preview-ro; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; From 694b80d9da05168f80d14175665a8b5d67514aa7 Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Fri, 18 Oct 2024 16:11:41 +0530 Subject: [PATCH 054/112] ARM: dts: msm: Add mem-offline device for kera Add the device-tree node for the mem-offline driver to enable memory offlining and convey the sizes of the offlineable memory. Describe the communication channel used to communicate with the firmware which supports onlining and offlining of memory. Change-Id: I6c7868545fe7601d3cc2c6d5ea95c980046c52b4 Signed-off-by: Vijayanand Jitta --- qcom/kera.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bbb1e381..be77c747 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -39,6 +39,13 @@ ddr-regions { }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x0>; + granule = <512>; + qcom,qmp = <&aoss_qmp>; + }; + firmware: firmware { qcom_scm: qcom_scm { }; }; From d7d25e4f4ab4ce628ca911dcb371d2445d7eb6d3 Mon Sep 17 00:00:00 2001 From: Khaja Hussain Shaik Khaji Date: Fri, 18 Oct 2024 18:32:57 +0530 Subject: [PATCH 055/112] ARM: dts: msm: add Modem DSM region info to IMEM IMEM gets updated with Modem DSM memory region info when Modem taken out of reset by APPS and the info is used for collection of coredumps. Change-Id: If549119c1516f8a995978c419fcb74b3d3e3ed9d Signed-off-by: Khaja Hussain Shaik Khaji --- qcom/sdxkova.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 831f79ad..4f0c8227 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1368,6 +1368,11 @@ compatible = "qcom,msm-imem-diag-dload"; reg = <0x0 0xc8 0x0 0xc8>; }; + + modem_dsm@c98 { + compatible = "qcom,msm-imem-mss-dsm"; + reg = <0x0 0xc98 0x0 0x10>; + }; }; tcsr_mutex_block: syscon@1f40000 { From d7325aaa00d56d3dd0e7b8d4f8ba4fed72bc32cb Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Fri, 18 Oct 2024 17:39:27 +0530 Subject: [PATCH 056/112] ARM: dts: msm: Override adsp firmware names for Tuna7 ADSP will use distinct firmware BINs for Tuna and Tuna7. Remoteproc driver reads the firmware-name from adsp dt node and loads the corrosponding adsp firmware. Override the firmware-name for ADSP in Tuna7 dtsi file to load the correct firmware for Tuna7. Change-Id: I914d9ff400688826196f2e9e205e728da3894c45 Signed-off-by: Shivendra Pratap --- qcom/tuna7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/tuna7.dtsi b/qcom/tuna7.dtsi index 769de07c..38eb356c 100644 --- a/qcom/tuna7.dtsi +++ b/qcom/tuna7.dtsi @@ -8,4 +8,9 @@ model = "Qualcomm Technologies, Inc. Tuna 7"; compatible = "qcom,tuna"; qcom,msm-id = <681 0x10000>; + +}; + +&adsp_pas { + firmware-name = "adsp2.mdt", "adsp2_dtb.mdt"; }; From 98d4c76e70d29cb938b7c253b6cf8bcd5a3f3eb2 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Fri, 18 Oct 2024 18:54:01 +0530 Subject: [PATCH 057/112] ARM: dts: msm: Cleanup parrot and ravelin devicetree Cleanup parrot and ravelin devicetree. Change-Id: Ib33b78a825fb481017be90d23c8066f2977b82a5 Signed-off-by: Saranya R --- qcom/parrot-4gb.dtsi | 8 +------- qcom/ravelin-low-memory.dtsi | 6 +----- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/qcom/parrot-4gb.dtsi b/qcom/parrot-4gb.dtsi index cea98f38..a82237e1 100644 --- a/qcom/parrot-4gb.dtsi +++ b/qcom/parrot-4gb.dtsi @@ -36,17 +36,11 @@ }; &soc { - - qcom,guestvm_loader@e0b00000 { + gh-secure-vm-loader@0 { status = "disabled"; }; qrtr-gunyah { status = "disabled"; }; - - qcom,virtio_backend@0 { - status = "disabled"; - }; - }; diff --git a/qcom/ravelin-low-memory.dtsi b/qcom/ravelin-low-memory.dtsi index 201d98f4..c3f8e9f7 100644 --- a/qcom/ravelin-low-memory.dtsi +++ b/qcom/ravelin-low-memory.dtsi @@ -28,15 +28,11 @@ }; &soc { - qcom,guestvm_loader@e0b00000 { + gh-secure-vm-loader@0 { status = "disabled"; }; qrtr-gunyah { status = "disabled"; }; - - qcom,virtio_backend@0 { - status = "disabled"; - }; }; From 98a422d702afe2198584d7cd1d8e4a430fb07ea6 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Sat, 19 Oct 2024 09:27:13 +0530 Subject: [PATCH 058/112] ARM: dts: msm: Added CPUIdle and PSCI devices for kera Added idle states for CPUs and CPU clusters, and PSCI device to enable CPUs to enter deeper LPMs. Disabled the idle states till Rumi validations are done. Additionally. updated APPS RSC device to be in cluster power domain to handle RSC activities when cluster is powering off. Change-Id: Ic41e219c5c4dabe29f9ac787010ea09c5c123534 Signed-off-by: Sneh Mankad --- qcom/kera-rumi.dtsi | 36 ++++++++ qcom/kera.dtsi | 195 ++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 215 insertions(+), 16 deletions(-) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index d3592d6b..b55b7c92 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -42,3 +42,39 @@ maximum-speed = "high-speed"; }; }; + +&SILVER_OFF { + status = "disabled"; +}; + +&SILVER_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_OFF { + status = "disabled"; +}; + +&GOLD_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_RAIL_OFF { + status = "disabled"; +}; + +&CLUSTER_PWR_DN { + status = "disabled"; +}; + +&CX_RET { + status = "disabled"; +}; + +&APSS_OFF { + status = "disabled"; +}; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..c777e9ce 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -55,8 +55,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -74,8 +76,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; }; @@ -83,8 +87,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "cache"; @@ -97,8 +103,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "cache"; @@ -111,8 +119,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "cache"; @@ -125,8 +135,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "cache"; @@ -139,8 +151,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "cache"; @@ -153,8 +167,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "cache"; @@ -204,6 +220,97 @@ }; }; + idle-states { + entry-method = "psci"; + + SILVER_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <250>; + exit-latency-us = <900>; + min-residency-us = <3200>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_RAIL_OFF: silver-cluster0-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF: gold-cluster1-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_PLUS_OFF: gold-plus-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <450>; + exit-latency-us = <1200>; + min-residency-us = <6230>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41001344>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + arm,psci-suspend-param = <0x4100b344>; + }; + }; + soc: soc { }; hypervisor: hypervisor { @@ -267,6 +374,56 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -362,6 +519,7 @@ interrupts = , , ; + power-domains = <&CLUSTER_PD>; apps_rsc_drv2: drv@2 { qcom,drv-id = <2>; @@ -549,6 +707,11 @@ qcom,smem-state-names = "stop"; }; + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,kera-tlmm"; reg = <0xf000000 0x1000000>; From f96418d810e0a91228498d968560379064b6accf Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Wed, 16 Oct 2024 17:33:26 +0530 Subject: [PATCH 059/112] ARM: dts: msm: Enable tri-led node for Ravelin Add compatible string to led DT node for Ravelin. This was removed from the bulk DT porting for Ravelin on qcom-6.6 device-tree branch. Also, the pwm driver probe fails when the "qcom,num-lpg-channels" value is higher than the number of configured channels in the dtsi for the pwm node. This is because the driver uses the lpg_sdam_base for every channel during probe and fails if not configured correctly in the dtsi. So, change the num-lpg-channels to 3 since only 3 channels are configured and used. Change-Id: I9dbe8a2bf97316fad69ff6a5f9db42a19b839901 Signed-off-by: Shilpa Suresh --- qcom/pmi632.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index ab5b1805..1d470d30 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -199,7 +199,7 @@ reg = <0xb300>; reg-names = "lpg-base"; #pwm-cells = <2>; - qcom,num-lpg-channels = <5>; + qcom,num-lpg-channels = <3>; nvmem-names = "ppg_sdam"; nvmem = <&pmi632_sdam7>; qcom,pbs-client = <&pmi632_pbs_client3>; @@ -235,6 +235,7 @@ }; pmi632_rgb: qcom,leds@d000 { + compatible = "qcom,tri-led"; reg = <0xd000>; red { label = "red"; From 99cac882c15fa00b280d08e17d5d1d33ee50020b Mon Sep 17 00:00:00 2001 From: Kartikey Arora Date: Tue, 15 Oct 2024 20:33:55 +0530 Subject: [PATCH 060/112] ARM: dts: msm: Add wpss rproc node for kera Add wpss rproc node for kera. Change-Id: Id61d12a4c4d5d346e8e06cc88997ef1342f24925 CRs-Fixed: 3954263 Signed-off-by: Kartikey Arora --- bindings/remoteproc/qcom,adsp.yaml | 1 + qcom/kera.dtsi | 40 ++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index e5b00374..191ee125 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -79,6 +79,7 @@ properties: - qcom,monaco-modem-pas - qcom,monaco-adsp-pas - qcom,tuna-wpss-pas + - qcom,kera-wpss-pas reg: maxItems: 1 diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..762c42d7 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -908,6 +908,46 @@ ranges; }; + wpss_pas: remoteproc-wpss@a3500000 { + compatible = "qcom,kera-wpss-pas"; + reg = <0xa3500000 0x10000>; + status = "ok"; + + memory-region = <&wpss_mem>; + + firmware-name = "qca6750/wpss.mdt"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From eae1f4e7d5b5ce951e9468270b72ce70bce68845 Mon Sep 17 00:00:00 2001 From: Rakesh Kundaram Date: Mon, 21 Oct 2024 10:31:38 +0530 Subject: [PATCH 061/112] ARM: dts: msm: Add sleepmon dtsi changes tuna and kera Add adsp sleepmon driver dtsi chagnes for tuna and kera. Change-Id: Iea7bd40bcfbed3167a298e1795816aa75aa4f348 Signed-off-by: Rakesh Kundaram --- qcom/kera.dtsi | 5 +++++ qcom/tuna.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index bfa5172a..e77a4a45 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -426,6 +426,11 @@ interrupt-controller; }; + adsp_sleepmon: adsp-sleepmon { + compatible = "qcom,adsp-sleepmon"; + qcom,rproc-handle = <&adsp_pas>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,kera-adsp-pas"; reg = <0x03000000 0x10000>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 217a3488..1fc4bd83 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -842,6 +842,11 @@ interrupt-controller; }; + adsp_sleepmon: adsp-sleepmon { + compatible = "qcom,adsp-sleepmon"; + qcom,rproc-handle = <&adsp_pas>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,tuna-adsp-pas"; reg = <0x03000000 0x10000>; From 85baae8710353d299f36dc53bffddb6c909fe46d Mon Sep 17 00:00:00 2001 From: Saranya R Date: Mon, 21 Oct 2024 11:27:39 +0530 Subject: [PATCH 062/112] ARM: dts: qcom: Add few nodes to optimize bootup time Add dsi_pll_codes and disp_rdump_region nodes in the beginning of devicetree to optimize the bootloader search for these nodes during bootup which reduces bootup time. Change-Id: I18a85629b8a20980c07a09a74f1b0da0f41fb1f3 Signed-off-by: Saranya R --- qcom/ravelin.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 32b8915b..fac08707 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -459,6 +459,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + dsi_pll_codes { + }; + + disp_rdump_region@e1000000 { + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 57d974a17610aad69811c6ba4401024eb8ea65bc Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 17 Jun 2024 16:03:10 +0530 Subject: [PATCH 063/112] ARM: dts: msm: Add support for GCC and TCSRCC on Kera Add support for GCC and TCSRCC on Kera platform. While at it, move the corresponding GDSC's to real. Change-Id: I1ecf7e1ec14afc71a9fc228c636668d9052ba14b Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 44 ++++++++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 9dcb25d5..f4f395d9 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1132,8 +1132,27 @@ }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,kera-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "sleep_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1146,8 +1165,9 @@ }; tcsrcc: clock-controller@1f40000 { - compatible = "qcom,dummycc"; - clock-output-names = "tcsrcc_clocks"; + compatible = "qcom,kera-tcsrcc", "syscon"; + reg = <0x1fbf000 0x20>; + reg-name = "cc_base"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1366,42 +1386,42 @@ }; &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_0_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_pcie_1_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_1_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_mem_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb3_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; From cbf54b8fbf9db94a8c013dd636f02c58feba0f49 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 23 Jul 2024 16:20:08 +0530 Subject: [PATCH 064/112] dt-bindings: clock: qcom: add GPU clock controller bindings on kera Add GPU clock controller bindings on kera device. Change-Id: I64ce64a93077f9699a559e76865fa09d571a4f36 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,gpucc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index ccdb4c98..2411e3c0 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -27,6 +27,7 @@ description: | dt-bindings/clock/qcom,gpucc-parrot.h dt-bindings/clock/qcom,gpucc-monaco.h dt-bindings/clock/qcom,gpucc-tuna.h + dt-bindings/clock/qcom,gpucc-kera.h properties: compatible: @@ -45,6 +46,7 @@ properties: - qcom,parrot-gpucc - qcom,monaco-gpucc - qcom,tuna-gpucc + - qcom,kera-gpucc clocks: items: From 7e9f80bdf3ade836b484acae12c4928496649523 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Mon, 21 Oct 2024 11:48:27 +0530 Subject: [PATCH 065/112] ARM: dts: msm: Adding SMMU Proxy for Tuna Adding smmu-proxy driver entries for Tuna. Change-Id: Iecc1d56757c9ec0c486c2612aa2a2ae24be9312d Signed-off-by: Ravi Kumar Bokka --- qcom/tuna-vm.dtsi | 33 +++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 4 ++++ 2 files changed, 37 insertions(+) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index ae2af360..19fda190 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { #address-cells = <0x2>; @@ -343,6 +344,38 @@ qcom,support-hypervisor; }; + qti,smmu-proxy { + compatible = "smmu-proxy-receiver"; + }; + + qti,smmu-proxy-camera-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + iommus = <&apps_smmu 0x1810 0x20>, + <&apps_smmu 0x1C10 0x0>, + <&apps_smmu 0x18F0 0x0>; + dma-coherent; + }; + + qti,smmu-proxy-display-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + iommus = <&apps_smmu 0x801 0x0>; + dma-coherent; + }; + + qti,smmu-proxy-eva-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00000000 0xffffffff>; + iommus = <&apps_smmu 0x1927 0x0>; + dma-coherent; + }; + qcom,mem-buf { compatible = "qcom,mem-buf"; qcom,mem-buf-capabilities = "consumer"; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 6a96d53e..468807f5 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1878,6 +1878,10 @@ clock-frequency = <32768>; }; + qti,smmu-proxy { + compatible = "smmu-proxy-sender"; + }; + clk_virt: interconnect@0 { compatible = "qcom,tuna-clk_virt"; #interconnect-cells = <1>; From 8aa06421222e1040022bdd330806ccd9c712d8d4 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Fri, 28 Jun 2024 17:54:22 +0530 Subject: [PATCH 066/112] ARM: dts: msm: Add support for VIDEO clock controller on KERA Add support for VIDEO clock controller and move corresponding gdsc's from dummy to real on Kera platform. Change-Id: I830ceb12fb979613401859313518d9e4de67e674 Signed-off-by: Anaadi Mishra --- qcom/kera.dtsi | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index f4f395d9..623e878f 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1173,8 +1173,19 @@ }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,tuna-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_CX_LEVEL>; + vdd_mxc-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1441,12 +1452,15 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &video_cc_mvs0c_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; From c24d51903ae22cc8c873902cbdff658f3b2371bf Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Mon, 23 Sep 2024 16:39:56 +0530 Subject: [PATCH 067/112] dt-bindings: clock: qcom: add debugcc bindings for Kera Add debug clock controller bindings for Kera platform. Change-Id: I8a15eeaaf5a20ec4a7c11629fea2ee51d0478c6e Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,debugcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1a7c7670..63a2918d 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -23,6 +23,7 @@ properties: - qcom,sm4450-debugcc - qcom,monaco-debugcc - qcom,tuna-debugcc + - qcom,kera-debugcc clocks: items: From 195658105fca58815fe4e21b204ec0d3f249b848 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 19 Sep 2024 04:43:09 +0530 Subject: [PATCH 068/112] dt-bindings: clock: Add gx_clkctl bindings for TUNA Add gx_clkctl bindings for tuna device. Change-Id: Ib6e4eb7d11eb6fcf23ebccc13e0f8b33f92522b1 Signed-off-by: Anaadi Mishra --- bindings/clock/qcom,gx_clkctl.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bindings/clock/qcom,gx_clkctl.yaml b/bindings/clock/qcom,gx_clkctl.yaml index 0790d60d..c5964e57 100644 --- a/bindings/clock/qcom,gx_clkctl.yaml +++ b/bindings/clock/qcom,gx_clkctl.yaml @@ -15,12 +15,13 @@ description: | See also: dt-bindings/clock/qcom,gxclkctl-sun.h + dt-bindings/clock/qcom,gpucc-tuna.h properties: compatible: enum: - qcom,sun-gx_clkctl - + - qcom,tuna-gx_clkctl reg: maxItems: 1 From 644206f2a69ed22a49c4ab6d85b245cef644fed5 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 14 Aug 2024 14:12:29 +0530 Subject: [PATCH 069/112] ARM: dts: msm: Update videocc clock node as GenPD provider Mark videocc clock node as GenPD provider and disable the video GDSC regulator nodes for tuna platform. While at it, keep the gdsc regulator nodes as it is on rumi platform. Change-Id: I8e8fc066ea54f16ccbc73b9b8705881b27d4d112 Signed-off-by: Anaadi Mishra --- qcom/tuna-rumi.dtsi | 8 ++++++++ qcom/tuna.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 04603181..915c4926 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -204,3 +204,11 @@ &disp_cc_mdss_core_int2_gdsc { status = "ok"; }; + +&video_cc_mvs0_gdsc { + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + status = "ok"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 6b8af30b..a2a88aab 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1628,6 +1628,7 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mxc-supply = <&VDD_MXC_LEVEL>; + vdd_mm_mxc_voter-supply = <&VDD_MM_MXC_VOTER_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, @@ -1636,6 +1637,7 @@ "bi_tcxo_ao", "sleep_clk", "iface"; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2641,14 +2643,12 @@ &video_cc_mvs0_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0c_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; - status = "ok"; }; &reserved_memory { From 86ee38dfc0ee08a6daaf21cb9977798acf0951b4 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Wed, 21 Aug 2024 10:28:31 +0530 Subject: [PATCH 070/112] ARM: dts: msm: Update gpucc and gx_clkctl clock node as GenPD provider Mark gpucc clock node as GenPD provider and disable the graphics GDSC regulator nodes. Update gxclkctl node to add support for gx_clkctl_gx_gdsc power domain. While at it, keep the gdsc regulator nodes as it is on rumi platform. Change-Id: If205c2116841ff3a11ebce4e06ca3067c4a8721b Signed-off-by: Anaadi Mishra --- qcom/tuna-rumi.dtsi | 8 ++++++++ qcom/tuna.dtsi | 13 +++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 915c4926..b24a40a4 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -212,3 +212,11 @@ &video_cc_mvs0c_gdsc { status = "ok"; }; + +&gpu_cc_cx_gdsc { + status = "ok"; +}; + +&gx_clkctl_gx_gdsc { + status = "ok"; +}; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a2a88aab..64e59129 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1605,13 +1605,16 @@ "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; gxclkctl: clock-controller@3d68024 { - compatible = "qcom,dummycc"; - clock-output-names = "gxclkctl_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; + compatible = "qcom,tuna-gx_clkctl"; + reg = <0x3d68024 0x8>; + reg-name = "cc_base"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; + #power-domain-cells = <1>; }; tcsrcc: clock-controller@1fbf000 { @@ -2632,12 +2635,10 @@ &gpu_cc_cx_gdsc { clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gx_clkctl_gx_gdsc { parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; - status = "ok"; }; &video_cc_mvs0_gdsc { From 777901812f1984b49337f3f1e01a0646962c0165 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Mon, 21 Oct 2024 16:47:26 +0530 Subject: [PATCH 071/112] ARM: dts: msm: Move SDC2 core_reset to tuna SoC dtsi Move core_reset for SDC2 from platform-specific files to the tuna SoC. This change ensures that the reset properties are managed centrally in the SoC file, reducing redundancy and improving maintainability. Change-Id: If8e6bcdac9b05275d20f1d205dfc7e6461d39b72 Signed-off-by: Manish Pandey --- qcom/tuna-cdp.dtsi | 4 ---- qcom/tuna-mtp.dtsi | 4 ---- qcom/tuna-qrd.dtsi | 4 ---- qcom/tuna.dtsi | 3 +++ 4 files changed, 3 insertions(+), 12 deletions(-) diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index 6b85652a..86c0f38a 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -4,7 +4,6 @@ */ #include -#include &qupv3_se4_i2c { #address-cells = <1>; @@ -102,9 +101,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 6b85652a..86c0f38a 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -4,7 +4,6 @@ */ #include -#include &qupv3_se4_i2c { #address-cells = <1>; @@ -102,9 +101,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index a5251301..cca1aa8f 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -3,7 +3,6 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include -#include #include &qupv3_se4_spi { @@ -113,9 +112,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 6a96d53e..f2633c1a 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2070,6 +2070,9 @@ interconnect-names = "sdhc-ddr","cpu-sdhc"; operating-points-v2 = <&sdhc2_opp_table>; + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + qos0 { mask = <0xc0>; vote = <44>; From e8e8edde95c8a1cff2228f7a451b4498d92386e1 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Mon, 21 Oct 2024 17:30:31 +0530 Subject: [PATCH 072/112] ARM: dts: msm: Add fps entry for tuna Add fps entry for tuna. Change-Id: I54eec125fe80f167bc243283c2ac668c569c8147 Signed-off-by: Sanskar Omar --- qcom/tuna.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 6a96d53e..8e370466 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1485,12 +1485,16 @@ feat_conf6: feat_conf6@0118 { reg = <0x0118 0x4>; }; + + feat_conf18: feat_conf18@0148 { + reg = <0x0148 0x4>; + }; }; qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; - nvmem-cells = <&feat_conf6>; - nvmem-cell-names = "feat_conf6"; + nvmem-cells = <&feat_conf6>, <&feat_conf18>; + nvmem-cell-names = "feat_conf6", "feat_conf18"; }; clocks { From e3754277a6a0e6708b483ea4ad5783f320c5abef Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Wed, 16 Oct 2024 04:15:18 -0700 Subject: [PATCH 073/112] ARM: dts: msm: Add interconnect devices for KERA Add interconnect devices for clk_virt_noc, mc_virt_noc, aggre1_noc, aggre2_noc, cnoc_cfg_noc, cnoc_main_noc, gem_noc, lpass_ag_noc, lpass_lpiaon_noc, lpass_lpicx_noc, mmss_noc, nsp_noc, pcie_anoc and system_noc. This will allow consumers to get their path and set bandwidth constraints on them. Change-Id: I99812ef866f12c4a3d4b4ee9cf0dd809c946a64f Signed-off-by: Raviteja Laggyshetty --- qcom/kera.dtsi | 128 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 9dcb25d5..6cef0b74 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include @@ -374,6 +376,10 @@ , ; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; }; @@ -1159,6 +1165,128 @@ #reset-cells = <1>; }; + clk_virt: interconnect@0 { + compatible = "qcom,kera-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,kera-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,kera-cnoc_cfg"; + reg = <0x1600000 0x5200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,kera-cnoc_main"; + reg = <0x1500000 0x16080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,kera-system_noc"; + reg = <0x1680000 0x40000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,kera-pcie_anoc"; + reg = <0x16c0000 0x11400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,kera-aggre1_noc"; + reg = <0x16e0000 0x16400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,kera-aggre2_noc"; + reg = <0x1700000 0x1f400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,kera-mmss_noc"; + reg = <0x1780000 0x7d800>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,kera-gem_noc"; + reg = <0x24100000 0x163080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,kera-nsp_noc"; + reg = <0x320c0000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,kera-lpass_ag_noc"; + reg = <0x7e40000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,kera-lpass_lpiaon_noc"; + reg = <0x7400000 0x19080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,kera-lpass_lpicx_noc"; + reg = <0x7420000 0x44080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { size = <0x4000>; gunyah-label = <0x11>; From d67461e2497a06c0214c609268c467bb54b6fefc Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 21 Oct 2024 20:23:07 +0530 Subject: [PATCH 074/112] ARM: dts: qcom: Add ParrotPRO SKU soc id support Add ParrotPRO SKU soc id support for parrot-vm. Change-Id: I18de30fd773f92f1190da036fd3008ccb9263148 Signed-off-by: Swetha Chikkaboraiah --- qcom/parrot-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 82ea3d9d..5d6aeb10 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -8,7 +8,7 @@ / { qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, - <633 0x10000>, <634 0x10000>, <638 0x10000>; + <633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>; interrupt-parent = <&vgic>; qcom,vm-config { From c62aec98c24c611aa0d74edb4f974a76d360d478 Mon Sep 17 00:00:00 2001 From: quic_swarbu Date: Tue, 15 Oct 2024 14:55:31 +0530 Subject: [PATCH 075/112] ARM: dts: qcom: add goodix touch support for Clarence platform Add goodix touch support for clarence RCM platform. Change-Id: I73d8d4523c3b07bbbccef4d41b4739a56655f338 Signed-off-by: quic_swarbu --- qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi index fec6cbb4..005563db 100644 --- a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi @@ -17,8 +17,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -41,7 +43,8 @@ pinctrl-0 = <&ts_spi_active>; pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; - + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; }; From 1783e66276f701eba8bdf93b7e14218fb33ccd6f Mon Sep 17 00:00:00 2001 From: Nitesh Kumar Date: Fri, 11 Oct 2024 16:12:04 +0530 Subject: [PATCH 076/112] ARM: dts: qcom: Add PMIC die temp alarm, socd, bcl support for Tuna Add PMIC die temp mitigation, socd mitigation, bcl support for tuna. Change-Id: I5d6fc37c0b9f4e137510abb1ee4aa3b47cae6005 Signed-off-by: Nitesh Kumar --- qcom/pm7550ba.dtsi | 8 +- qcom/pmk8550.dtsi | 5 + qcom/tuna-mtp.dtsi | 2 + qcom/tuna-pm7550ba.dtsi | 35 +++++ qcom/tuna-pmic-overlay.dtsi | 44 +++++- qcom/tuna-qrd.dtsi | 1 + qcom/tuna-thermal-overlay.dtsi | 252 +++++++++++++++++++++++++++++++++ qcom/tuna-thermal.dtsi | 61 ++++++-- 8 files changed, 393 insertions(+), 15 deletions(-) create mode 100644 qcom/tuna-thermal-overlay.dtsi diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi index 953da75d..534a7689 100644 --- a/qcom/pm7550ba.dtsi +++ b/qcom/pm7550ba.dtsi @@ -156,7 +156,7 @@ pm7550ba_trip1: trip1 { temperature = <115000>; hysteresis = <0>; - type = "critical"; + type = "hot"; }; pm7550ba_trip2: trip2 { @@ -196,7 +196,7 @@ }; pm7550ba-bcl-lvl0 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 5>; @@ -222,7 +222,7 @@ }; pm7550ba-bcl-lvl1 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 6>; @@ -248,7 +248,7 @@ }; pm7550ba-bcl-lvl2 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 7>; diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi index 21ddcae1..f86189a3 100644 --- a/qcom/pmk8550.dtsi +++ b/qcom/pmk8550.dtsi @@ -30,6 +30,11 @@ #address-cells = <1>; #size-cells = <1>; + sm1510_present: sm1510_present@5d { + reg = <0x5d 0x1>; + bits = <5 5>; + }; + ocp_log: ocp-log@76 { reg = <0x76 0x6>; }; diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 86c0f38a..36ab15e3 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -4,6 +4,8 @@ */ #include +#include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index e0d2e5c3..344d2862 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -224,3 +224,38 @@ }; }; }; + +&pm7550ba_bcl { + nvmem-cells = <&sm1510_present>; + nvmem-cell-names = "sm1510_present"; +}; + +&thermal_zones { + pm7550ba-2s-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 8>; + + trips { + ibat_2s_lvl0: ibat-2s-lvl0 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7550ba-2s-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 9>; + + trips { + ibat_2s_lvl1: ibat-2s-lvl1 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi index 379dc61b..bc82d7e3 100644 --- a/qcom/tuna-pmic-overlay.dtsi +++ b/qcom/tuna-pmic-overlay.dtsi @@ -124,7 +124,7 @@ &thermal_zones { sys-therm-0 { - polling-delay-passive = <0>; + polling-delay-passive = <5000>; polling-delay = <0>; thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; trips { @@ -139,6 +139,48 @@ hysteresis = <1000>; type = "passive"; }; + + trip_config0: trip-config0 { + temperature = <78000>; + hysteresis = <8000>; + type = "passive"; + }; + + trip_config1: trip-config1 { + temperature = <80000>; + hysteresis = <10000>; + type = "passive"; + }; + + display_test_config1: display-test-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config2: display-test-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config3: display-test-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config4: display-test-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config5: display-test-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index cca1aa8f..cfd38eeb 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -4,6 +4,7 @@ */ #include #include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_spi { #address-cells = <1>; diff --git a/qcom/tuna-thermal-overlay.dtsi b/qcom/tuna-thermal-overlay.dtsi new file mode 100644 index 00000000..4d2ebf83 --- /dev/null +++ b/qcom/tuna-thermal-overlay.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pmih010x-bcl-lvl0 { + cooling-maps { + lbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_bcl 1 1>; + }; + + lbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; + + pmih010x-bcl-lvl1 { + cooling-maps { + lbat_modem1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_bcl 2 2>; + }; + + lbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmih010x-bcl-lvl2 { + cooling-maps { + lbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl0 { + cooling-maps { + vph_0_nr_scg { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vph_0_nr { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vph_0_mdm_lte { + trip = <&bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vph_gpu0 { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7550ba-bcl-lvl1 { + cooling-maps { + vph_1_nr_scg { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + vph_1_nr { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + vph_1_mdm_lte { + trip = <&bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vph_gpu1 { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl2 { + cooling-maps { + vph_gpu2 { + trip = <&bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; + + pmxr2230-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_gpu0 { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmxr2230-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_gpu1 { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmxr2230-bcl-lvl2 { + cooling-maps { + lbat_gpu2 { + trip = <&bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; + + sys-therm-0 { + cooling-maps { + apc1_cdev { + trip = <&trip_config0>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + apc0_cdev { + trip = <&trip_config0>; + cooling-device = <&APC0_MX_CX_PAUSE 1 1>; + }; + + cdsp_cdev { + trip = <&trip_config0>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + gpu_cdev { + trip = <&trip_config0>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + + cpu3_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + + cpu4_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + + cpu5_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + + cpu6_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + + cpu7_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + + lte_cdev { + trip = <&trip_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev { + trip = <&trip_config1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + display_cdev1 { + trip = <&display_test_config1>; + cooling-device = <&display_fps 1 1>; + }; + + display_cdev2 { + trip = <&display_test_config2>; + cooling-device = <&display_fps 2 2>; + }; + + display_cdev3 { + trip = <&display_test_config3>; + cooling-device = <&display_fps 3 3>; + }; + }; + }; +}; diff --git a/qcom/tuna-thermal.dtsi b/qcom/tuna-thermal.dtsi index 0f0afb75..f555783e 100644 --- a/qcom/tuna-thermal.dtsi +++ b/qcom/tuna-thermal.dtsi @@ -5,6 +5,10 @@ #include +&msm_gpu { + #cooling-cells = <2>; +}; + &soc { tsens0: tsens0@c228000 { compatible = "qcom,tsens-v2"; @@ -207,6 +211,11 @@ }; }; + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + qcom,cpufreq-cdev { compatible = "qcom,cpufreq-cdev"; @@ -236,16 +245,6 @@ #cooling-cells = <2>; }; - cdsp_sw_hvx: cdsp_sw_hvx { - qcom,qmi-dev-name = "cdsp_sw_hvx"; - #cooling-cells = <2>; - }; - - cdsp_sw_hmx: cdsp_sw_hmx { - qcom,qmi-dev-name = "cdsp_sw_hmx"; - #cooling-cells = <2>; - }; - cdsp_hw: cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <2>; @@ -1241,6 +1240,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-1 { @@ -1273,6 +1279,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-2 { @@ -1305,6 +1318,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu2_cdev { + trip = <&gpu2_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-3 { @@ -1337,6 +1357,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu3_cdev { + trip = <&gpu3_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-4 { @@ -1369,6 +1396,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu4_cdev { + trip = <&gpu4_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-5 { @@ -1401,6 +1435,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu5_cdev { + trip = <&gpu5_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; nsphvx-0 { From 0beccbc35be42c5a3763462852d928073247a7f1 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Tue, 22 Oct 2024 12:43:01 +0530 Subject: [PATCH 077/112] ARM: dts: msm: Add CPUSYS_VM support for parrot/ravelin Add support for CPUSYS_VM loading for parrot and ravelin targets. Change-Id: I501768800e705cf0a7fdec60264b88555dc5a4b9 Signed-off-by: Swetha Chikkaboraiah --- qcom/parrot.dtsi | 10 ++++++++++ qcom/ravelin.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index d36b3a45..e08ae024 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -2066,6 +2066,16 @@ virtio-backends = <&trust_ui_vm_virt_be0>; }; + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; + }; + qrtr-gunyah { compatible = "qcom,qrtr-gunyah"; qcom,master; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 32b8915b..1c15c92c 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -2473,6 +2473,16 @@ virtio-backends = <&trust_ui_vm_virt_be0>; }; + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; + }; + vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; From a10ae9a3631ff0bf43bbd3c3b45d39629235e2a9 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 8 Oct 2024 15:17:47 +0530 Subject: [PATCH 078/112] ARM: dts: msm: Add GSI event buffers on Tuna USB The GSI event buffers are required for the various GSI related usecases which are excercised from the dwc3 glue driver. Add the number of event buffers along with the register offsets defined. Change-Id: I07bd9bb0c319392657070b6c338ddc0edf442934 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 59d0d614..7023ffdb 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -37,11 +37,6 @@ interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; - interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; - interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, - <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; - qcom,use-pdc-interrupts; qcom,use-eusb2-phy; @@ -49,6 +44,20 @@ qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-disconnected = <133333333>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0 0xa600000 0x0 0xd93c>; From a3e441feb208917f7a39d47f3443cb39239dcbed Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 10 Oct 2024 15:34:15 +0530 Subject: [PATCH 079/112] ARM: dts: msm: Adding Regulator support for both HS and SS Phy In this change EUSB_1P2 is added for eusb_phy and Refgen support is added for SS Phy. Change-Id: I1d6726882725c958178f0ad43bbd0ae264cb6046 Signed-off-by: Uttkarsh Aggarwal --- qcom/tuna-usb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 7023ffdb..295425b4 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -101,6 +101,7 @@ vdd-supply = <&L3B>; qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&L4B>; vdd_refgen-supply = <&L2B>; clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, @@ -125,6 +126,7 @@ qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; core-supply = <&L4B>; + vdd_refgen-supply = <&L2B>; usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, From e5d54ea8bd8b330b40a49f4300e20987db5cc23e Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Tue, 22 Oct 2024 14:15:35 +0530 Subject: [PATCH 080/112] ARM: dts: msm: Add arm-smmu device on kera-vm Describe the register, interrupts, and settings of the arm-smmu device. Change-Id: I7a2be4e5b344a40c42657e5d03f2bc88696f29c1 Signed-off-by: Vijayanand Jitta --- qcom/kera-vm.dtsi | 2 ++ qcom/msm-arm-smmu-kera-vm.dtsi | 62 ++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 qcom/msm-arm-smmu-kera-vm.dtsi diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi index a40e16dc..ba17e3a3 100644 --- a/qcom/kera-vm.dtsi +++ b/qcom/kera-vm.dtsi @@ -244,3 +244,5 @@ qcom,support-hypervisor; }; }; + +#include "msm-arm-smmu-kera-vm.dtsi" diff --git a/qcom/msm-arm-smmu-kera-vm.dtsi b/qcom/msm-arm-smmu-kera-vm.dtsi new file mode 100644 index 00000000..f9dabb87 --- /dev/null +++ b/qcom/msm-arm-smmu-kera-vm.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x7>; + num-smrs = <0xe>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c08 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0804 0x0002 0x00000001>, + + /* NSP:Compute */ + <0x0c0b 0x0000 0x00000303>, + + /* SF:Camera IPE*/ + <0x1808 0x0020 0x00000001>, + + /* SF:Camera CDM IPE/IFE/OFE*/ + <0x1841 0x0000 0x00000001>, + <0x1861 0x0000 0x00000001>, + <0x1881 0x0000 0x00000001>, + + /* SF:Camera ICP*/ + <0x18c2 0x0000 0x00000001>, + <0x1982 0x0000 0x00000001>, + + /* SF:Camera CRE*/ + <0x18e8 0x0000 0x00000103>, + + /* SF:EVA */ + <0x1901 0x0020 0x00000103>, + <0x1925 0x0000 0x00000103>; + }; +}; From a14fb7406408af01561cf637380a61f8a2836611 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Fri, 18 Oct 2024 15:28:04 +0530 Subject: [PATCH 081/112] ARM: dts: msm: Add CRM nodes for tuna Add Camera, Display, PCIe CESTA nodes for tuna. Also disable them in RUMI till validations are completed. Also rename the syscon device to avoid naming conflicts. Change-Id: Ia8238c95b18a9992efe34e34d062e3835b501dcf Signed-off-by: Sneh Mankad --- qcom/tuna-rumi.dtsi | 12 ++++++++++ qcom/tuna.dtsi | 53 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 5f538408..211700f0 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -127,6 +127,18 @@ status = "disabled"; }; +&cam_crm { + status = "disabled"; +}; + +&disp_crm { + status = "disabled"; +}; + +&pcie_crm { + status = "disabled"; +}; + &qupv3_se7_2uart { qcom,rumi_platform; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1a106540..dba7b358 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -813,6 +813,55 @@ }; }; + disp_crm: crm@af21000 { + label = "disp_crm"; + compatible = "qcom,disp-crm-v2"; + reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>, + <0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = , + , + , + , + , + ; + interrupt-names = "disp_crm_drv0", + "disp_crm_drv1", + "disp_crm_drv2", + "disp_crm_drv3", + "disp_crm_drv4", + "disp_crm_drv5"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2 3 4 5>; + qcom,sw-drv-ids = <0 1 2 3 4 5>; + }; + + cam_crm: crm@adcb000 { + label = "cam_crm"; + compatible = "qcom,cam-crm-v2"; + reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd200 0x400>, + <0xadcd600 0x2000>, <0xadcf600 0x700>, <0xadcfd00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = ; + interrupt-names = "cam_crm_drv0"; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2>; + qcom,sw-drv-ids = <0>; + }; + + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm-v2"; + reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>, + <0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = ; + interrupt-names = "pcie_crm_drv0"; + clocks = <&pcie_0_pipe_clk>; + qcom,hw-drv-ids = <0 1>; + qcom,sw-drv-ids = <0>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,tuna-pdc", "qcom,pdc"; reg = <0xb220000 0x10000>, <0x174000f0 0x64>; @@ -1577,7 +1626,7 @@ <&cpufreq_hw 3>; }; - cam_crm: syscon@adcd600 { + camcc_crm: syscon@adcd600 { compatible = "syscon"; reg = <0xadcd600 0x2000>; }; @@ -1595,7 +1644,7 @@ clock-names = "bi_tcxo", "sleep_clk", "iface"; - qcom,cam_crm-crmc = <&cam_crm>; + qcom,cam_crm-crmc = <&camcc_crm>; #clock-cells = <1>; #reset-cells = <1>; }; From 5d3122681a759747b1604233cea70866e1064d93 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 22 Oct 2024 14:45:39 +0530 Subject: [PATCH 082/112] ARM: dts: msm: Add gcc qcom-dummycc support for TVM on Kera For upstream and tvm, qup common driver uses gcc phandles which are common in dt and to avoid qup driver probe failure, add gcc qcom-dummycc support as they are nop. This helps in avoiding additional logic in qup driver to not conditionalize based on variant. Change-Id: I00c3c59116519822be0368511499874951d0d882 Signed-off-by: Anaadi Mishra --- qcom/kera-vm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi index ba17e3a3..5ae595f2 100644 --- a/qcom/kera-vm.dtsi +++ b/qcom/kera-vm.dtsi @@ -205,6 +205,13 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + virtio-mmio { wakeup-source; }; From 7a4852007b16ddb6b6efb24f2d7e5eab77a90b49 Mon Sep 17 00:00:00 2001 From: Auditya Bhattaram Date: Wed, 18 Sep 2024 15:39:12 +0530 Subject: [PATCH 083/112] ARM: dts: qcom: Add support for LowSVS on ICC for soccp Add support for LowSVS on ICC for soccp. Change-Id: Ic845482060c91edf4e9bab3f2248dd6299f43194 Signed-off-by: Auditya Bhattaram --- qcom/sun.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 045ed6b9..47cd48d4 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3650,6 +3650,9 @@ <&cnoc_main MASTER_CNOC_CFG &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "rproc_cnoc"; + rproc-ddr-set-icc-low-svs; + rproc-ddr-lowsvs-icc-bw = <1200>; + memory-region = <&soccp_mem 0>; soccp-tcsr = <&tcsr 0x1a000>; soccp-spare = <0xda0024>; From 459c98e26490aba8af41a03dc4812dfcc9ba0183 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Tue, 22 Oct 2024 17:22:40 +0530 Subject: [PATCH 084/112] bindings: Add Pinctrl documentation for Kera VM Add documentation describing the pinctrl devicetree properties for Kera VM. Change-Id: I45881e367708a614d3459568035807d4878aab4a Signed-off-by: Hrishabh Rajput --- bindings/pinctrl/qcom,kera-vm-tlmm.yaml | 190 ++++++++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 bindings/pinctrl/qcom,kera-vm-tlmm.yaml diff --git a/bindings/pinctrl/qcom,kera-vm-tlmm.yaml b/bindings/pinctrl/qcom,kera-vm-tlmm.yaml new file mode 100644 index 00000000..92cd32ad --- /dev/null +++ b/bindings/pinctrl/qcom,kera-vm-tlmm.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kera-vm-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kera VM TLMM block + +maintainers: + - Murali Nalajala + - Satya Durga Srinivasu Prabhala + +description: | + This binding describes the Top Level Mode Multiplexer block for VM. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kera-vm-tlmm + + reg: + maxItems: 1 + + interrupts-extended: true + interrupt-controller: true + '#interrupt-cells': true + + gpio-controller: true + '#gpio-cells': true + gpio-ranges: true + gpios: + description: array of gpio pin number required by VM TLMM clients + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-kera-vm-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kera-vm-tlmm-state" + additionalProperties: false + +$defs: + qcom-kera-vm-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3, + atest_char_start, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1, + audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk, + cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0, + cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4, + cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2, + cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0, + cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, + gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0, + i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0, + i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0, + i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0, + i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0, + i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, + i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1, + mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, + mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, + phase_flag14, phase_flag15, phase_flag16, phase_flag17, + phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, + phase_flag25, phase_flag26, phase_flag27, phase_flag28, + phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, + qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, + qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4, + qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, + qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3, + qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0, + qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1, + qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2, + qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3, + qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4, + qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2, + qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, + qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6, + qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0, + qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40, + sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, + tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, + vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + then: + required: + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,kera-vm-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup1_se7_l0"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup1_se7_l1"; + bias-disable; + }; + }; + }; +... From 960b39e2cc779ad3bb18b8e8d136b6d8695498df Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Tue, 22 Oct 2024 17:52:13 +0530 Subject: [PATCH 085/112] ARM: dts: msm: Add the "gcc_cfg_noc_pcie_anoc_ahb_clk" clock for tuna Add the "gcc_cfg_noc_pcie_anoc_ahb_clk" clock for tuna. Change-Id: Ib023883dc4aac18e024aa8f0250de7aa5ad2b91a Signed-off-by: Paras Sharma --- qcom/tuna-pcie.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi index b0972852..d50e57d9 100644 --- a/qcom/tuna-pcie.dtsi +++ b/qcom/tuna-pcie.dtsi @@ -94,6 +94,7 @@ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie_0_pipe_clk>; @@ -104,13 +105,13 @@ "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", - "gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk", - "pcie_pipe_clk_mux", + "gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", + "pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, - <100000000>, <0>, <0>, <0>, <0>, <0>, <0>; + <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, - <0>, <0>, <0>, <1>, <0>, <0>, <0>; + <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_PHY_BCR>; From 41b5132332e3edfe3e30f1b7c70372ca8540fda2 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 13 Aug 2024 15:59:18 +0530 Subject: [PATCH 086/112] ARM: dts: msm: Add pmic-glink support and its clients for kera Add pmic-glink support and its clients: - 1.ucsi. 2.qti-battery-charger. 3.altmode. For debug support enable other clients like: - 1.glink-adc. 2.charger-ulog. 3.glink-spmi-regmap. 4.battery-debug. Change-Id: Ida1252a029918ce53bd97ba9fcbdea89e253a774 Signed-off-by: Kavya Nunna --- qcom/kera.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 3665d86b..90fa4ef0 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1328,6 +1328,55 @@ thermal_zones: thermal-zones { }; + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + }; + + pmic_glink_adc: qcom,glink-adc { + compatible = "qcom,glink-adc"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; }; #include "tuna-gdsc.dtsi" From ebae62793278df1bc910ae18d5e73172c149167f Mon Sep 17 00:00:00 2001 From: Ashok Kadavul Date: Thu, 3 Oct 2024 13:50:21 +0530 Subject: [PATCH 087/112] dt-bindings: leds: Add bindings for spmi-wled driver Add devicetree bindings for the spmi-wled driver. Change-Id: Iee2dd7e2a4361b673d0f87a439e1d02e35b70e0a Signed-off-by: Ashok Kadavul --- bindings/leds/backlight/qcom-spmi-wled.yaml | 386 ++++++++++++++++++++ 1 file changed, 386 insertions(+) create mode 100644 bindings/leds/backlight/qcom-spmi-wled.yaml diff --git a/bindings/leds/backlight/qcom-spmi-wled.yaml b/bindings/leds/backlight/qcom-spmi-wled.yaml new file mode 100644 index 00000000..7abb1eac --- /dev/null +++ b/bindings/leds/backlight/qcom-spmi-wled.yaml @@ -0,0 +1,386 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/qcom-spmi-wled.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. WLED (White Light Emitting Diode) driver + +maintainers: + - Jishnu Prakash + +description: > + WLED (White Light Emitting Diode) driver is used for controlling display + backlight that is part of PMIC on Qualcomm Technologies, Inc. reference + platforms. The PMIC is connected to the host processor via SPMI bus. + +properties: + compatible: + enum: + - qcom,pmi8998-spmi-wled + - qcom,pm8150l-spmi-wled + - qcom,pm6150l-spmi-wled + - qcom,pm660l-spmi-wled + - qcom,pm7325b-spmi-wled + + reg: + minItems: 1 + maxItems: 2 + description: Base address and size of the WLED modules. + + reg-names: + $ref: /schemas/types.yaml#/definitions/string + description: | + Names associated with base addresses. should be + "wled-ctrl-base", "wled-sink-base". + + interrupts: + minItems: 1 + maxItems: 2 + description: | + Interrupts associated with WLED. Interrupts can be specified as per the encoding listed + under Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt. + + interrupt-names: + items: + - const: sc-irq + - const: ovp-irq + - const: pre-flash-irq + - const: flash-irq + + label: true + + default-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Brightness value on boot. Default is 2048. + For pmi8998, it is 0-4095. + For pm8150l, this can vary from 0-4095 or 0-32767 depending + on the brightness control mode. If CABC is enabled, 0-4095 + range is used. + + max-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum brightness level. Allowed values are + For pmi8998, it is 4095. + For pm8150l, this can be either 4095 or 32767. + If CABC is enabled, this is capped to 4095. + + qcom,fs-current-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + per-string full scale current limit in uA. value from + 0 to 30000 with 5000 uA resolution. + default is 25000 uA + + qcom,boost-current-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ILIM threshold in mA. values are 105, 280, 450, 620, 970, + 1150, 1300, 1500. + default is 970 mA + + qcom,switching-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Switching frequency in KHz. values are + 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, + 1600, 1920, 2400, 3200, 4800, 9600. + default is 800 KHz + + qcom,ovp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Over-voltage protection limit in mV. values are 31100, + 29600, 19600, 18100. + default is 29600 mV + + qcom,string-cfg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Bit mask of the WLED strings. Bit 0 to 3 indicates strings + 0 to 3 respectively. WLED module has four strings of leds + numbered from 0 to 3. Each string of leds are operated + individually. Specify the strings using the bit mask. Any + combination of led strings can be used. + Default value is 15 (b1111). + + qcom,en-cabc: + type: boolean + description: | + Specify if cabc (content adaptive backlight control) is + needed. + + qcom,ext-pfet-sc-pro-en: + type: boolean + description: | + Specify if external PFET control for short circuit + protection is needed. This is not applicable for PM8150L. + + qcom,auto-calibration: + type: boolean + description: | + Enables auto-calibration of the WLED sink configuration. + + qcom,modulator-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Selects the modulator used for brightness modulation. + Allowed values are + 0 - Modulator A + 1 - Modulator B + If not specified, then modulator A will be used by default. + This property is applicable only to WLED5 peripheral. + + qcom,cabc-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Selects the CABC pin signal used for brightness modulation. + Allowed values are + 0 - CABC disabled + 1 - CABC 1 + 2 - CABC 2 + 3 - External signal (e.g. LPG) is used for dimming + This property is applicable only to WLED5 peripheral. + + qcom,leds-per-string: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + If specified, can be used to calculate available current + during selfie flash operation. If not specified, available + current calculated is simply the configured threshold. + + io-channels: + maxItems: 3 + description: | + IIO channel specifiers for each name in io-channel-names. + + io-channel-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: | + Names of the IIO channels that are used by WLED. + For details about IIO bindings refer below + Documentation/devicetree/bindings/iio/iio-bindings.txt + + qcom,use-exp-dimming: + type: boolean + description: | + Specifies that exponential dimming lookup table values should be used. + + qcom,exp-dimming-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + It specifies a table of brightness values that can be programmed + into WLED_SINK for exponential dimming which provides smooth brightness + change. There should be exactly 256 values in the table and they should + be at most 15 bits long. This table would be used only if the + "qcom,use-exp-dimming" property is set. This feature is supported from + PM7325B onwards. + + qcom,slew-ramp-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Software brightness slew ramp time values in ms. This is supported from + PM7325B onwards. + Valid values are 2, 4, 8, 64, 128, 192, 256, 320, 384, 448, 512, 704, 896, + 1024, 2048, 4096. + default is 256 + +patternProperties: + "^wled_torch[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: Properties for wled_torch. + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "torch". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_torch" is used. + + qcom,wled-torch-fsc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch full scale current in mA. This configures the + maximum current allowed for torch device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 30 mA. + + qcom,wled-torch-step: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + + qcom,wled-torch-timer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch safety timer in ms. This configures the safety + timer to turn off torch automatically after timer expiry. + Allowed values are 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 1200 ms. + + + required: + - label + + "^wled_flash[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: wled_flash child subnode properties + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "flash". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_flash" is used. + + qcom,wled-flash-fsc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash full scale current in mA. This configures the + maximum current allowed for flash device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 40 mA. + + qcom,wled-flash-step: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + + qcom,wled-flash-timer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash safety timer in ms. This configures the safety + timer to turn off flash automatically after timer expiry. + Allowed values are 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 100 ms. + + required: + - label + + "^wled_switch[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: wled_switch child subnode properties + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "switch". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_switch" is used. + + required: + - label + +required: + - compatible + - reg + - reg-names + - label + +additionalProperties: false + +examples: + - | + #include + + qcom-wled@d800 { + compatible = "qcom,pmi8998-spmi-wled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd800 0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq", "ovp-irq"; + qcom,fs-current-limit = <25000>; + qcom,boost-current-limit = <970>; + qcom,switching-freq = <800>; + qcom,ovp = <29600>; + qcom,string-cfg = <15>; + }; + + - | + #include + #include + qcom-wled@d800 { + compatible = "qcom,pm8150l-spmi-wled"; + #address-cells = <2>; + #size-cells = <0>; + reg = <0xd800 0x100>, <0xd900 0x100>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + qcom,string-cfg = <7>; + + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>; + + io-channel-names = "rbatt", + "voltage_ocv", + "current_now"; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,wled-torch-fsc = <40>; + qcom,wled-torch-step = <300>; + qcom,wled-torch-timer = <600>; + }; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,wled-flash-fsc = <60>; + qcom,wled-flash-step = <100>; + qcom,wled-flash-timer = <200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + }; + + }; + + - | + #include + qcom,leds@d800 { + compatible = "qcom,pm660l-spmi-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + linux,name = "wled"; + linux,default-led-trigger = "bkl-trigger"; + + }; From e6219eae76acad1941bd38de434fe93bf35d24e3 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 21 Oct 2024 22:37:23 +0530 Subject: [PATCH 088/112] bindings: soc: qcom: Document pcie-pdc compatible for tuna Document pcie pdc device support for tuna. Change-Id: I56a2d505fd453ffbebc95dbf202b5f949ded4c4c Signed-off-by: Sneh Mankad --- bindings/soc/qcom/qcom,pcie-pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/soc/qcom/qcom,pcie-pdc.yaml b/bindings/soc/qcom/qcom,pcie-pdc.yaml index 8010730e..37a32c9f 100644 --- a/bindings/soc/qcom/qcom,pcie-pdc.yaml +++ b/bindings/soc/qcom/qcom,pcie-pdc.yaml @@ -21,6 +21,7 @@ properties: - qcom,sun-pcie-pdc - qcom,pineapple-pcie-pdc - qcom,cliffs-pcie-pdc + - qcom,tuna-pcie-pdc - qcom,pcie-pdc reg: From 9baa3580d7fc4c48e0cd88bfbda44635a0c68835 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Wed, 23 Oct 2024 11:03:24 +0530 Subject: [PATCH 089/112] ARM: dts: msm: Add pcie-pdc device for tuna Add PCIe PDC device to wakeup SoC from PCIe clk request gpio. Change-Id: Ic3a6027c6b3c8e80ff305ea82393720930c732b9 Signed-off-by: Sneh Mankad --- qcom/tuna.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a2b7031e..4494477c 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -862,6 +862,11 @@ qcom,rproc-handle = <&adsp_pas>; }; + pcie_pdc: pdc@b360000 { + compatible = "qcom,tuna-pcie-pdc", "qcom,pcie-pdc"; + reg = <0xb360000 0x10000>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,tuna-adsp-pas"; reg = <0x03000000 0x10000>; From 9f952013af17fb190a42438f07ec81cb2b762a59 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Wed, 23 Oct 2024 14:17:00 +0530 Subject: [PATCH 090/112] ARM: dts: msm: Update UFS_RESET pin for tuna Commit 95fd342 (pinctrl: qcom: Add missing pins for Tuna SoC and update egpio) updates the UFS_RESET pin from 187 to 191. This commit updates tuna UFS 'reset-gpios' to 191 to ensure proper functioning of UFS. Change-Id: I3e7720449ca439b8ea2c0364137408d8d91a5701 Signed-off-by: Manish Pandey --- qcom/tuna.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index a2b7031e..a2fd1593 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2207,7 +2207,7 @@ qcom,bypass-pbl-rst-wa; qcom,max-cpus = <8>; - reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; From 1c62c7510af0e5efe34d4492b38126998e95f165 Mon Sep 17 00:00:00 2001 From: songchai Date: Wed, 23 Oct 2024 03:27:36 -0700 Subject: [PATCH 091/112] ARM: dts: msm: enable coresight and memory dump for tuna Enable coresight and memory dump for tuna. Change-Id: I6eeb25a2b24e8dfcc592113b177b53afc11754fd Signed-off-by: songchai --- qcom/tuna.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 2fef1f7a..5bad991e 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -3254,6 +3254,8 @@ }; }; +#include "tuna-coresight.dtsi" +#include "tuna-debug.dtsi" #include "tuna-pinctrl.dtsi" #include "tuna-regulators.dtsi" #include "tuna-usb.dtsi" From e5a68b71d140dc1767b37860ec2ff0072778b06f Mon Sep 17 00:00:00 2001 From: Vijayanand Jitta Date: Wed, 23 Oct 2024 16:24:30 +0530 Subject: [PATCH 092/112] ARM: dts: msm: update kernel bootargs for tuna Update the following bootargs: 1) Enable Page poisoning 2) Disable cgroup memory accounting. Change-Id: I67f4db126924e4633557d9c40c0b42b8d42a22e4 Signed-off-by: Vijayanand Jitta --- qcom/tuna.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 2fef1f7a..75224840 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -38,7 +38,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; From cf9b41da358577000f572ad9f0c9233ce8306b4d Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 23 Oct 2024 17:13:15 +0530 Subject: [PATCH 093/112] ARM: dts: msm: Add pmiv0102 support for kera Add pmiv0102 support for kera platforms. Change-Id: I8a579b873b7c224cb4eb53637e5ee08f7bd021e2 Signed-off-by: Kavya Nunna --- qcom/kera-pmiv0102.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 qcom/kera-pmiv0102.dtsi diff --git a/qcom/kera-pmiv0102.dtsi b/qcom/kera-pmiv0102.dtsi new file mode 100644 index 00000000..94ec6fbd --- /dev/null +++ b/qcom/kera-pmiv0102.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-pmiv0108.dtsi" + +&pmiv010x_amoled { + status= "ok"; +}; + +&pmiv010x_amoled_ecm { + status = "ok" +}; + + From 10f6f3c714ac024c9f1127c57107b04b1b9487b6 Mon Sep 17 00:00:00 2001 From: Ashok Kadavul Date: Thu, 3 Oct 2024 15:48:48 +0530 Subject: [PATCH 094/112] dt-bindings: qpnp-lcdb-regulator: Support for some LCDB DT properties Add support for the following LCDB devicee tree properties: "qcom,ncp-symmetry" to make NCP voltage follow LDO voltage directly. "qcom,high-p2-blank-time-ns" to control the higher clamp threshold for p2 minimum on time. "qcom,low-p2-blank-time-ns" to control the lower clamp threshold for p2 minimum on time. "qcom,mpc-current-thr-ma" to control the mpc threshold for inductor current after start up is done. Change-Id: I873d177fd71da7a98aa043f1b30db7c42a6cd803 Signed-off-by: Ashok Kadavul --- .../regulator/qcom,qpnp-lcdb-regulator.yaml | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml index 4b7cbd70..4048d81c 100644 --- a/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml +++ b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml @@ -33,6 +33,11 @@ properties: to be enabled only on platforms where voltage needs to be ramped up with multiple steps. + qcom,ncp-symmetry: + type: boolean + description: Enabling this will make NCP voltage follow LDO voltage + directly. + qcom,pwrdn-delay-ms: description: Required to control the LDO power down delay. Possible values are 0, 1, 4, 8. @@ -44,13 +49,30 @@ properties: qcom,pwrup-config: $ref: /schemas/types.yaml#/definitions/uint32 description: Controls the order of powering up BOOST, LDO AND NCP - blocks. Appilcable for PM7325B. Possible values are 0, 1, 2, 3, 4. + blocks. Applicable for PM7325B. Possible values are 0, 1, 2, 3, 4. 0 - Boost, LDO, NCP 1 - Boost, LDO 2 - Boost, NCP 3 - Boost only 4 - Boost, NCP, LDO + qcom,high-p2-blank-time-ns: + description: Controls the higher clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + + qcom,low-p2-blank-time-ns: + description: Controls the lower clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + + qcom,mpc-current-thr-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Controls the mpc threshold for inductor current after start up + is done. Applicable for PM7325B. Possible values are 160, 200, 240, + 280, 320, 360, 400, 440. + + qcom,ttw-enable: type: boolean description: Touch to wake-up support enabled. From 5971284786b4f53c95aa179c0e9af73d8cddc5bf Mon Sep 17 00:00:00 2001 From: Shilpa Suresh Date: Tue, 24 Sep 2024 12:25:45 +0530 Subject: [PATCH 095/112] dt-bindings: pinctrl: qcom-pmic-gpio: Add binding for PM7325B Add compatible string for pm7325b gpio in pmic gpio bindings. Change-Id: I015425864bc9510302364c17cfe361003031af97 Signed-off-by: Shilpa Suresh --- bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/pinctrl/qcom,pmic-gpio.yaml b/bindings/pinctrl/qcom,pmic-gpio.yaml index 7fda52d1..911034f9 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -28,6 +28,7 @@ properties: - qcom,pm6450-gpio - qcom,pm7250b-gpio - qcom,pm7325-gpio + - qcom,pm7325b-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio @@ -183,6 +184,7 @@ allOf: - qcom,pm8350b-gpio - qcom,pm8550ve-gpio - qcom,pm8950-gpio + - qcom,pm7325b-gpio - qcom,pm7550ba-gpio - qcom,pmi632-gpio then: @@ -441,6 +443,7 @@ $defs: - gpio1-gpio9 for pm6450 - gpio1-gpio12 for pm7250b - gpio1-gpio10 for pm7325 + - gpio1-gpio8 for pm7325b - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 From 87ac1a7b7c5c3af1bd7a1c7995bd7c9d111a9de8 Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Thu, 24 Oct 2024 12:22:14 +0530 Subject: [PATCH 096/112] ARM: dts: msm: Update GPIOs for Pinctrl TLMM on Tuna Remove invalid GPIOs and replace them with corresponding pins for Tuna SoC. Change-Id: I9db60c4edde97c63296380fd4df7557cf2b5d2e9 Signed-off-by: Hrishabh Rajput --- qcom/tuna-vm.dtsi | 14 +++++--------- qcom/tuna.dtsi | 12 ++++-------- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 19fda190..e52fa547 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -258,15 +258,13 @@ interrupt-controller; #interrupt-cells = <2>; /* Valid pins */ - gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>; + gpios = /bits/ 16 <77 78 14 126 16 17 18 19 189 176 44 45 46 47>; }; tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; tlmm-vm-test { @@ -274,10 +272,8 @@ pinctrl-names = "active", "sleep"; pinctrl-0 = <&qupv3_se1_7i2c_active>; pinctrl-1 = <&qupv3_se1_7i2c_sleep>; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; pinctrl@f000000 { diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index d51d206e..56a5c3e9 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1159,20 +1159,16 @@ tuivm { qcom,label = <0x08>; qcom,vmid = <45>; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; slimbam: bamdma@6c04000 { From 1d07bacb66896eb8efa75e12e85fac805e28ef76 Mon Sep 17 00:00:00 2001 From: Satya Priya Kakitapalli Date: Tue, 17 Sep 2024 12:06:37 +0530 Subject: [PATCH 097/112] dt-bindings: clock: Add gcc, debugcc and rpmhcc for sdxbaagha Add GCC, DEBUGCC and RPMHCC dt-bindings for sdxbaagha platform. Change-Id: I7aec3f5160d57c30637325042d3ade770815d21c Signed-off-by: Satya Priya Kakitapalli --- bindings/clock/qcom,debugcc.yaml | 1 + bindings/clock/qcom,rpmhcc.yaml | 1 + bindings/clock/qcom,sdxbaagha-gcc.yaml | 60 ++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 bindings/clock/qcom,sdxbaagha-gcc.yaml diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 63a2918d..1c8b8d47 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -20,6 +20,7 @@ properties: - qcom,sun-debugcc - qcom,parrot-debugcc - qcom,sdx75-debugcc + - qcom,sdxbaagha-debugcc - qcom,sm4450-debugcc - qcom,monaco-debugcc - qcom,tuna-debugcc diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index 70fa6032..1b915c27 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk - qcom,sdx75-rpmh-clk + - qcom,sdxbaagha-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk diff --git a/bindings/clock/qcom,sdxbaagha-gcc.yaml b/bindings/clock/qcom,sdxbaagha-gcc.yaml new file mode 100644 index 00000000..7f4b09b6 --- /dev/null +++ b/bindings/clock/qcom,sdxbaagha-gcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdxbaagha-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Global clock control module which supports the clocks, resets and + power domains on sdxbaagha + + See also: + - dt-bindings/clock/qcom,gcc-sdxbaagha.h + +properties: + compatible: + const: qcom,sdxbaagha-gcc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: PCIE Pipe clock source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: pcie_pipe_clk + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdxbaagha-gcc"; + reg = <0x80000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>,<&rpmhcc RPMH_CXO_CLK_A>, + <&pcie_pipe_clk>,<&sleep_clk>; + clock-names = "bi_tcxo","bi_tcxo_ao", + "pcie_pipe_clk","sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... From 5de6529a5cf982563b5e820b17deecb04fd2b160 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Tue, 17 Sep 2024 15:51:16 +0530 Subject: [PATCH 098/112] ARM: dts: msm: Add support for CAMCC, CAMBISTMCLKCC and DISPCC on Kera Add support for camera, cambistmclk and display clock controller nodes on Kera platform. While at it, move camcc and dispcc gdsc's to real alongwith required interconnect voting for camcc_titan_top gdsc and updated dispcc crm property name for tuna platform. Change-Id: I844a35d688eb4050212e11e81eae1aaa55a4a24f Signed-off-by: Ajit Pandey --- qcom/kera.dtsi | 61 ++++++++++++++++++++++++++++++++++++++------------ qcom/tuna.dtsi | 2 +- 2 files changed, 48 insertions(+), 15 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d349e893..0859d024 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1163,22 +1163,58 @@ }; cambistmclkcc: clock-controller@1760000 { - compatible = "qcom,dummycc"; - clock-output-names = "cambistmclkcc_clocks"; + compatible = "qcom,tuna-cambistmclkcc", "syscon"; + reg = <0x1760000 0x6000>; + reg-name = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; camcc: clock-controller@ade0000 { - compatible = "qcom,dummycc"; - clock-output-names = "camcc_clocks"; + compatible = "qcom,kera-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; + dispcc_crm: syscon@af27800 { + compatible = "syscon"; + reg = <0xaf27800 0x2000>; + }; + dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,tuna-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; + qcom,disp_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1718,42 +1754,39 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_ofe_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_2_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_titan_top_gdsc { - compatible = "regulator-fixed"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + interconnect-names = "mmnoc"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index d51d206e..979a84e1 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1708,7 +1708,7 @@ "bi_tcxo_ao", "sleep_clk", "iface"; - qcom,dispcc_crm-crmc = <&dispcc_crm>; + qcom,disp_crm-crmc = <&dispcc_crm>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From d35403b3dea4846fc243c9b429ef172ea355fcf3 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Thu, 24 Oct 2024 14:22:49 +0530 Subject: [PATCH 099/112] ARM: dts: msm: Add ipcc_mproc_ns1 for tuna TUIVM Add ipcc_mproc_n1 device tree node and entries to enable IPCC and mbox communication between TUIVM and CDSP SecurePD on tuna TUIVM. Change-Id: Ia38df4150a766a66cdead3c2dd60b4e6fc2fc4cd Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna-vm.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 19fda190..cc4bb9fb 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -73,7 +73,8 @@ vm-attrs = "context-dump", "crash-restart"; iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 - 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>; + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0 + 0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>; /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. * QUP1_SE4: GPII5 : IRQ_316 @@ -324,6 +325,15 @@ <0x17180000 0x200000>; /* GICR * 8 */ }; + ipcc_mproc_ns1: qcom,ipcc@407000 { + compatible = "qcom,ipcc"; + reg = <0x407000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; always-on; From 3845e9a00a2d0df80f39a6c1519ece4346d7a7d0 Mon Sep 17 00:00:00 2001 From: Manish Pandey Date: Thu, 24 Oct 2024 22:08:59 +0530 Subject: [PATCH 100/112] ARM: dts: msm: Add UFS nodes for kera pre-sil Add UFS host controller and PHY nodes for kera soc. Change-Id: I11a8dde3e083c35b4744a6bed5e8032f69fbf4fb Signed-off-by: Manish Pandey --- qcom/kera-rumi.dtsi | 80 +++++++++++++++++++++++++++++++++++++++++ qcom/kera.dtsi | 87 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index d3592d6b..46558f5c 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &arch_timer { clock-frequency = <500000>; }; @@ -35,6 +38,83 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L6B>; + vdda-phy-max-microamp = <211860>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18330>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <1890>; + + /* Detect whether RH132 card based sequences to be used */ + qcom,soc_emulation_type_addr = <0x1fc8004>; + qcom,soc_emulation_type_bits = <32>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + rpm-level = <0>; + spm-level = <0>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L1D>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L3G>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + qcom,disable-lpm; + + status = "ok"; +}; + &usb0 { dwc3@a600000 { usb-phy = <&usb_emuphy>, <&usb_nop_phy>; diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d349e893..070e8c41 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Kera"; @@ -48,6 +49,7 @@ aliases { serial0 = &qupv3_se13_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ }; cpus { @@ -1712,6 +1714,91 @@ status = "disabled"; }; }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + /* set the dependency that smmu being probed before ufs */ + depends-on-supply = <&apps_smmu>; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + qcom,bypass-pbl-rst-wa; + qcom,max-cpus = <8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + }; }; #include "tuna-gdsc.dtsi" From c989bbec1eb306e33fb5683bb59db957bab620c8 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Thu, 24 Oct 2024 14:45:02 +0530 Subject: [PATCH 101/112] ARM: dts: msm: Add oemvm qrtr gunyah node for tuna Add the nodes for enable qrtr communication between primary vm and oemvm on tuna. This adds platform devices and vdevice descriptions to start the qrtr gunyah transport on both primary vm and oemvm device trees. This also adds the device tree node to configure qrtr as node id 21 on oem vm. Change-Id: I8697478e2e1b8269aa3b93f940a8c98f03b7c9b2 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna-oemvm.dtsi | 21 +++++++++++++++++++++ qcom/tuna.dtsi | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 96d6d622..103554ce 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -157,6 +157,17 @@ }; }; + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x8>; + allocate-base; + }; + }; + vrtc { vdevice-type = "vrtc-pl031"; peer-default; @@ -239,6 +250,16 @@ compatible = "qcom,smcinvoke"; }; + qcom,qrtr { + compatible = "qcom,qrtr"; + qcom,node-id = <21>; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <8>; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <512>; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index ff413ab8..dd5b85ca 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2519,6 +2519,14 @@ }; }; + + qcom,qrtr-gunyah-oemvm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <8>; + peer-name = <4>; + }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { size = <0x4000>; gunyah-label = <0x11>; From a89f3f4af9d5b5c8783121a37db3a69acf47f757 Mon Sep 17 00:00:00 2001 From: Pranav Mahesh Phansalkar Date: Thu, 24 Oct 2024 14:48:59 +0530 Subject: [PATCH 102/112] ARM: dts: msm: Add GLINK PKT nodes for tuna GLINK PKT provides a userspace interface to RPMSG GLINK through character device node. Add the nodes and corresponding channel devices to enable GLINK communication from userspace. Change-Id: Ie880b3806843fcf57fbb2f77a2d77e24ee7359b6 Signed-off-by: Pranav Mahesh Phansalkar --- qcom/tuna.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index dd5b85ca..05e3e8b2 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -1140,6 +1140,66 @@ }; }; + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-qmc-dma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_dma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-qmc-cma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_cma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-xpan_control { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "bt_cp_ctrl"; + qcom,glinkpkt-dev-name = "bt_cp_ctrl"; + }; + }; + sys-pm-vx@c320000 { compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna"; reg = <0xc320000 0x400>; From 8046b8d9855fc7918f31f9344a93dc806bfac926 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Mon, 7 Oct 2024 11:27:02 +0530 Subject: [PATCH 103/112] bindings: usb: Add support for voting refgen LDO(s) Some target require refgen to operate. For this an additional ldo which will be exposed and the driver need to vote for proper phy functionality. Add a phandle which will be used in the driver to identify the ldo and vote accordingly. Change-Id: I15b3bcb031cefe037fbb0364bfb7b87d26489006 Signed-off-by: Udipto Goswami --- bindings/usb/qcom,usb-snps-eusb2-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/usb/qcom,usb-snps-eusb2-phy.yaml b/bindings/usb/qcom,usb-snps-eusb2-phy.yaml index ec68957a..c2a9ecfe 100644 --- a/bindings/usb/qcom,usb-snps-eusb2-phy.yaml +++ b/bindings/usb/qcom,usb-snps-eusb2-phy.yaml @@ -71,6 +71,11 @@ properties: phandle to eUSB2 repeater for enforcing probe ordering for eUSB2 repeater and eUSB2 PHY driver. + vdd_refgen-supply: + description: | + phandle to vote for additional refgen ldo. This is generally board/target + specific. + required: - compatible - reg From 834a48ef49f412e2ab5d1fc7b1f284aacfcf215e Mon Sep 17 00:00:00 2001 From: Satya Priya Kakitapalli Date: Thu, 26 Sep 2024 11:02:07 +0530 Subject: [PATCH 104/112] dt-bindings: clock: Add support for interconnect for sdxbaagha Add support for interconnect for sdxbaagha platform. Change-Id: Ia59ecee142ff7bc4583e44b1e92a6bdcb592a337 Signed-off-by: Satya Priya Kakitapalli --- bindings/interconnect/qcom,rpmh.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index 15d8319a..bd6e5ae7 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -89,6 +89,14 @@ properties: - qcom,sdx65-mc-virt - qcom,sdx65-mem-noc - qcom,sdx65-system-noc + - qcom,sdxbaagha-aggre_noc, + - qcom,sdxbaagha-cnoc_main, + - qcom,sdxbaagha-dc_noc, + - qcom,sdxbaagha-mc_virt, + - qcom,sdxbaagha-clk_virt, + - qcom,sdxbaagha-pcie_anoc, + - qcom,sdxbaagha-mem_noc, + - qcom,sdxbaagha-system_noc, - qcom,sm8150-aggre1-noc - qcom,sm8150-aggre2-noc - qcom,sm8150-camnoc-noc From e66fb5dbe0e1495505793875e882cad7f5e2ebbe Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Fri, 25 Oct 2024 14:03:20 +0530 Subject: [PATCH 105/112] ARM: dts: msm: Add debug related nodes for Tuna VM Add dmesg dumper and gunyah panic notifier nodes for Tuna VM. Change-Id: Ibd9b5add353457fe183b2ae757c10ff8770728da Signed-off-by: Hrishabh Rajput --- qcom/tuna-vm.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 18 +++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 19fda190..80dc0c3c 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -53,6 +53,29 @@ }; }; + dmesg-dump { + compatible = "qcom,dmesg-dump"; + gunyah-label = <7>; + ddump-pubkey-size = <270>; + ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2 + 0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96 + 0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc + 0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7 + 0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e + 0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d + 0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b + 0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0 + 0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27 + 0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31 + 0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79 + 0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd + 0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0 + 0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf + 0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac + 0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50 + 0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>; + }; + qcom,vm-config { compatible = "qcom,vm-1.0"; vm-type = "aarch64-guest"; @@ -200,6 +223,28 @@ qcom,label = <0x0000001>; }; + ddump-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/ddump-shm"; + push-compatible = "qcom,ddump-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x7>; + allocate-base; + }; + }; + + gunyah-panic-notifier-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/gpn-shm"; + push-compatible = "qcom,gunyah-panic-gen"; + peer-default; + memory { + qcom,label = <0x9>; + allocate-base; + }; + }; + gpiomem0 { vdevice-type = "iomem"; patch = "/soc/tlmm-vm-mem-access"; @@ -358,6 +403,11 @@ dma-coherent; }; + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + gunyah-label = <9>; + }; + qti,smmu-proxy-display-cb { compatible = "smmu-proxy-cb"; qti,cb-id = ; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index d51d206e..d9ef7bd6 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2651,6 +2651,24 @@ }; }; + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + qcom,primary-vm; + gunyah-label = <9>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + + dmesg-dump { + compatible = "qcom,dmesg-dump"; + qcom,primary-vm; + gunyah-label = <7>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + mmio_sram: mmio-sram@17D09400 { #address-cells = <2>; #size-cells = <2>; From 1ee0d138daa9c6d0d2342554ecc170de3ac3965a Mon Sep 17 00:00:00 2001 From: Hrishabh Rajput Date: Fri, 25 Oct 2024 14:46:44 +0530 Subject: [PATCH 106/112] ARM: dts: msm: Add test nodes for Tuna VMs Add test nodes for Tuna Trusted VM and OEMVM. Change-Id: I9b7fe8d547f764e5917e48ef36f9727018a8fb79 Signed-off-by: Hrishabh Rajput --- qcom/tuna-oemvm.dtsi | 57 ++++++++++++++++++++++++++++++++++++++++++++ qcom/tuna-vm.dtsi | 56 +++++++++++++++++++++++++++++++++++++++++++ qcom/tuna.dtsi | 43 +++++++++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 96d6d622..55c3eb52 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -171,6 +171,38 @@ peer-default; qcom,label = <0x000000C>; }; + + test-dbl-oemvm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-oemvm"; + qcom,label = <0x5>; + peer-default; + }; + + test-dbl-oemvm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-oemvm-source"; + qcom,label = <0x5>; + peer-default; + }; + + test-msgq-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x5>; + peer-default; + }; + + test-large-dmabuf-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xe>; + peer-default; + }; }; }; @@ -235,6 +267,31 @@ qcom,block-size = <0x400000>; }; + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; }; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index 80dc0c3c..9288da4e 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -257,6 +257,37 @@ }; }; + test-dbl-tuivm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-tuivm"; + qcom,label = <0x4>; + peer-default; + }; + + test-dbl-tuivm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-tuivm-source"; + qcom,label = <0x4>; + peer-default; + }; + + test-msgq-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x4>; + peer-default; + }; + + test-large-dmabuf-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xd>; + peer-default; + }; }; }; @@ -408,6 +439,31 @@ gunyah-label = <9>; }; + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + qti,smmu-proxy-display-cb { compatible = "smmu-proxy-cb"; qti,cb-id = ; diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index d9ef7bd6..e07adf2e 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -2651,6 +2651,49 @@ }; }; + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + qcom,primary; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + qcom,primary; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + qcom,primary; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + qcom,primary; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,primary; + }; + qcom,gunyah-panic-notifier { compatible = "qcom,gh-panic-notifier"; qcom,primary-vm; From 4ba1b0c54502006589d3eec025765709358053eb Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Fri, 4 Oct 2024 13:52:17 +0530 Subject: [PATCH 107/112] ARM: dts: qcom: Add NVMEM cell for FMD_CONT_AFTER_PON for PMK8550 Add NVMEM cell for FMD_CONT_AFTER_PON to provide the option to prevent FMD(find-my-device) feature disablement on PON trigger. 0 - Disable FMD feature on PON. 1 - Keep FMD feature enabled on PON. Change-Id: I5e5386867546aacf526fe7be65e1e1e1ece30ffc Signed-off-by: Kamal Wadhwa --- qcom/pmk8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi index 21ddcae1..6284319f 100644 --- a/qcom/pmk8550.dtsi +++ b/qcom/pmk8550.dtsi @@ -58,6 +58,10 @@ reg = <0x9a 0x1>; }; + fmd_cont_after_pon: fmd-cont-after-pon@9c { + reg = <0x9c 0x1>; + }; + fmd_chg_pon: fmd-chg-pon@9f { reg = <0x9f 0x1>; }; From 5f802658c4b8a5daa8d8090654753edf3f10e0a5 Mon Sep 17 00:00:00 2001 From: Kartikey Arora Date: Fri, 25 Oct 2024 17:42:53 +0530 Subject: [PATCH 108/112] ARM: dts: msm: Update wpss rproc node for kera Update wpss rproc node for kera with modified WPSS image address in PIL region. Change-Id: Ib6c22e6f35dd3b9e3dcb6165ad4f969a4f5aa245 CRs-Fixed: 3959798 Signed-off-by: Kartikey Arora --- qcom/kera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index d349e893..6218255f 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -1057,9 +1057,9 @@ nvmem-cell-names = "feat_conf6"; }; - wpss_pas: remoteproc-wpss@a3500000 { + wpss_pas: remoteproc-wpss@97000000 { compatible = "qcom,kera-wpss-pas"; - reg = <0xa3500000 0x10000>; + reg = <0x97000000 0x10000>; status = "ok"; memory-region = <&wpss_mem>; From 5575062d334a10009bd27dbd09b9b1b13fd34777 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 25 Oct 2024 17:51:07 +0530 Subject: [PATCH 109/112] ARM: dts: msm: Add interconnect vote for KERA remote processors As now interconnect changes are in place, add interconnect voting for remote processors. Change-Id: I8a1016f0fe760b49aa88dd51bbb00ef7fdf785fb Signed-off-by: Mukesh Ojha --- qcom/kera.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index e930ebca..e9b492b6 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -452,6 +452,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "adsp.mdt", "adsp_dtb.mdt"; @@ -529,6 +531,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "cdsp.mdt", "cdsp_dtb.mdt"; @@ -606,6 +610,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "modem.mdt", "modem_dtb.mdt"; From e4dd39189ca5681d37247fd1fdb865a92cc18530 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Tue, 11 Oct 2022 15:58:25 +0530 Subject: [PATCH 110/112] dt-bindings: pinctrl: qcom-pmic-gpio: Add PMX35 bindings update PMIC GPIO binding documentation to include compatible string for PMX35 PMIC. Change-Id: Ifeea36b51f12e189bce0ed97664e6d3b3f51a6ed Signed-off-by: Kavya Nunna Signed-off-by: Satya Priya Kakitapalli --- bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/pinctrl/qcom,pmic-gpio.yaml b/bindings/pinctrl/qcom,pmic-gpio.yaml index 911034f9..12ba5c91 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -74,6 +74,7 @@ properties: - qcom,pmx55-gpio - qcom,pmx65-gpio - qcom,pmx75-gpio + - qcom,pmx35-gpio - qcom,pmxr2230-gpio - enum: @@ -187,6 +188,7 @@ allOf: - qcom,pm7325b-gpio - qcom,pm7550ba-gpio - qcom,pmi632-gpio + - qcom,pmx35-gpio then: properties: gpio-line-names: @@ -486,6 +488,7 @@ $defs: - gpio1-gpio2 for pmr735d - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) + - gpio1-gpio8 for pmx35 - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 and gpio11) - gpio1-gpio16 for pmx65 From 7e886b8d92535e6b5e112370a1ea9e4505ee6fd7 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Tue, 29 Oct 2024 11:58:25 +0530 Subject: [PATCH 111/112] ARM: dts: msm: Add clocks property for camera gdscs Add clocks property for camera gdscs. Change-Id: I02e3575b4cf4721648a1963027be3c9cad7aa1c6 Signed-off-by: Anaadi Mishra --- qcom/tuna.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 6c9968c9..70245e8c 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -3156,31 +3156,37 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_ofe_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; interconnect-names = "mmnoc"; From 54028a4bba2961e6a033696c54c4c6e7904a953b Mon Sep 17 00:00:00 2001 From: Shivendra Pratap Date: Wed, 16 Oct 2024 16:20:44 +0530 Subject: [PATCH 112/112] ARM: dts: qcom: Add support for platforms for Tuna MTP Add base device tree support for MTP harmonium and MTP NFC platforms for Tuna SoC. Change-Id: I4cef3297884dff5e7edee9121496c7284551c99c Signed-off-by: Shivendra Pratap --- qcom/Makefile | 2 ++ qcom/platform_map.bzl | 2 ++ qcom/tuna-mtp-kiwi-harmonium-overlay.dts | 18 ++++++++++++++++++ qcom/tuna-mtp-kiwi-harmonium.dtsi | 6 ++++++ qcom/tuna-mtp-nfc-overlay.dts | 18 ++++++++++++++++++ qcom/tuna-mtp-nfc.dtsi | 6 ++++++ 6 files changed, 52 insertions(+) create mode 100644 qcom/tuna-mtp-kiwi-harmonium-overlay.dts create mode 100644 qcom/tuna-mtp-kiwi-harmonium.dtsi create mode 100644 qcom/tuna-mtp-nfc-overlay.dts create mode 100644 qcom/tuna-mtp-nfc.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index bb164de8..6f922104 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -56,7 +56,9 @@ TUNA_BASE_DTB += tuna.dtb tuna7.dtb NOAPQ_TUNA_BOARDS += \ tuna-atp-overlay.dtbo \ tuna-cdp-overlay.dtbo \ + tuna-mtp-kiwi-harmonium-overlay.dtbo \ tuna-mtp-kiwi-overlay.dtbo \ + tuna-mtp-nfc-overlay.dtbo \ tuna-mtp-overlay.dtbo \ tuna-mtp-qmp1000-overlay.dtbo \ tuna-mtp-kiwi-pmd802x-overlay.dtbo \ diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index a7f9db89..95d31391 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -85,7 +85,9 @@ _platform_map = { }, {"name": "tuna-atp-overlay.dtbo"}, {"name": "tuna-cdp-overlay.dtbo"}, + {"name": "tuna-mtp-kiwi-harmonium-overlay.dtbo"}, {"name": "tuna-mtp-kiwi-overlay.dtbo"}, + {"name": "tuna-mtp-nfc-overlay.dtbo"}, {"name": "tuna-mtp-overlay.dtbo"}, {"name": "tuna-mtp-qmp1000-overlay.dtbo"}, {"name": "tuna-qrd-overlay.dtbo"}, diff --git a/qcom/tuna-mtp-kiwi-harmonium-overlay.dts b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts new file mode 100644 index 00000000..dfaff3ba --- /dev/null +++ b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-kiwi-harmonium.dtsi" +#include "tuna-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 3>; +}; diff --git a/qcom/tuna-mtp-kiwi-harmonium.dtsi b/qcom/tuna-mtp-kiwi-harmonium.dtsi new file mode 100644 index 00000000..37e840c1 --- /dev/null +++ b/qcom/tuna-mtp-kiwi-harmonium.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp-kiwi.dtsi" diff --git a/qcom/tuna-mtp-nfc-overlay.dts b/qcom/tuna-mtp-nfc-overlay.dts new file mode 100644 index 00000000..440dcc09 --- /dev/null +++ b/qcom/tuna-mtp-nfc-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-nfc.dtsi" +#include "tuna-pm7550ba-pmd802x.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + SN220/SN300 NFC"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 4>; +}; diff --git a/qcom/tuna-mtp-nfc.dtsi b/qcom/tuna-mtp-nfc.dtsi new file mode 100644 index 00000000..386415d7 --- /dev/null +++ b/qcom/tuna-mtp-nfc.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp.dtsi"