diff --git a/bindings/arm/msm/sys-pm-violators.yaml b/bindings/arm/msm/sys-pm-violators.yaml index a498fea3..3883054a 100644 --- a/bindings/arm/msm/sys-pm-violators.yaml +++ b/bindings/arm/msm/sys-pm-violators.yaml @@ -27,6 +27,7 @@ properties: - qcom,sys-pm-monaco-auto - qcom,sys-pm-sun - qcom,sys-pm-tuna + - qcom,sys-pm-kera reg: maxItems: 1 @@ -50,6 +51,7 @@ allOf: enum: - qcom,sys-pm-sun - qcom,sys-pm-tuna + - qcom,sys-pm-kera - qcom,sys-pm-pineapple - qcom,sys-pm-parrot - qcom,sys-pm-ravelin diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1a7c7670..1c8b8d47 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -20,9 +20,11 @@ properties: - qcom,sun-debugcc - qcom,parrot-debugcc - qcom,sdx75-debugcc + - qcom,sdxbaagha-debugcc - qcom,sm4450-debugcc - qcom,monaco-debugcc - qcom,tuna-debugcc + - qcom,kera-debugcc clocks: items: diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index ccdb4c98..2411e3c0 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -27,6 +27,7 @@ description: | dt-bindings/clock/qcom,gpucc-parrot.h dt-bindings/clock/qcom,gpucc-monaco.h dt-bindings/clock/qcom,gpucc-tuna.h + dt-bindings/clock/qcom,gpucc-kera.h properties: compatible: @@ -45,6 +46,7 @@ properties: - qcom,parrot-gpucc - qcom,monaco-gpucc - qcom,tuna-gpucc + - qcom,kera-gpucc clocks: items: diff --git a/bindings/clock/qcom,gx_clkctl.yaml b/bindings/clock/qcom,gx_clkctl.yaml index 0790d60d..c5964e57 100644 --- a/bindings/clock/qcom,gx_clkctl.yaml +++ b/bindings/clock/qcom,gx_clkctl.yaml @@ -15,12 +15,13 @@ description: | See also: dt-bindings/clock/qcom,gxclkctl-sun.h + dt-bindings/clock/qcom,gpucc-tuna.h properties: compatible: enum: - qcom,sun-gx_clkctl - + - qcom,tuna-gx_clkctl reg: maxItems: 1 diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml index 70fa6032..1b915c27 100644 --- a/bindings/clock/qcom,rpmhcc.yaml +++ b/bindings/clock/qcom,rpmhcc.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdx55-rpmh-clk - qcom,sdx65-rpmh-clk - qcom,sdx75-rpmh-clk + - qcom,sdxbaagha-rpmh-clk - qcom,sm4450-rpmh-clk - qcom,sm6350-rpmh-clk - qcom,sm8150-rpmh-clk diff --git a/bindings/clock/qcom,sdxbaagha-gcc.yaml b/bindings/clock/qcom,sdxbaagha-gcc.yaml new file mode 100644 index 00000000..7f4b09b6 --- /dev/null +++ b/bindings/clock/qcom,sdxbaagha-gcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sdxbaagha-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Global clock control module which supports the clocks, resets and + power domains on sdxbaagha + + See also: + - dt-bindings/clock/qcom,gcc-sdxbaagha.h + +properties: + compatible: + const: qcom,sdxbaagha-gcc + + clocks: + items: + - description: Board XO source + - description: Board active XO source + - description: PCIE Pipe clock source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: pcie_pipe_clk + - const: sleep_clk + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@80000 { + compatible = "qcom,sdxbaagha-gcc"; + reg = <0x80000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>,<&rpmhcc RPMH_CXO_CLK_A>, + <&pcie_pipe_clk>,<&sleep_clk>; + clock-names = "bi_tcxo","bi_tcxo_ao", + "pcie_pipe_clk","sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/input/qcom,hv-haptics.yaml b/bindings/input/qcom,hv-haptics.yaml index 70997a88..4eb33ab5 100644 --- a/bindings/input/qcom,hv-haptics.yaml +++ b/bindings/input/qcom,hv-haptics.yaml @@ -161,6 +161,13 @@ properties: method is used for LRA resonant frequency detection. type: boolean + qcom,hbst-ovp-trim: + description: | + Boolean flag indicating that the hBoost OVP trim PBS sequence would be + triggered during driver initialization. This is only applicable for HAP530_HV + haptics module. + type: boolean + patternProperties: ".*hap-swr-slave-reg$": description: | diff --git a/bindings/interconnect/qcom,rpmh.yaml b/bindings/interconnect/qcom,rpmh.yaml index 02e1536b..bd6e5ae7 100644 --- a/bindings/interconnect/qcom,rpmh.yaml +++ b/bindings/interconnect/qcom,rpmh.yaml @@ -89,6 +89,14 @@ properties: - qcom,sdx65-mc-virt - qcom,sdx65-mem-noc - qcom,sdx65-system-noc + - qcom,sdxbaagha-aggre_noc, + - qcom,sdxbaagha-cnoc_main, + - qcom,sdxbaagha-dc_noc, + - qcom,sdxbaagha-mc_virt, + - qcom,sdxbaagha-clk_virt, + - qcom,sdxbaagha-pcie_anoc, + - qcom,sdxbaagha-mem_noc, + - qcom,sdxbaagha-system_noc, - qcom,sm8150-aggre1-noc - qcom,sm8150-aggre2-noc - qcom,sm8150-camnoc-noc @@ -198,6 +206,20 @@ properties: - qcom,tuna-nsp_noc - qcom,tuna-pcie_anoc - qcom,tuna-system_noc + - qcom,kera-aggre1_noc + - qcom,kera-aggre2_noc + - qcom,kera-clk_virt + - qcom,kera-cnoc_cfg + - qcom,kera-cnoc_main + - qcom,kera-gem_noc + - qcom,kera-lpass_ag_noc + - qcom,kera-lpass_lpiaon_noc + - qcom,kera-lpass_lpicx_noc + - qcom,kera-mc_virt + - qcom,kera-mmss_noc + - qcom,kera-nsp_noc + - qcom,kera-pcie_anoc + - qcom,kera-system_noc '#interconnect-cells': true diff --git a/bindings/leds/backlight/qcom-spmi-wled.yaml b/bindings/leds/backlight/qcom-spmi-wled.yaml new file mode 100644 index 00000000..7abb1eac --- /dev/null +++ b/bindings/leds/backlight/qcom-spmi-wled.yaml @@ -0,0 +1,386 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/qcom-spmi-wled.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. WLED (White Light Emitting Diode) driver + +maintainers: + - Jishnu Prakash + +description: > + WLED (White Light Emitting Diode) driver is used for controlling display + backlight that is part of PMIC on Qualcomm Technologies, Inc. reference + platforms. The PMIC is connected to the host processor via SPMI bus. + +properties: + compatible: + enum: + - qcom,pmi8998-spmi-wled + - qcom,pm8150l-spmi-wled + - qcom,pm6150l-spmi-wled + - qcom,pm660l-spmi-wled + - qcom,pm7325b-spmi-wled + + reg: + minItems: 1 + maxItems: 2 + description: Base address and size of the WLED modules. + + reg-names: + $ref: /schemas/types.yaml#/definitions/string + description: | + Names associated with base addresses. should be + "wled-ctrl-base", "wled-sink-base". + + interrupts: + minItems: 1 + maxItems: 2 + description: | + Interrupts associated with WLED. Interrupts can be specified as per the encoding listed + under Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt. + + interrupt-names: + items: + - const: sc-irq + - const: ovp-irq + - const: pre-flash-irq + - const: flash-irq + + label: true + + default-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Brightness value on boot. Default is 2048. + For pmi8998, it is 0-4095. + For pm8150l, this can vary from 0-4095 or 0-32767 depending + on the brightness control mode. If CABC is enabled, 0-4095 + range is used. + + max-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum brightness level. Allowed values are + For pmi8998, it is 4095. + For pm8150l, this can be either 4095 or 32767. + If CABC is enabled, this is capped to 4095. + + qcom,fs-current-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + per-string full scale current limit in uA. value from + 0 to 30000 with 5000 uA resolution. + default is 25000 uA + + qcom,boost-current-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ILIM threshold in mA. values are 105, 280, 450, 620, 970, + 1150, 1300, 1500. + default is 970 mA + + qcom,switching-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Switching frequency in KHz. values are + 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, + 1600, 1920, 2400, 3200, 4800, 9600. + default is 800 KHz + + qcom,ovp: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Over-voltage protection limit in mV. values are 31100, + 29600, 19600, 18100. + default is 29600 mV + + qcom,string-cfg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Bit mask of the WLED strings. Bit 0 to 3 indicates strings + 0 to 3 respectively. WLED module has four strings of leds + numbered from 0 to 3. Each string of leds are operated + individually. Specify the strings using the bit mask. Any + combination of led strings can be used. + Default value is 15 (b1111). + + qcom,en-cabc: + type: boolean + description: | + Specify if cabc (content adaptive backlight control) is + needed. + + qcom,ext-pfet-sc-pro-en: + type: boolean + description: | + Specify if external PFET control for short circuit + protection is needed. This is not applicable for PM8150L. + + qcom,auto-calibration: + type: boolean + description: | + Enables auto-calibration of the WLED sink configuration. + + qcom,modulator-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Selects the modulator used for brightness modulation. + Allowed values are + 0 - Modulator A + 1 - Modulator B + If not specified, then modulator A will be used by default. + This property is applicable only to WLED5 peripheral. + + qcom,cabc-sel: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Selects the CABC pin signal used for brightness modulation. + Allowed values are + 0 - CABC disabled + 1 - CABC 1 + 2 - CABC 2 + 3 - External signal (e.g. LPG) is used for dimming + This property is applicable only to WLED5 peripheral. + + qcom,leds-per-string: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + If specified, can be used to calculate available current + during selfie flash operation. If not specified, available + current calculated is simply the configured threshold. + + io-channels: + maxItems: 3 + description: | + IIO channel specifiers for each name in io-channel-names. + + io-channel-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: | + Names of the IIO channels that are used by WLED. + For details about IIO bindings refer below + Documentation/devicetree/bindings/iio/iio-bindings.txt + + qcom,use-exp-dimming: + type: boolean + description: | + Specifies that exponential dimming lookup table values should be used. + + qcom,exp-dimming-map: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + It specifies a table of brightness values that can be programmed + into WLED_SINK for exponential dimming which provides smooth brightness + change. There should be exactly 256 values in the table and they should + be at most 15 bits long. This table would be used only if the + "qcom,use-exp-dimming" property is set. This feature is supported from + PM7325B onwards. + + qcom,slew-ramp-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Software brightness slew ramp time values in ms. This is supported from + PM7325B onwards. + Valid values are 2, 4, 8, 64, 128, 192, 256, 320, 384, 448, 512, 704, 896, + 1024, 2048, 4096. + default is 256 + +patternProperties: + "^wled_torch[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: Properties for wled_torch. + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "torch". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_torch" is used. + + qcom,wled-torch-fsc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch full scale current in mA. This configures the + maximum current allowed for torch device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 30 mA. + + qcom,wled-torch-step: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + + qcom,wled-torch-timer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED torch safety timer in ms. This configures the safety + timer to turn off torch automatically after timer expiry. + Allowed values are 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 1200 ms. + + + required: + - label + + "^wled_flash[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: wled_flash child subnode properties + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "flash". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_flash" is used. + + qcom,wled-flash-fsc: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash full scale current in mA. This configures the + maximum current allowed for flash device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 40 mA. + + qcom,wled-flash-step: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + + qcom,wled-flash-timer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WLED flash safety timer in ms. This configures the safety + timer to turn off flash automatically after timer expiry. + Allowed values are 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 100 ms. + + required: + - label + + "^wled_switch[0-9a-f]+$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: wled_switch child subnode properties + + properties: + label: + $ref: /schemas/types.yaml#/definitions/string + description: | + Should be "switch". + + qcom,default-led-trigger: + $ref: /schemas/types.yaml#/definitions/string + description: | + Name for LED trigger. If unspecified, "wled_switch" is used. + + required: + - label + +required: + - compatible + - reg + - reg-names + - label + +additionalProperties: false + +examples: + - | + #include + + qcom-wled@d800 { + compatible = "qcom,pmi8998-spmi-wled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd800 0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq", "ovp-irq"; + qcom,fs-current-limit = <25000>; + qcom,boost-current-limit = <970>; + qcom,switching-freq = <800>; + qcom,ovp = <29600>; + qcom,string-cfg = <15>; + }; + + - | + #include + #include + qcom-wled@d800 { + compatible = "qcom,pm8150l-spmi-wled"; + #address-cells = <2>; + #size-cells = <0>; + reg = <0xd800 0x100>, <0xd900 0x100>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + qcom,string-cfg = <7>; + + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>; + + io-channel-names = "rbatt", + "voltage_ocv", + "current_now"; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,wled-torch-fsc = <40>; + qcom,wled-torch-step = <300>; + qcom,wled-torch-timer = <600>; + }; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,wled-flash-fsc = <60>; + qcom,wled-flash-step = <100>; + qcom,wled-flash-timer = <200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + }; + + }; + + - | + #include + qcom,leds@d800 { + compatible = "qcom,pm660l-spmi-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + linux,name = "wled"; + linux,default-led-trigger = "bkl-trigger"; + + }; diff --git a/bindings/pinctrl/qcom,kera-vm-tlmm.yaml b/bindings/pinctrl/qcom,kera-vm-tlmm.yaml new file mode 100644 index 00000000..92cd32ad --- /dev/null +++ b/bindings/pinctrl/qcom,kera-vm-tlmm.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kera-vm-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kera VM TLMM block + +maintainers: + - Murali Nalajala + - Satya Durga Srinivasu Prabhala + +description: | + This binding describes the Top Level Mode Multiplexer block for VM. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kera-vm-tlmm + + reg: + maxItems: 1 + + interrupts-extended: true + interrupt-controller: true + '#interrupt-cells': true + + gpio-controller: true + '#gpio-cells': true + gpio-ranges: true + gpios: + description: array of gpio pin number required by VM TLMM clients + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-kera-vm-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kera-vm-tlmm-state" + additionalProperties: false + +$defs: + qcom-kera-vm-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3, + atest_char_start, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1, + audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk, + cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0, + cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4, + cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2, + cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0, + cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, + gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0, + i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0, + i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0, + i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0, + i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0, + i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, + i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1, + mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, + mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, + phase_flag14, phase_flag15, phase_flag16, phase_flag17, + phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, + phase_flag25, phase_flag26, phase_flag27, phase_flag28, + phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2, + qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3, + qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4, + qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2, + qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3, + qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0, + qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1, + qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2, + qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3, + qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4, + qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2, + qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, + qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6, + qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0, + qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40, + sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, + tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, + vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + allOf: + - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + - if: + properties: + pins: + pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + then: + required: + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,kera-vm-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = ; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup1_se7_l0"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup1_se7_l1"; + bias-disable; + }; + }; + }; +... diff --git a/bindings/pinctrl/qcom,pmic-gpio.yaml b/bindings/pinctrl/qcom,pmic-gpio.yaml index 7fda52d1..12ba5c91 100644 --- a/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -28,6 +28,7 @@ properties: - qcom,pm6450-gpio - qcom,pm7250b-gpio - qcom,pm7325-gpio + - qcom,pm7325b-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio - qcom,pm8008-gpio @@ -73,6 +74,7 @@ properties: - qcom,pmx55-gpio - qcom,pmx65-gpio - qcom,pmx75-gpio + - qcom,pmx35-gpio - qcom,pmxr2230-gpio - enum: @@ -183,8 +185,10 @@ allOf: - qcom,pm8350b-gpio - qcom,pm8550ve-gpio - qcom,pm8950-gpio + - qcom,pm7325b-gpio - qcom,pm7550ba-gpio - qcom,pmi632-gpio + - qcom,pmx35-gpio then: properties: gpio-line-names: @@ -441,6 +445,7 @@ $defs: - gpio1-gpio9 for pm6450 - gpio1-gpio12 for pm7250b - gpio1-gpio10 for pm7325 + - gpio1-gpio8 for pm7325b - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 - gpio1-gpio2 for pm8008 @@ -483,6 +488,7 @@ $defs: - gpio1-gpio2 for pmr735d - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) + - gpio1-gpio8 for pmx35 - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 and gpio11) - gpio1-gpio16 for pmx65 diff --git a/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml index 4b7cbd70..4048d81c 100644 --- a/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml +++ b/bindings/regulator/qcom,qpnp-lcdb-regulator.yaml @@ -33,6 +33,11 @@ properties: to be enabled only on platforms where voltage needs to be ramped up with multiple steps. + qcom,ncp-symmetry: + type: boolean + description: Enabling this will make NCP voltage follow LDO voltage + directly. + qcom,pwrdn-delay-ms: description: Required to control the LDO power down delay. Possible values are 0, 1, 4, 8. @@ -44,13 +49,30 @@ properties: qcom,pwrup-config: $ref: /schemas/types.yaml#/definitions/uint32 description: Controls the order of powering up BOOST, LDO AND NCP - blocks. Appilcable for PM7325B. Possible values are 0, 1, 2, 3, 4. + blocks. Applicable for PM7325B. Possible values are 0, 1, 2, 3, 4. 0 - Boost, LDO, NCP 1 - Boost, LDO 2 - Boost, NCP 3 - Boost only 4 - Boost, NCP, LDO + qcom,high-p2-blank-time-ns: + description: Controls the higher clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + + qcom,low-p2-blank-time-ns: + description: Controls the lower clamp threshold for p2 minimum on time. + Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159, + 189, 220, 250. + + qcom,mpc-current-thr-ma: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Controls the mpc threshold for inductor current after start up + is done. Applicable for PM7325B. Possible values are 160, 200, 240, + 280, 320, 360, 400, 440. + + qcom,ttw-enable: type: boolean description: Touch to wake-up support enabled. diff --git a/bindings/remoteproc/qcom,adsp.yaml b/bindings/remoteproc/qcom,adsp.yaml index e5b00374..191ee125 100644 --- a/bindings/remoteproc/qcom,adsp.yaml +++ b/bindings/remoteproc/qcom,adsp.yaml @@ -79,6 +79,7 @@ properties: - qcom,monaco-modem-pas - qcom,monaco-adsp-pas - qcom,tuna-wpss-pas + - qcom,kera-wpss-pas reg: maxItems: 1 diff --git a/bindings/soc/qcom/qcom,pcie-pdc.yaml b/bindings/soc/qcom/qcom,pcie-pdc.yaml index 8010730e..37a32c9f 100644 --- a/bindings/soc/qcom/qcom,pcie-pdc.yaml +++ b/bindings/soc/qcom/qcom,pcie-pdc.yaml @@ -21,6 +21,7 @@ properties: - qcom,sun-pcie-pdc - qcom,pineapple-pcie-pdc - qcom,cliffs-pcie-pdc + - qcom,tuna-pcie-pdc - qcom,pcie-pdc reg: diff --git a/bindings/soc/qcom/qcom-stats.yaml b/bindings/soc/qcom/qcom-stats.yaml index 64948af2..61c21ff3 100644 --- a/bindings/soc/qcom/qcom-stats.yaml +++ b/bindings/soc/qcom/qcom-stats.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/soc/qcom/qcom-stats.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Technologies, Inc. (QTI) Stats bindings +title: Qualcomm Technologies, Inc. SoC LPM stats maintainers: - Maulik Shah @@ -25,6 +25,7 @@ properties: - qcom,rpmh-stats-v4 - qcom,sdm845-rpmh-stats - qcom,rpm-stats + - qcom,rpm-stats-v2 # For older RPM firmware versions with fixed offset for the sleep stats - qcom,apq8084-rpm-stats - qcom,msm8226-rpm-stats diff --git a/bindings/thermal/qcom-bcl-pmic5.yaml b/bindings/thermal/qcom-bcl-pmic5.yaml index a0c67869..5bfb1a83 100644 --- a/bindings/thermal/qcom-bcl-pmic5.yaml +++ b/bindings/thermal/qcom-bcl-pmic5.yaml @@ -23,8 +23,10 @@ description: | properties: compatible: - const: qcom,bcl-v5 description: msm battery state of charge device + items: + - const: qcom,bcl-v5 + - const: qcom,pm8550-bcl-v5 reg: maxItems: 1 @@ -96,3 +98,16 @@ examples: qcom,bcl-mon-vbat-only; qcom,pmic7-threshold; }; + + bcl@4700 { + compatible = "qcom,pm8550-bcl-v5"; + reg = <0x4700 0x100>; + interrupts = <0x1 0x47 0x0 IRQ_TYPE_NONE>, + <0x1 0x47 0x1 IRQ_TYPE_NONE>, + <0x1 0x47 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-lvl0", + "bcl-lvl1", + "bcl-lvl2"; + qcom,pmic7-threshold; + #thermal-sensor-cells = <1>; + }; diff --git a/bindings/usb/qcom,usb-snps-eusb2-phy.yaml b/bindings/usb/qcom,usb-snps-eusb2-phy.yaml index ec68957a..c2a9ecfe 100644 --- a/bindings/usb/qcom,usb-snps-eusb2-phy.yaml +++ b/bindings/usb/qcom,usb-snps-eusb2-phy.yaml @@ -71,6 +71,11 @@ properties: phandle to eUSB2 repeater for enforcing probe ordering for eUSB2 repeater and eUSB2 PHY driver. + vdd_refgen-supply: + description: | + phandle to vote for additional refgen ldo. This is generally board/target + specific. + required: - compatible - reg diff --git a/qcom/Makefile b/qcom/Makefile index 3f8b30be..6f922104 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -56,7 +56,9 @@ TUNA_BASE_DTB += tuna.dtb tuna7.dtb NOAPQ_TUNA_BOARDS += \ tuna-atp-overlay.dtbo \ tuna-cdp-overlay.dtbo \ + tuna-mtp-kiwi-harmonium-overlay.dtbo \ tuna-mtp-kiwi-overlay.dtbo \ + tuna-mtp-nfc-overlay.dtbo \ tuna-mtp-overlay.dtbo \ tuna-mtp-qmp1000-overlay.dtbo \ tuna-mtp-kiwi-pmd802x-overlay.dtbo \ @@ -235,6 +237,14 @@ dtb-y += $(tuna_tuivm-dtb-y) endif endif +ifeq ($(CONFIG_ARCH_KERA), y) +ifeq ($(CONFIG_ARCH_QTI_VM), y) +kera_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kera-vm-rumi.dtb \ + kera-oemvm-rumi.dtb +dtb-y += $(kera_tuivm-dtb-y) +endif +endif + MONACO_BASE_DTB += monaco.dtb monacop.dtb MONACO_BOARDS += \ diff --git a/qcom/kera-oemvm-rumi.dts b/qcom/kera-oemvm-rumi.dts new file mode 100644 index 00000000..8d4a30b6 --- /dev/null +++ b/qcom/kera-oemvm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-oemvm.dtsi" +#include "kera-oemvm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera OEMVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/kera-oemvm-rumi.dtsi b/qcom/kera-oemvm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/kera-oemvm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/kera-oemvm.dtsi b/qcom/kera-oemvm.dtsi new file mode 100644 index 00000000..cd6f0bf4 --- /dev/null +++ b/qcom/kera-oemvm.dtsi @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <659 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,oemvm"; + qcom,pasid = <0x0 0x22>; + qcom,qtee-config-info = "p=3,9,39,7C,8F,97,159,7F1,CDF;"; + qcom,secdomain-ids = <49>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/oemvm"; + vm-guid = "847bfe26-0b12-5728-812a-06103f6bdec0"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x0 0x0>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x16>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xFFEFC000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x13>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xFFF00000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x14>; + #address-cells = <0x2>; + base = <0x0 0xFFF04000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <512>; + qcom,support-hypervisor; + }; +}; diff --git a/qcom/kera-pmiv0102.dtsi b/qcom/kera-pmiv0102.dtsi new file mode 100644 index 00000000..94ec6fbd --- /dev/null +++ b/qcom/kera-pmiv0102.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-pmiv0108.dtsi" + +&pmiv010x_amoled { + status= "ok"; +}; + +&pmiv010x_amoled_ecm { + status = "ok" +}; + + diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi index 427aea63..a0c6bbdf 100644 --- a/qcom/kera-reserved-memory.dtsi +++ b/qcom/kera-reserved-memory.dtsi @@ -65,6 +65,11 @@ reg = <0x0 0x81ce4000 0x0 0x10000>; }; + chipinfo_mem: chipinfo_region@81cf4000 { + no-map; + reg = <0x0 0x81cf4000 0x0 0x1000>; + }; + smem_mem: smem_region@81d00000 { compatible = "qcom,smem"; reg = <0x0 0x81d00000 0x0 0x200000>; diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index d3592d6b..4a1f5de8 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -3,6 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &arch_timer { clock-frequency = <500000>; }; @@ -35,6 +38,83 @@ }; }; +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&L6B>; + vdda-phy-max-microamp = <211860>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&L4B>; + vdda-pll-max-microamp = <18330>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&L2B>; + vdda-qref-max-microamp = <1890>; + + /* Detect whether RH132 card based sequences to be used */ + qcom,soc_emulation_type_addr = <0x1fc8004>; + qcom,soc_emulation_type_bits = <32>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + rpm-level = <0>; + spm-level = <0>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L1D>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L3G>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&S2B>; + qcom,vccq-parent-max-microamp = <210000>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + + qcom,disable-lpm; + + status = "ok"; +}; + &usb0 { dwc3@a600000 { usb-phy = <&usb_emuphy>, <&usb_nop_phy>; @@ -42,3 +122,39 @@ maximum-speed = "high-speed"; }; }; + +&SILVER_OFF { + status = "disabled"; +}; + +&SILVER_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_OFF { + status = "disabled"; +}; + +&GOLD_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_RAIL_OFF { + status = "disabled"; +}; + +&CLUSTER_PWR_DN { + status = "disabled"; +}; + +&CX_RET { + status = "disabled"; +}; + +&APSS_OFF { + status = "disabled"; +}; diff --git a/qcom/kera-vm-rumi.dts b/qcom/kera-vm-rumi.dts new file mode 100644 index 00000000..6c653ef1 --- /dev/null +++ b/qcom/kera-vm-rumi.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "kera-vm.dtsi" +#include "kera-vm-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/kera-vm-rumi.dtsi b/qcom/kera-vm-rumi.dtsi new file mode 100644 index 00000000..7cb42305 --- /dev/null +++ b/qcom/kera-vm-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&arch_timer { + clock-frequency = <500000>; +}; diff --git a/qcom/kera-vm.dtsi b/qcom/kera-vm.dtsi new file mode 100644 index 00000000..5ae595f2 --- /dev/null +++ b/qcom/kera-vm.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + qcom,msm-id = <659 0x10000>; + interrupt-parent = <&vgic>; + + chosen { + bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce"; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + }; + + CPU1: cpu@100 { + compatible = "arm,armv8"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + cpu-idle-states = <&CPU_PWR_DWN + &CLUSTER_PWR_DWN>; + + }; + }; + + idle-states { + CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + + CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */ + compatible = "arm,idle-state"; + status = "disabled"; + }; + }; + + qcom,vm-config { + compatible = "qcom,vm-1.0"; + vm-type = "aarch64-guest"; + boot-config = "fdt,unified"; + os-type = "linux"; + kernel-entry-segment = "kernel"; + kernel-entry-offset = <0x0 0x0>; + vendor = "QTI"; + image-name = "qcom,trustedvm"; + qcom,pasid = <0x0 0x1c>; + qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;"; + qcom,secdomain-ids = <45>; + qcom,primary-vm-index = <0>; + vm-uri = "vmuid/trusted-ui"; + vm-guid = "598085da-c516-5b25-a9c1-927a02819770"; + qcom,sensitive; + + vm-attrs = "context-dump", "crash-restart"; + + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. + * QUP1_SE4: GPII5 : IRQ_316 + * QUP2_SE7: GPII5 : IRQ_625 + */ + gic-irq-ranges = <316 316 + 625 625 /* PVM->SVM IRQ transfer */ + 279 279>; + + memory { + #address-cells = <0x2>; + #size-cells = <0x0>; + /* + * IPA address linux image is loaded at. Must be within + * first 1GB due to memory hotplug requirement. + */ + base-address = <0x0 0x88800000 >; + }; + + segments { + config_cpio = <2>; + }; + + vcpus { + config = "/cpus"; + affinity = "proxy"; + affinity-map = <0x0 0x0>; + sched-priority = <0>; /* relative to PVM */ + sched-timeslice = <2000>; /* in ms */ + }; + + interrupts { + config = &vgic; + }; + + vdevices { + generate = "/hypervisor"; + + minidump { + vdevice-type = "minidump"; + push-compatible = "qcom,minidump_rm"; + minidump_allowed; + }; + + rm-rpc { + vdevice-type = "rm-rpc"; + generate = "/hypervisor/qcom,resource-mgr"; + console-dev; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + qcom,label = <0x1>; + }; + + virtio-mmio@0 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x1>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x0>; + memory { + qcom,label = <0x11>; //for persist.img + #address-cells = <0x2>; + base = <0x0 0xDA6F8000>; + }; + }; + + virtio-mmio@1 { + vdevice-type = "virtio-mmio"; + generate = "/virtio-mmio"; + peer-default; + vqs-num = <0x2>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x4000>; + memory { + qcom,label = <0x10>; //for system.img + #address-cells = <0x2>; + base = <0x0 0xDA6FC000>; + }; + }; + + virtio-mmio@2 { + vdevice-type = "virtio-mmio"; + patch = "/soc/virtio-mmio"; + peer-default; + vqs-num = <0x3>; + push-compatible = "virtio,mmio"; + dma-coherent; + dma_base = <0x0 0x8000>; + memory { + qcom,label = <0x15>; //for virtio-vsock + #address-cells = <0x2>; + base = <0x0 0xDA700000>; + }; + }; + + swiotlb-shm { + vdevice-type = "shm"; + generate = "/swiotlb"; + push-compatible = "swiotlb"; + peer-default; + dma_base = <0x0 0x14000>; + memory { + qcom,label = <0x12>; + #address-cells = <0x2>; + base = <0x0 0xDA70c000>; + }; + }; + + vrtc { + vdevice-type = "vrtc-pl031"; + peer-default; + allocate-base; + }; + + }; + }; + + firmware: firmware { + qcom_scm: qcom_scm { + compatible = "qcom,scm"; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + virtio-mmio { + wakeup-source; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + vgic: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <0x3>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + always-on; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,custom-bridge-size = <64>; + qcom,support-hypervisor; + }; +}; + +#include "msm-arm-smmu-kera-vm.dtsi" diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi index 53f08502..7a61f8d0 100644 --- a/qcom/kera.dtsi +++ b/qcom/kera.dtsi @@ -13,8 +13,12 @@ #include #include #include +#include +#include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. Kera"; @@ -31,7 +35,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-2 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops"; stdout-path = "/soc/qcom,qupv3_1_geni_se@8c0000/qcom,qup_uart@894000:115200n8"; }; @@ -39,12 +43,20 @@ ddr-regions { }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x0>; + granule = <512>; + qcom,qmp = <&aoss_qmp>; + }; + firmware: firmware { qcom_scm: qcom_scm { }; }; aliases { serial0 = &qupv3_se13_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ }; cpus { @@ -55,8 +67,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -74,8 +88,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; }; @@ -83,8 +99,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "cache"; @@ -97,8 +115,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "cache"; @@ -111,8 +131,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "cache"; @@ -125,8 +147,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "cache"; @@ -139,8 +163,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "cache"; @@ -153,8 +179,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; - enable-method = "spin-table"; /* TODO: Update to psci */ - cpu-release-addr = <0x0 0xE3940000>; + enable-method = "psci"; + cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "cache"; @@ -204,6 +232,97 @@ }; }; + idle-states { + entry-method = "psci"; + + SILVER_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <250>; + exit-latency-us = <900>; + min-residency-us = <3200>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_RAIL_OFF: silver-cluster0-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF: gold-cluster1-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_PLUS_OFF: gold-plus-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <450>; + exit-latency-us = <1200>; + min-residency-us = <6230>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_PLUS_RAIL_OFF: gold-plus-cluster3-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41001344>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + arm,psci-suspend-param = <0x4100b344>; + }; + }; + soc: soc { }; hypervisor: hypervisor { @@ -267,6 +386,56 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>; + }; + }; + intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -351,6 +520,16 @@ qcom,vmid-cp-camera-preview-ro; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "supplier"; + qcom,vmid = <3>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + }; + apps_rsc: rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; @@ -362,6 +541,7 @@ interrupts = , , ; + power-domains = <&CLUSTER_PD>; apps_rsc_drv2: drv@2 { qcom,drv-id = <2>; @@ -374,6 +554,10 @@ , ; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; }; @@ -401,7 +585,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,kera-pdc", "qcom,pdc"; - reg = <0xb220000 0x10000>, <0x17c000f0 0x60>; + reg = <0xb220000 0x10000>, <0x174000f0 0x64>; qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, <10 230 1>, <11 724 1>, <12 716 1>, <13 727 1>, <14 720 1>, <15 726 1>, @@ -426,6 +610,11 @@ interrupt-controller; }; + adsp_sleepmon: adsp-sleepmon { + compatible = "qcom,adsp-sleepmon"; + qcom,rproc-handle = <&adsp_pas>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,kera-adsp-pas"; reg = <0x03000000 0x10000>; @@ -441,6 +630,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "adsp.mdt", "adsp_dtb.mdt"; @@ -464,6 +655,42 @@ /* Outputs to turing */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_adsp_glink: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,net-id = <2>; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + + qcom,no-wake-svc = <0x190>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3 + 0x2000 1>; + }; + }; }; cdsp_pas: remoteproc-cdsp@32300000 { @@ -482,6 +709,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "cdsp.mdt", "cdsp_dtb.mdt"; @@ -506,6 +735,42 @@ /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; + + remoteproc_cdsp_glink: glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12 + 0xF00 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-cores = <0 1>; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; }; modem_pas: remoteproc-mss@04080000 { @@ -523,6 +788,8 @@ qcom,qmp = <&aoss_qmp>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "crypto_ddr"; firmware-name = "modem.mdt", "modem_dtb.mdt"; @@ -547,6 +814,45 @@ /* Outputs to mss */ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + + glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + }; + }; + + sys-pm-vx@c320000 { + compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kera"; + reg = <0xc320000 0x400>; + qcom,qmp = <&aoss_qmp>; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; }; tlmm: pinctrl@f000000 { @@ -629,6 +935,12 @@ cap-based-alloc-and-pwr-collapse; }; + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + qcom,gic-class0-cpus = <&CPU0 &CPU1 &CPU2>; + qcom,gic-class1-cpus = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; + }; + tcsr: syscon@1fc0000 { compatible = "syscon"; reg = <0x1fc0000 0x30000>; @@ -758,6 +1070,28 @@ }; }; + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + qcom,smp2p-soccp { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; @@ -906,6 +1240,55 @@ #size-cells = <1>; read-only; ranges; + feat_conf6: feat_conf6@0118 { + reg = <0x0118 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf6>; + nvmem-cell-names = "feat_conf6"; + }; + + wpss_pas: remoteproc-wpss@97000000 { + compatible = "qcom,kera-wpss-pas"; + reg = <0x97000000 0x10000>; + status = "ok"; + + memory-region = <&wpss_mem>; + + firmware-name = "qca6750/wpss.mdt"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = ; + reg-names = "cx","mx"; + + qcom,qmp = <&aoss_qmp>; + + /* Inputs from wpss */ + interrupts-extended = <&intc GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 0>, + <&wpss_smp2p_in 2 0>, + <&wpss_smp2p_in 1 0>, + <&wpss_smp2p_in 3 0>, + <&wpss_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to wpss */ + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; }; clocks { @@ -974,29 +1357,106 @@ }; cambistmclkcc: clock-controller@1760000 { - compatible = "qcom,dummycc"; - clock-output-names = "cambistmclkcc_clocks"; + compatible = "qcom,tuna-cambistmclkcc", "syscon"; + reg = <0x1760000 0x6000>; + reg-name = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>; + clock-names = "bi_tcxo", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x178b0098 0x4>, + <0x178c0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats-v4"; + reg = <0x0c3f0000 0x400>; + qcom,qmp = <&aoss_qmp>; + ss-name = "modem", "wpss", "adsp", "adsp_island", + "cdsp", "apss"; + }; + camcc: clock-controller@ade0000 { - compatible = "qcom,dummycc"; - clock-output-names = "camcc_clocks"; + compatible = "qcom,kera-camcc", "syscon"; + reg = <0xade0000 0x20000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; + dispcc_crm: syscon@af27800 { + compatible = "syscon"; + reg = <0xaf27800 0x2000>; + }; + dispcc: clock-controller@af00000 { - compatible = "qcom,dummycc"; - clock-output-names = "dispcc_clocks"; + compatible = "qcom,tuna-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; + qcom,disp_crm-crmc = <&dispcc_crm>; #clock-cells = <1>; #reset-cells = <1>; }; gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,kera-gcc", "syscon"; + reg = <0x100000 0x1f4200>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie_0_pipe_clk>, + <&pcie_1_pipe_clk>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "pcie_1_pipe_clk", + "sleep_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1009,25 +1469,585 @@ }; tcsrcc: clock-controller@1f40000 { - compatible = "qcom,dummycc"; - clock-output-names = "tcsrcc_clocks"; + compatible = "qcom,kera-tcsrcc", "syscon"; + reg = <0x1fbf000 0x20>; + reg-name = "cc_base"; #clock-cells = <1>; #reset-cells = <1>; }; videocc: clock-controller@aaf0000 { - compatible = "qcom,dummycc"; - clock-output-names = "videocc_clocks"; + compatible = "qcom,tuna-videocc", "syscon"; + reg = <0xaaf0000 0x10000>; + reg-name = "cc_base"; + vdd_mm-supply = <&VDD_CX_LEVEL>; + vdd_mxc-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk", + "iface"; #clock-cells = <1>; #reset-cells = <1>; }; + clk_virt: interconnect@0 { + compatible = "qcom,kera-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,kera-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,kera-cnoc_cfg"; + reg = <0x1600000 0x5200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,kera-cnoc_main"; + reg = <0x1500000 0x16080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,kera-system_noc"; + reg = <0x1680000 0x40000>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,kera-pcie_anoc"; + reg = <0x16c0000 0x11400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,kera-aggre1_noc"; + reg = <0x16e0000 0x16400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,kera-aggre2_noc"; + reg = <0x1700000 0x1f400>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,kera-mmss_noc"; + reg = <0x1780000 0x7d800>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,kera-gem_noc"; + reg = <0x24100000 0x163080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,kera-nsp_noc"; + reg = <0x320c0000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,kera-lpass_ag_noc"; + reg = <0x7e40000 0xe080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,kera-lpass_lpiaon_noc"; + reg = <0x7400000 0x19080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,kera-lpass_lpicx_noc"; + reg = <0x7420000 0x44080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + qcom,skip-qos; + }; + + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x11>; + }; + + trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x10>; + }; + + + trust_ui_vm_vsock_ring: trust_ui_vm_vsock_ring { + size = <0xc000>; + gunyah-label = <0x15>; + }; + + trust_ui_vm_swiotlb: trust_ui_vm_swiotlb { + size = <0x400000>; + gunyah-label = <0x12>; + }; + + trust_ui_vm: qcom,trust_ui_vm { + vm_name = "trustedvm"; + shared-buffers-size = <0x414000>; + shared-buffers = <&trust_ui_vm_vblk0_ring + &trust_ui_vm_vblk1_ring + &trust_ui_vm_vsock_ring + &trust_ui_vm_swiotlb>; + }; + + trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x11>; + }; + + trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x10>; + }; + + trust_ui_vm_virt_be2: trust_ui_vm_virt_be2@15 { + qcom,vm = <&trust_ui_vm>; + qcom,label = <0x15>; + }; + + gh-secure-vm-loader@0 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <28>; + qcom,vmid = <45>; + qcom,firmware-name = "trustedvm"; + qcom,keep-running; + memory-region = <&trust_ui_vm_mem &vm_comm_mem>; + virtio-backends = <&trust_ui_vm_virt_be0 + &trust_ui_vm_virt_be1 + &trust_ui_vm_virt_be2>; + }; + + oem_vm_vblk0_ring: oem_vm_vblk0_ring { + size = <0x4000>; + gunyah-label = <0x16>; + }; + + oem_vm_vblk1_ring: oem_vm_vblk1_ring { + size = <0x4000>; + gunyah-label = <0x13>; + }; + + oem_vm_swiotlb: oem_vm_swiotlb { + size = <0x100000>; + gunyah-label = <0x14>; + }; + + oem_vm: qcom,oem_vm { + vm_name = "oemvm"; + shared-buffers-size = <0x108000>; + shared-buffers = <&oem_vm_vblk0_ring &oem_vm_vblk1_ring &oem_vm_swiotlb>; + }; + + oem_vm_virt_be0: oem_vm_virt_be0@16 { + qcom,vm = <&oem_vm>; + qcom,label = <0x16>; + }; + + oem_vm_virt_be1: oem_vm_virt_be1@13 { + qcom,vm = <&oem_vm>; + qcom,label = <0x13>; + }; + + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <34>; + qcom,vmid = <49>; + qcom,firmware-name = "oemvm"; + qcom,keep-running; + memory-region = <&oem_vm_mem &vm_comm_mem>; + virtio-backends = <&oem_vm_virt_be0 &oem_vm_virt_be1>; + }; + gh-secure-vm-loader@2 { compatible = "qcom,gh-secure-vm-loader"; qcom,pas-id = <35>; qcom,vmid = <50>; qcom,firmware-name = "cpusys_vm"; memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; + }; + + mmio_sram: mmio-sram@17D09400 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "mmio-sram"; + reg = <0x0 0x17D09400 0x0 0x400>; + ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>; + + cpu_scp_lpri: scmi-shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x17D09400 0x0 0x400>; + }; + }; + + cpucp: qcom,cpucp@17400000 { + compatible = "qcom,cpucp"; + reg = <0x17d90000 0x2000>, + <0x17400000 0x10>; + reg-names = "rx", "tx"; + #mbox-cells = <1>; + interrupts = ; + }; + + scmi: qcom,scmi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,scmi"; + mboxes = <&cpucp 0>; + mbox-names = "tx"; + shmem = <&cpu_scp_lpri>; + + scmi_qcom: protocol@80 { + reg = <0x80>; + #clock-cells = <1>; + }; + }; + + cpucp_log: qcom,cpucp_log@d8140000 { + compatible = "qcom,cpucp-log"; + reg = <0x81200000 0x10000>, <0x81210000 0x10000>; + mboxes = <&cpucp 1>; + }; + + qcom_c1dcvs: qcom,c1dcvs { + compatible = "qcom,c1dcvs-v2"; + }; + + qcom_dynpf: qcom,dynpf { + compatible = "qcom,dynpf"; + }; + + qcom_cpufreq_stats: qcom,cpufreq_stats { + compatible = "qcom,cpufreq-stats-v2"; + }; + + spmi_bus: spmi0_bus: qcom,spmi@c42d000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc42d000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4c0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <0>; + }; + + spmi1_bus: qcom,spmi@c432000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc432000 0x4000>, + <0xc400000 0x3000>, + <0xc500000 0x400000>, + <0xc440000 0x80000>, + <0xc4d0000 0x10000>; + reg-names = "cnfg", "core", "chnls", "obsrvr", "intr"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + qcom,bus-id = <1>; + depends-on-supply = <&spmi0_bus>; + status = "disabled"; + }; + + spmi0_debug_bus: qcom,spmi-debug@10b14000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x10b14000 0x60>, <0x221c8784 0x4>; + reg-names = "core", "fuse"; + clocks = <&aoss_qmp>; + clock-names = "core_clk"; + qcom,fuse-enable-bit = <18>; + #address-cells = <2>; + #size-cells = <0>; + depends-on-supply = <&spmi_bus>; + + pmk8550@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmxr2230@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmd802x@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8550vs@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmg1110@9 { + compatible = "qcom,spmi-pmic"; + reg = <9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pmr735d@a { + compatible = "qcom,spmi-pmic"; + reg = <10 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@c { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + pm8010@d { + compatible = "qcom,spmi-pmic"; + reg = <13 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + thermal_zones: thermal-zones { + }; + + qcom,pmic_glink { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS"; + qcom,subsys-name = "lpass"; + qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd"; + depends-on-supply = <&ipcc_mproc>; + + battery_charger: qcom,battery_charger { + compatible = "qcom,battery-charger"; + }; + + ucsi: qcom,ucsi { + compatible = "qcom,ucsi-glink"; + }; + + altmode: qcom,altmode { + compatible = "qcom,altmode-glink"; + #altmode-cells = <1>; + }; + }; + + qcom,pmic_glink_log { + compatible = "qcom,qti-pmic-glink"; + qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS"; + + qcom,battery_debug { + compatible = "qcom,battery-debug"; + }; + + qcom,charger_ulog_glink { + compatible = "qcom,charger-ulog-glink"; + }; + + pmic_glink_debug: qcom,pmic_glink_debug { + compatible = "qcom,pmic-glink-debug"; + #address-cells = <1>; + #size-cells = <0>; + depends-on-supply = <&spmi1_bus>; + + }; + + pmic_glink_adc: qcom,glink-adc { + compatible = "qcom,glink-adc"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", "qref_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + /* set the dependency that smmu being probed before ufs */ + depends-on-supply = <&apps_smmu>; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + qcom,bypass-pbl-rst-wa; + qcom,max-cpus = <8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; }; }; @@ -1035,82 +2055,79 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_ofe_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_0_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_1_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_tfe_2_gdsc { - compatible = "regulator-fixed"; status = "ok"; }; &cam_cc_titan_top_gdsc { - compatible = "regulator-fixed"; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; + interconnect-names = "mmnoc"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_0_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_0_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_pcie_1_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_pcie_1_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_mem_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; &gcc_ufs_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb30_prim_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; &gcc_usb3_phy_gdsc { - compatible = "regulator-fixed"; + parent-supply = <&VDD_MX_LEVEL>; status = "ok"; }; @@ -1130,12 +2147,15 @@ }; &video_cc_mvs0_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; status = "ok"; }; &video_cc_mvs0c_gdsc { - compatible = "regulator-fixed"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; status = "ok"; }; @@ -1150,6 +2170,28 @@ reg = <0x0 0x81c60000 0x0 0x20000>; }; + trust_ui_vm_mem: trust_ui_vm_region@f3800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf3800000 0x0 0x4400000>; + reusable; + alignment = <0x0 0x400000>; + }; + + oem_vm_mem: oem_vm_region@f7c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + reusable; + alignment = <0x0 0x400000>; + }; + + vm_comm_mem: vm_comm_mem_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + adsp_mem_heap: adsp_heap_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index bfcaacb2..66587965 100644 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -84,6 +84,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_1: l1-icache { compatible = "cache"; @@ -109,6 +110,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_2: l1-icache { compatible = "cache"; @@ -134,6 +136,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; L1_I_3: l1-icache { compatible = "cache"; @@ -1641,24 +1644,11 @@ }; rpm-sleep-stats@4690000 { - /* compatible = "qcom,rpm-sleep-stats"; */ + compatible = "qcom,rpm-stats-v2"; reg = <0x04690000 0x400>; ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss"; }; - subsystem-sleep-stats@4690000 { - /* compatible = "qcom,subsystem-sleep-stats-v2"; */ - reg = <0x4690000 0x400>; - }; - - qcom,rpm-master-stats@45f0150 { - /* compatible = "qcom,rpm-master-stats"; */ - reg = <0x45f0150 0x5000>; - qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; - qcom,master-stats-version = <2>; - qcom,master-offset = <4096>; - }; - sdhc1_opp_table: sdhc1-opp-table { compatible = "operating-points-v2"; diff --git a/qcom/msm-arm-smmu-kera-vm.dtsi b/qcom/msm-arm-smmu-kera-vm.dtsi new file mode 100644 index 00000000..f9dabb87 --- /dev/null +++ b/qcom/msm-arm-smmu-kera-vm.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x7>; + num-smrs = <0xe>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c08 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0804 0x0002 0x00000001>, + + /* NSP:Compute */ + <0x0c0b 0x0000 0x00000303>, + + /* SF:Camera IPE*/ + <0x1808 0x0020 0x00000001>, + + /* SF:Camera CDM IPE/IFE/OFE*/ + <0x1841 0x0000 0x00000001>, + <0x1861 0x0000 0x00000001>, + <0x1881 0x0000 0x00000001>, + + /* SF:Camera ICP*/ + <0x18c2 0x0000 0x00000001>, + <0x1982 0x0000 0x00000001>, + + /* SF:Camera CRE*/ + <0x18e8 0x0000 0x00000103>, + + /* SF:EVA */ + <0x1901 0x0020 0x00000103>, + <0x1925 0x0000 0x00000103>; + }; +}; diff --git a/qcom/msm-arm-smmu-kera.dtsi b/qcom/msm-arm-smmu-kera.dtsi index 106a073f..c3fe3578 100644 --- a/qcom/msm-arm-smmu-kera.dtsi +++ b/qcom/msm-arm-smmu-kera.dtsi @@ -17,6 +17,13 @@ ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = + "gpu_cc_hlos1_vote_gpu_smmu"; + interrupts = , , , @@ -53,6 +60,7 @@ reg = <0x3de8000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <49>; + interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; }; @@ -230,6 +238,7 @@ reg = <0x16f2000 0x1000>; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -238,6 +247,7 @@ reg = <0x171b000 0x1000>; qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <36>; + interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -246,6 +256,7 @@ reg = <0x17f7000 0x1000>; qcom,stream-id-range = <0x1c00 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -254,6 +265,7 @@ reg = <0x7d3000 0x1000>; qcom,stream-id-range = <0xc00 0x400>; qcom,iova-width = <32>; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -262,6 +274,7 @@ reg = <0x7b3000 0x1000>; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <32>; + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <1>; }; @@ -271,6 +284,7 @@ qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <32>; qcom,num-qtb-ports = <1>; + interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; qcom,opt-out-tbu-halting; }; @@ -279,6 +293,7 @@ reg = <0x17b7000 0x1000>; qcom,stream-id-range = <0x1800 0x400>; qcom,iova-width = <32>; + interconnects = <&mmss_noc MASTER_VIDEO_MVP &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; @@ -287,6 +302,7 @@ reg = <0x17f6000 0x1000>; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; + interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>; qcom,num-qtb-ports = <2>; }; diff --git a/qcom/msm-arm-smmu-tuna-vm.dtsi b/qcom/msm-arm-smmu-tuna-vm.dtsi new file mode 100644 index 00000000..f9dabb87 --- /dev/null +++ b/qcom/msm-arm-smmu-tuna-vm.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +/ { + vm-config { + vdevices { + vsmmu@15000000 { + vdevice-type = "vsmmu-v2"; + smmu-handle = <0x15000000>; + num-cbs = <0x7>; + num-smrs = <0xe>; + patch = "/soc/apps-smmu@15000000"; + }; + }; + }; +}; + +&soc { + apps_smmu: apps-smmu@15000000 { + /* + * reg, #global-interrupts & interrupts properties will + * be added dynamically by bootloader. + */ + compatible = "qcom,qsmmu-v500", "qcom,virt-smmu"; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + dma-coherent; + + qcom,actlr = + /* CAM_HF:Camera */ + <0x1c08 0x0000 0x00000001>, + + /* Mnoc_HF_23:Display */ + <0x0804 0x0002 0x00000001>, + + /* NSP:Compute */ + <0x0c0b 0x0000 0x00000303>, + + /* SF:Camera IPE*/ + <0x1808 0x0020 0x00000001>, + + /* SF:Camera CDM IPE/IFE/OFE*/ + <0x1841 0x0000 0x00000001>, + <0x1861 0x0000 0x00000001>, + <0x1881 0x0000 0x00000001>, + + /* SF:Camera ICP*/ + <0x18c2 0x0000 0x00000001>, + <0x1982 0x0000 0x00000001>, + + /* SF:Camera CRE*/ + <0x18e8 0x0000 0x00000103>, + + /* SF:EVA */ + <0x1901 0x0020 0x00000103>, + <0x1925 0x0000 0x00000103>; + }; +}; diff --git a/qcom/parrot-4gb.dtsi b/qcom/parrot-4gb.dtsi index cea98f38..a82237e1 100644 --- a/qcom/parrot-4gb.dtsi +++ b/qcom/parrot-4gb.dtsi @@ -36,17 +36,11 @@ }; &soc { - - qcom,guestvm_loader@e0b00000 { + gh-secure-vm-loader@0 { status = "disabled"; }; qrtr-gunyah { status = "disabled"; }; - - qcom,virtio_backend@0 { - status = "disabled"; - }; - }; diff --git a/qcom/parrot-pinctrl.dtsi b/qcom/parrot-pinctrl.dtsi index 28d57699..7d9220df 100644 --- a/qcom/parrot-pinctrl.dtsi +++ b/qcom/parrot-pinctrl.dtsi @@ -1887,4 +1887,14 @@ }; }; + tlmm-vm-mem-access { + compatible = "qcom,tlmm-vm-mem-access"; + qcom,master; + tuivm { + qcom,label = <0x08>; + qcom,vmid = <45>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; + }; + }; }; diff --git a/qcom/parrot-qrd.dtsi b/qcom/parrot-qrd.dtsi index c537398e..aa7b33d2 100644 --- a/qcom/parrot-qrd.dtsi +++ b/qcom/parrot-qrd.dtsi @@ -159,6 +159,13 @@ goodix,touch-type = "primary"; goodix,qts_en; - qcom,touch-environment = "pvm"; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "pvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <595>; + qts,trusted-touch-io-bases = <0xa8c000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 + &tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>; }; }; diff --git a/qcom/parrot-vm-qrd.dtsi b/qcom/parrot-vm-qrd.dtsi index 1510613d..a6f2eb6a 100644 --- a/qcom/parrot-vm-qrd.dtsi +++ b/qcom/parrot-vm-qrd.dtsi @@ -5,3 +5,25 @@ &soc { }; + +&qupv3_se9_spi { + status = "ok"; + goodix-berlin@0 { + compatible = "goodix,gt9916S"; + reg = <0>; + spi-max-frequency = <1000000>; + goodix,panel-max-x = <1080>; + goodix,panel-max-y = <2400>; + goodix,panel-max-w = <255>; + goodix,panel-max-p = <4096>; + goodix,touch-type = "primary"; + goodix,qts_en; + qts,trusted-touch-mode = "vm_mode"; + qts,touch-environment = "tvm"; + qts,trusted-touch-type = "primary"; + qts,trusted-touch-spi-irq = <595>; + qts,trusted-touch-io-bases = <0xa8c000>; + qts,trusted-touch-io-sizes = <0x1000>; + qts,trusted-touch-vm-gpio-list = <&tlmm 10 0 &tlmm 11 0 &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0x2008>; + }; +}; diff --git a/qcom/parrot-vm.dtsi b/qcom/parrot-vm.dtsi index 82ea3d9d..953d401c 100644 --- a/qcom/parrot-vm.dtsi +++ b/qcom/parrot-vm.dtsi @@ -8,7 +8,7 @@ / { qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>, - <633 0x10000>, <634 0x10000>, <638 0x10000>; + <633 0x10000>, <634 0x10000>, <638 0x10000>, <663 0x10000>; interrupt-parent = <&vgic>; qcom,vm-config { @@ -53,14 +53,14 @@ <0x17260000 0x100000>; /* GICR * 8 */ }; - pinctrl@f000000 { + tlmm: pinctrl@f000000 { compatible = "qcom,parrot-vm-tlmm"; - gpios = /bits/ 16 <>; - qcom,gpios-reserved = <0 1 2 3 38>; + gpios = /bits/ 16 <98 99 10 11 12 13 64 65>; }; tlmm-vm-mem-access { - tlmm-vm-gpio-list = <>; + tlmm-vm-gpio-list = <&tlmm 98 0 &tlmm 99 0 &tlmm 10 0 &tlmm 11 0 + &tlmm 12 0 &tlmm 13 0 &tlmm 64 0 &tlmm 65 0>; }; apps-smmu@15000000 { diff --git a/qcom/parrot.dtsi b/qcom/parrot.dtsi index d36b3a45..8e6b856d 100644 --- a/qcom/parrot.dtsi +++ b/qcom/parrot.dtsi @@ -463,6 +463,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + dsi_pll_codes { + }; + + disp_rdump_region@e1000000 { + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -2066,6 +2072,16 @@ virtio-backends = <&trust_ui_vm_virt_be0>; }; + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; + }; + qrtr-gunyah { compatible = "qcom,qrtr-gunyah"; qcom,master; diff --git a/qcom/pineapple-debug.dtsi b/qcom/pineapple-debug.dtsi index 7b272c0d..144efbab 100644 --- a/qcom/pineapple-debug.dtsi +++ b/qcom/pineapple-debug.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -10,11 +10,8 @@ #size-cells = <2>; ranges; - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; + dump_mem: dump_mem_region { alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; size = <0 0x1800000>; }; }; @@ -4505,414 +4502,418 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; - c0_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x0>; - }; - - c100_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x1>; - }; - - c200_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x2>; - }; - - c300_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x3>; - }; - - c400_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x4>; - }; - - c500_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x5>; - }; - - c600_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x6>; - }; - - c700_context { - qcom,dump-size = <0x800>; - qcom,dump-id = <0x7>; - }; - - l1_icache0 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x60>; - }; - - l1_icache100 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x61>; - }; - - l1_icache200 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x62>; - }; - - l1_icache300 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x63>; - }; - - l1_icache400 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x64>; - }; - - l1_icache500 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x65>; - }; - - l1_icache600 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x66>; - }; - - l1_icache700 { - qcom,dump-size = <0x22100>; - qcom,dump-id = <0x67>; - }; - - l1_dcache0 { - qcom,dump-size = <0x12100>; - qcom,dump-id = <0x80>; - }; - - l1_dcache100 { - qcom,dump-size = <0x12100>; - qcom,dump-id = <0x81>; - }; - - l1_dcache200 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x82>; - }; - - l1_dcache300 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x83>; - }; - - l1_dcache400 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x84>; - }; - - l1_dcache500 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x85>; - }; - - l1_dcache600 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x86>; - }; - - l1_dcache700 { - qcom,dump-size = <0x1a100>; - qcom,dump-id = <0x87>; - }; - - l1_itlb700 { - qcom,dump-size = <0x600>; - qcom,dump-id = <0x27>; - }; - - l1_dtlb700 { - qcom,dump-size = <0xa00>; - qcom,dump-id = <0x47>; - }; - - l2_cache0 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc0>; - }; - - l2_cache100 { - qcom,dump-size = <0x90100>; - qcom,dump-id = <0xc1>; - }; - - l2_cache200 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc2>; - }; - - l2_cache300 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc3>; - }; - - l2_cache400 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc4>; - }; - - l2_cache500 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc5>; - }; - - l2_cache600 { - qcom,dump-size = <0xd0100>; - qcom,dump-id = <0xc6>; - }; - - l2_cache700 { - qcom,dump-size = <0x340100>; - qcom,dump-id = <0xc7>; - }; - - l2_tlb0 { - qcom,dump-size = <0xf700>; - qcom,dump-id = <0x120>; - }; - - l2_tlb100 { - qcom,dump-size = <0xf700>; - qcom,dump-id = <0x121>; - }; - - l2_tlb700 { - qcom,dump-size = <0xa900>; - qcom,dump-id = <0x127>; - }; - - l1dcdirty0 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x170>; - }; - - l1dcdirty100 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x171>; - }; - - l1dcmte0 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x180>; - }; - - l1dcmte100 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x181>; - }; - - l2dcmte0 { - qcom,dump-size = <0x10100>; - qcom,dump-id = <0x190>; - }; - - l2dcmte100 { - qcom,dump-size = <0x10100>; - qcom,dump-id = <0x191>; - }; - - l0mopca700 { - qcom,dump-size = <0x4100>; - qcom,dump-id = <0x1a7>; - }; - - l2victim700 { - qcom,dump-size = <0x2100>; - qcom,dump-id = <0x1e7>; - }; - - l2tldtcsp200 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x202>; - }; - - l2tldtcsp300 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x203>; - }; - - l2tldtcsp400 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x204>; - }; - - l2tldtcsp500 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x205>; - }; - - l2tldtcsp600 { - qcom,dump-size = <0x7900>; - qcom,dump-id = <0x206>; - }; - - l2tldtcmp200 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x212>; - }; - - l2tldtcmp300 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x213>; - }; - - l2tldtcmp400 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x214>; - }; - - l2tldtcmp500 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x215>; - }; - - l2tldtcmp600 { - qcom,dump-size = <0x1300>; - qcom,dump-id = <0x216>; - }; - - cpuss_reg { - qcom,dump-size = <0x36000>; - qcom,dump-id = <0xef>; - }; - - rpmh { - qcom,dump-size = <0x400000>; - qcom,dump-id = <0xec>; - }; - - rpm_sw { - qcom,dump-size = <0x28000>; - qcom,dump-id = <0xea>; - }; - - pmic { - qcom,dump-size = <0x200000>; - qcom,dump-id = <0xe4>; - }; - - fcm { - qcom,dump-size = <0x8400>; - qcom,dump-id = <0xee>; - }; - - etf_swao { - qcom,dump-size = <0x10000>; - qcom,dump-id = <0xf1>; - }; - - etr_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x100>; - }; - - etfswao_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x102>; - }; - - etr1_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x105>; - }; - - misc_data { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0xe8>; - }; - - etf_slpi { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf3>; - }; - - etfslpi_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x103>; - }; - - etf_lpass { - qcom,dump-size = <0x4000>; - qcom,dump-id = <0xf4>; - }; - - etflpass_reg { - qcom,dump-size = <0x1000>; - qcom,dump-id = <0x104>; - }; - - osm_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x163>; - }; - - pcu_reg { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x164>; - }; - - fsm_data { - qcom,dump-size = <0x400>; - qcom,dump-id = <0x165>; - }; - - spr_cpu0 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f0>; - }; - - spr_cpu1 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f1>; - }; - - spr_cpu2 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f2>; - }; - - spr_cpu3 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f3>; - }; - - spr_cpu4 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f4>; - }; - - spr_cpu5 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f5>; - }; - - spr_cpu6 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f6>; - }; - - spr_cpu7 { - qcom,dump-size = <0x2000>; - qcom,dump-id = <0x1f7>; - }; - - scandump_smmu { - qcom,dump-size = <0x40000>; - qcom,dump-id = <0x220>; - }; - - scandump_gpu { - qcom,dump-size = <0x300000>; - qcom,dump-id = <0x221>; + static_dump { + qcom,static-mem-dump; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + l1_icache0 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x22100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x1a100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb700 { + qcom,dump-size = <0x600>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb700 { + qcom,dump-size = <0xa00>; + qcom,dump-id = <0x47>; + }; + + l2_cache0 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc0>; + }; + + l2_cache100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc1>; + }; + + l2_cache200 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc2>; + }; + + l2_cache300 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc3>; + }; + + l2_cache400 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache500 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache600 { + qcom,dump-size = <0xd0100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache700 { + qcom,dump-size = <0x340100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0xf700>; + qcom,dump-id = <0x121>; + }; + + l2_tlb700 { + qcom,dump-size = <0xa900>; + qcom,dump-id = <0x127>; + }; + + l1dcdirty0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x170>; + }; + + l1dcdirty100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x171>; + }; + + l1dcmte0 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x180>; + }; + + l1dcmte100 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x181>; + }; + + l2dcmte0 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x190>; + }; + + l2dcmte100 { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x191>; + }; + + l0mopca700 { + qcom,dump-size = <0x4100>; + qcom,dump-id = <0x1a7>; + }; + + l2victim700 { + qcom,dump-size = <0x2100>; + qcom,dump-id = <0x1e7>; + }; + + l2tldtcsp200 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x202>; + }; + + l2tldtcsp300 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x203>; + }; + + l2tldtcsp400 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x204>; + }; + + l2tldtcsp500 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x205>; + }; + + l2tldtcsp600 { + qcom,dump-size = <0x7900>; + qcom,dump-id = <0x206>; + }; + + l2tldtcmp200 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x212>; + }; + + l2tldtcmp300 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x213>; + }; + + l2tldtcmp400 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x214>; + }; + + l2tldtcmp500 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x215>; + }; + + l2tldtcmp600 { + qcom,dump-size = <0x1300>; + qcom,dump-id = <0x216>; + }; + + cpuss_reg { + qcom,dump-size = <0x36000>; + qcom,dump-id = <0xef>; + }; + + rpmh { + qcom,dump-size = <0x400000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + etr1_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x105>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_slpi { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf3>; + }; + + etfslpi_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x103>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + + spr_cpu0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f0>; + }; + + spr_cpu1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f1>; + }; + + spr_cpu2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f2>; + }; + + spr_cpu3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f3>; + }; + + spr_cpu4 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f4>; + }; + + spr_cpu5 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f5>; + }; + + spr_cpu6 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f6>; + }; + + spr_cpu7 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x1f7>; + }; + + scandump_smmu { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x220>; + }; + + scandump_gpu { + qcom,dump-size = <0x300000>; + qcom,dump-id = <0x221>; + }; }; }; }; diff --git a/qcom/platform_map.bzl b/qcom/platform_map.bzl index 74b784bc..95d31391 100644 --- a/qcom/platform_map.bzl +++ b/qcom/platform_map.bzl @@ -85,7 +85,9 @@ _platform_map = { }, {"name": "tuna-atp-overlay.dtbo"}, {"name": "tuna-cdp-overlay.dtbo"}, + {"name": "tuna-mtp-kiwi-harmonium-overlay.dtbo"}, {"name": "tuna-mtp-kiwi-overlay.dtbo"}, + {"name": "tuna-mtp-nfc-overlay.dtbo"}, {"name": "tuna-mtp-overlay.dtbo"}, {"name": "tuna-mtp-qmp1000-overlay.dtbo"}, {"name": "tuna-qrd-overlay.dtbo"}, @@ -142,7 +144,7 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], - "binary_compatible_with": ["tuna-tuivm"], + "binary_compatible_with": ["tuna-tuivm", "kera-tuivm"], }, "sun-oemvm": { "dtb_list": [ @@ -162,7 +164,7 @@ _platform_map = { {"name": "sunp-vm-hdk.dtb"}, {"name": "sun-vm-rumi.dtb"}, ], - "binary_compatible_with": ["tuna-oemvm"], + "binary_compatible_with": ["tuna-oemvm", "kera-oemvm"], }, "tuna-tuivm": { "dtb_list": [ @@ -210,6 +212,20 @@ _platform_map = { {"name": "tuna-vm-rumi.dtb"}, ], }, + "kera-tuivm": { + "dtb_list": [ + # keep sorted + {"name": "kera-oemvm-rumi.dtb"}, + {"name": "kera-vm-rumi.dtb"}, + ], + }, + "kera-oemvm": { + "dtb_list": [ + # keep sorted + {"name": "kera-oemvm-rumi.dtb"}, + {"name": "kera-vm-rumi.dtb"}, + ], + }, "pineapple": { "dtb_list": [ {"name": "pineapple.dtb"}, diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi index 953da75d..534a7689 100644 --- a/qcom/pm7550ba.dtsi +++ b/qcom/pm7550ba.dtsi @@ -156,7 +156,7 @@ pm7550ba_trip1: trip1 { temperature = <115000>; hysteresis = <0>; - type = "critical"; + type = "hot"; }; pm7550ba_trip2: trip2 { @@ -196,7 +196,7 @@ }; pm7550ba-bcl-lvl0 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 5>; @@ -222,7 +222,7 @@ }; pm7550ba-bcl-lvl1 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 6>; @@ -248,7 +248,7 @@ }; pm7550ba-bcl-lvl2 { - polling-delay-passive = <100>; + polling-delay-passive = <50>; polling-delay = <0>; thermal-sensors = <&pm7550ba_bcl 7>; diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index ab5b1805..1d470d30 100644 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -199,7 +199,7 @@ reg = <0xb300>; reg-names = "lpg-base"; #pwm-cells = <2>; - qcom,num-lpg-channels = <5>; + qcom,num-lpg-channels = <3>; nvmem-names = "ppg_sdam"; nvmem = <&pmi632_sdam7>; qcom,pbs-client = <&pmi632_pbs_client3>; @@ -235,6 +235,7 @@ }; pmi632_rgb: qcom,leds@d000 { + compatible = "qcom,tri-led"; reg = <0xd000>; red { label = "red"; diff --git a/qcom/pmih010x.dtsi b/qcom/pmih010x.dtsi index 42ae38ea..0bcc96fb 100644 --- a/qcom/pmih010x.dtsi +++ b/qcom/pmih010x.dtsi @@ -62,7 +62,6 @@ hap_swr_slave_reg: qcom,hap-swr-slave-reg { regulator-name = "hap-swr-slave-reg"; - regulator-always-on; }; /* diff --git a/qcom/pmk8550.dtsi b/qcom/pmk8550.dtsi index 21ddcae1..6c15ff6f 100644 --- a/qcom/pmk8550.dtsi +++ b/qcom/pmk8550.dtsi @@ -30,6 +30,11 @@ #address-cells = <1>; #size-cells = <1>; + sm1510_present: sm1510_present@5d { + reg = <0x5d 0x1>; + bits = <5 5>; + }; + ocp_log: ocp-log@76 { reg = <0x76 0x6>; }; @@ -58,6 +63,10 @@ reg = <0x9a 0x1>; }; + fmd_cont_after_pon: fmd-cont-after-pon@9c { + reg = <0x9c 0x1>; + }; + fmd_chg_pon: fmd-chg-pon@9f { reg = <0x9f 0x1>; }; diff --git a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi index fec6cbb4..005563db 100644 --- a/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi +++ b/qcom/ravelin-idp-wcn3950-amoled-rcm.dtsi @@ -17,8 +17,10 @@ #size-cells = <0>; status = "ok"; qcom,touch-active = "goodix,gt9916S"; + qcom,la-vm; goodix-berlin@0 { + compatible = "goodix,gt9916S"; reg = <0>; spi-max-frequency = <1000000>; @@ -41,7 +43,8 @@ pinctrl-0 = <&ts_spi_active>; pinctrl-1 = <&ts_spi_int_suspend &ts_spi_reset_suspend>; pinctrl-2 = <&ts_spi_release>; - + goodix,touch-type = "primary"; + goodix,qts_en; qcom,touch-environment = "pvm"; }; }; diff --git a/qcom/ravelin-low-memory.dtsi b/qcom/ravelin-low-memory.dtsi index 201d98f4..c3f8e9f7 100644 --- a/qcom/ravelin-low-memory.dtsi +++ b/qcom/ravelin-low-memory.dtsi @@ -28,15 +28,11 @@ }; &soc { - qcom,guestvm_loader@e0b00000 { + gh-secure-vm-loader@0 { status = "disabled"; }; qrtr-gunyah { status = "disabled"; }; - - qcom,virtio_backend@0 { - status = "disabled"; - }; }; diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index 32b8915b..74364536 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -459,6 +459,12 @@ ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + dsi_pll_codes { + }; + + disp_rdump_region@e1000000 { + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -2473,6 +2479,16 @@ virtio-backends = <&trust_ui_vm_virt_be0>; }; + gh-secure-vm-loader@1 { + compatible = "qcom,gh-secure-vm-loader"; + qcom,pas-id = <35>; + qcom,vmid = <50>; + qcom,firmware-name = "cpusys_vm"; + memory-region = <&cpusys_vm_mem>; + ext-region = <&chipinfo_mem>; + ext-label = <0x7>; + }; + vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index cafbcccd..4f0c8227 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -1325,7 +1325,7 @@ qcom,msm-imem@14680000 { compatible = "qcom,msm-imem"; reg = <0x0 0x14680000 0x0 0x1000>; - ranges = <0x0 0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x14680000 0x0 0x1000>; #address-cells = <2>; #size-cells = <2>; @@ -1368,6 +1368,11 @@ compatible = "qcom,msm-imem-diag-dload"; reg = <0x0 0xc8 0x0 0xc8>; }; + + modem_dsm@c98 { + compatible = "qcom,msm-imem-mss-dsm"; + reg = <0x0 0xc98 0x0 0x10>; + }; }; tcsr_mutex_block: syscon@1f40000 { @@ -2125,3 +2130,19 @@ #include "sdxkova-usb.dtsi" #include "ipcc-test-sdxkova.dtsi" + +&CPU0 { + /delete-property/ clocks; +}; + +&CPU1 { + /delete-property/ clocks; +}; + +&CPU2 { + /delete-property/ clocks; +}; + +&CPU3 { + /delete-property/ clocks; +}; diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index deec010a..44909887 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -35,7 +35,7 @@ chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops slub_debug=-"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; @@ -3651,6 +3651,9 @@ <&cnoc_main MASTER_CNOC_CFG &mc_virt SLAVE_EBI1>; interconnect-names = "rproc_ddr", "rproc_cnoc"; + rproc-ddr-set-icc-low-svs; + rproc-ddr-lowsvs-icc-bw = <1200>; + memory-region = <&soccp_mem 0>; soccp-tcsr = <&tcsr 0x1a000>; soccp-spare = <0xda0024>; diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi index 6b85652a..86c0f38a 100644 --- a/qcom/tuna-cdp.dtsi +++ b/qcom/tuna-cdp.dtsi @@ -4,7 +4,6 @@ */ #include -#include &qupv3_se4_i2c { #address-cells = <1>; @@ -102,9 +101,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna-dma-heaps.dtsi b/qcom/tuna-dma-heaps.dtsi index 9e9b9381..f41a1746 100644 --- a/qcom/tuna-dma-heaps.dtsi +++ b/qcom/tuna-dma-heaps.dtsi @@ -10,6 +10,13 @@ compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = ; + qcom,max-align = <9>; + memory-region = <&non_secure_display_memory>; + }; + qcom,secure_cdsp { qcom,dma-heap-name = "qcom,cma-secure-cdsp"; qcom,dma-heap-type = ; diff --git a/qcom/tuna-mtp-kiwi-harmonium-overlay.dts b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts new file mode 100644 index 00000000..dfaff3ba --- /dev/null +++ b/qcom/tuna-mtp-kiwi-harmonium-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-kiwi-harmonium.dtsi" +#include "tuna-pm7550ba.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 3>; +}; diff --git a/qcom/tuna-mtp-kiwi-harmonium.dtsi b/qcom/tuna-mtp-kiwi-harmonium.dtsi new file mode 100644 index 00000000..37e840c1 --- /dev/null +++ b/qcom/tuna-mtp-kiwi-harmonium.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp-kiwi.dtsi" diff --git a/qcom/tuna-mtp-nfc-overlay.dts b/qcom/tuna-mtp-nfc-overlay.dts new file mode 100644 index 00000000..440dcc09 --- /dev/null +++ b/qcom/tuna-mtp-nfc-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-mtp-nfc.dtsi" +#include "tuna-pm7550ba-pmd802x.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + SN220/SN300 NFC"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 4>; +}; diff --git a/qcom/tuna-mtp-nfc.dtsi b/qcom/tuna-mtp-nfc.dtsi new file mode 100644 index 00000000..386415d7 --- /dev/null +++ b/qcom/tuna-mtp-nfc.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-mtp.dtsi" diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi index 6b85652a..36ab15e3 100644 --- a/qcom/tuna-mtp.dtsi +++ b/qcom/tuna-mtp.dtsi @@ -5,6 +5,7 @@ #include #include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_i2c { #address-cells = <1>; @@ -102,9 +103,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna-oemvm.dtsi b/qcom/tuna-oemvm.dtsi index 3bbe6c32..bdd5e6a1 100644 --- a/qcom/tuna-oemvm.dtsi +++ b/qcom/tuna-oemvm.dtsi @@ -87,7 +87,7 @@ vcpus { config = "/cpus"; affinity = "proxy"; - affinity-map = <0x5 0x6>; + affinity-map = <0x0 0x0>; sched-priority = <0>; /* relative to PVM */ sched-timeslice = <2000>; /* in ms */ }; @@ -157,12 +157,63 @@ }; }; + qrtr-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/qrtr-shm"; + push-compatible = "qcom,qrtr-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x8>; + allocate-base; + }; + }; + vrtc { vdevice-type = "vrtc-pl031"; peer-default; allocate-base; }; + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x000000C>; + }; + + test-dbl-oemvm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-oemvm"; + qcom,label = <0x5>; + peer-default; + }; + + test-dbl-oemvm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-oemvm-source"; + qcom,label = <0x5>; + peer-default; + }; + + test-msgq-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x5>; + peer-default; + }; + + test-large-dmabuf-oemvm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-oemvm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xe>; + peer-default; + }; }; }; @@ -206,10 +257,66 @@ clock-frequency = <19200000>; }; + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ + qcom,vmid = <49>; + }; + + qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "oem_vm"; + }; + + virtio_mem_device { + compatible = "qcom,virtio-mem"; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x10000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + }; + + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; }; + qcom,qrtr { + compatible = "qcom,qrtr"; + qcom,node-id = <21>; + }; + + qrtr-gunyah { + compatible = "qcom,qrtr-gunyah"; + gunyah-label = <8>; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; qcom,custom-bridge-size = <512>; diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi index b0972852..d50e57d9 100644 --- a/qcom/tuna-pcie.dtsi +++ b/qcom/tuna-pcie.dtsi @@ -94,6 +94,7 @@ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie_0_pipe_clk>; @@ -104,13 +105,13 @@ "pcie_rate_change_clk", "gcc_ddrss_pcie_sf_qtb_clk", "pcie_aggre_noc_axi_clk", - "gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk", - "pcie_pipe_clk_mux", + "gcc_cnoc_pcie_sf_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk", + "pcie_0_pipe_div2_clk", "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, - <100000000>, <0>, <0>, <0>, <0>, <0>, <0>; + <100000000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>; clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>, - <0>, <0>, <0>, <1>, <0>, <0>, <0>; + <0>, <0>, <0>, <1>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_PHY_BCR>; diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi index e0d2e5c3..344d2862 100644 --- a/qcom/tuna-pm7550ba.dtsi +++ b/qcom/tuna-pm7550ba.dtsi @@ -224,3 +224,38 @@ }; }; }; + +&pm7550ba_bcl { + nvmem-cells = <&sm1510_present>; + nvmem-cell-names = "sm1510_present"; +}; + +&thermal_zones { + pm7550ba-2s-ibat-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 8>; + + trips { + ibat_2s_lvl0: ibat-2s-lvl0 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm7550ba-2s-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7550ba_bcl 9>; + + trips { + ibat_2s_lvl1: ibat-2s-lvl1 { + temperature = <7000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi index 6fe5a0e0..bc82d7e3 100644 --- a/qcom/tuna-pmic-overlay.dtsi +++ b/qcom/tuna-pmic-overlay.dtsi @@ -113,11 +113,18 @@ nvmem-cells = <&restart_reason>; nvmem-cell-names = "restart_reason"; }; + + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pmk8550_sdam_5>, <&pmk8550_sdam_6>; + nvmem-names = "pon_log0", "pon_log1"; + depends-on-supply = <&gh_watchdog>; + }; }; &thermal_zones { sys-therm-0 { - polling-delay-passive = <0>; + polling-delay-passive = <5000>; polling-delay = <0>; thermal-sensors = <&pmk8550_vadc PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU>; trips { @@ -132,6 +139,48 @@ hysteresis = <1000>; type = "passive"; }; + + trip_config0: trip-config0 { + temperature = <78000>; + hysteresis = <8000>; + type = "passive"; + }; + + trip_config1: trip-config1 { + temperature = <80000>; + hysteresis = <10000>; + type = "passive"; + }; + + display_test_config1: display-test-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config2: display-test-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config3: display-test-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config4: display-test-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + display_test_config5: display-test-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi index 86cea255..cfd38eeb 100644 --- a/qcom/tuna-qrd.dtsi +++ b/qcom/tuna-qrd.dtsi @@ -3,7 +3,8 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include -#include +#include +#include "tuna-thermal-overlay.dtsi" &qupv3_se4_spi { #address-cells = <1>; @@ -89,6 +90,14 @@ status = "ok"; }; +&wcd_usbss { + interrupt-parent = <&spmi_bus>; + interrupts = <0x0 0xb6 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_wcd"; + nvmem-cells = <&usb_mode>; + nvmem-cell-names = "usb_mode"; +}; + &sdhc_2 { vdd-supply = <&L13B>; qcom,vdd-voltage-level = <2960000 2960000>; @@ -104,9 +113,6 @@ cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_SDCC2_BCR>; - reset-names = "core_reset"; - qcom,uses_level_shifter; status = "ok"; diff --git a/qcom/tuna-qupv3.dtsi b/qcom/tuna-qupv3.dtsi index 8e7e3077..4ad94442 100644 --- a/qcom/tuna-qupv3.dtsi +++ b/qcom/tuna-qupv3.dtsi @@ -47,7 +47,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup1_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -255,8 +256,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>; pinctrl-1 = <&qupv3_se4_i2c_sleep>; - dmas = <&gpi_dma1 0 4 3 64 0>, - <&gpi_dma1 1 4 3 64 0>; + dmas = <&gpi_dma1 0 4 3 64 2>, + <&gpi_dma1 1 4 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -279,8 +280,8 @@ pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>, <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>; pinctrl-1 = <&qupv3_se4_spi_sleep>; - dmas = <&gpi_dma1 0 4 1 64 0>, - <&gpi_dma1 1 4 1 64 0>; + dmas = <&gpi_dma1 0 4 1 64 2>, + <&gpi_dma1 1 4 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; @@ -419,7 +420,8 @@ , , ; - qcom,gpii-mask = <0x1f>; + qcom,static-gpii-mask = <0x1>; + qcom,gpii-mask = <0x1e>; qcom,ev-factor = <1>; memory-region = <&qup2_gpi_iommu_region>; qcom,gpi-ee-offset = <0x10000>; @@ -749,8 +751,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; pinctrl-1 = <&qupv3_se15_i2c_sleep>; - dmas = <&gpi_dma2 0 7 3 64 0>, - <&gpi_dma2 1 7 3 64 0>; + dmas = <&gpi_dma2 0 7 3 64 2>, + <&gpi_dma2 1 7 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -773,8 +775,8 @@ pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; pinctrl-1 = <&qupv3_se15_spi_sleep>; - dmas = <&gpi_dma2 0 7 1 64 0>, - <&gpi_dma2 1 7 1 64 0>; + dmas = <&gpi_dma2 0 7 1 64 2>, + <&gpi_dma2 1 7 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi index e0fb9e3d..fd4dd00a 100644 --- a/qcom/tuna-regulators.dtsi +++ b/qcom/tuna-regulators.dtsi @@ -483,6 +483,25 @@ }; }; + rpmh-regulator-bobb1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "bobb1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + BOB: + pmxr2230_bob: regulator-pmxr2230-bob1 { + regulator-name = "pmxr2230_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + }; + }; + rpmh-regulator-msslvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "mss.lvl"; diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi index 5f538408..6c23a664 100644 --- a/qcom/tuna-rumi.dtsi +++ b/qcom/tuna-rumi.dtsi @@ -127,6 +127,18 @@ status = "disabled"; }; +&cam_crm { + status = "disabled"; +}; + +&disp_crm { + status = "disabled"; +}; + +&pcie_crm { + status = "disabled"; +}; + &qupv3_se7_2uart { qcom,rumi_platform; }; @@ -196,3 +208,27 @@ clock-output-names = "rpmh_clocks"; clock-frequency = <19200000>; }; + +&disp_cc_mdss_core_gdsc { + status = "ok"; +}; + +&disp_cc_mdss_core_int2_gdsc { + status = "ok"; +}; + +&video_cc_mvs0_gdsc { + status = "ok"; +}; + +&video_cc_mvs0c_gdsc { + status = "ok"; +}; + +&gpu_cc_cx_gdsc { + status = "ok"; +}; + +&gx_clkctl_gx_gdsc { + status = "ok"; +}; diff --git a/qcom/tuna-thermal-overlay.dtsi b/qcom/tuna-thermal-overlay.dtsi new file mode 100644 index 00000000..4d2ebf83 --- /dev/null +++ b/qcom/tuna-thermal-overlay.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&thermal_zones { + socd { + cooling-maps { + socd_apc1 { + trip = <&socd_trip>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + socd_cdsp1 { + trip = <&socd_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + socd_gpu0 { + trip = <&socd_trip>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pmih010x-bcl-lvl0 { + cooling-maps { + lbat_modem0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&modem_bcl 1 1>; + }; + + lbat_gpu0 { + trip = <&b_bcl_lvl0>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; + + pmih010x-bcl-lvl1 { + cooling-maps { + lbat_modem1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&modem_bcl 2 2>; + }; + + lbat_gpu1 { + trip = <&b_bcl_lvl1>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmih010x-bcl-lvl2 { + cooling-maps { + lbat_gpu2 { + trip = <&b_bcl_lvl2>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl0 { + cooling-maps { + vph_0_nr_scg { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + vph_0_nr { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + vph_0_mdm_lte { + trip = <&bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + vph_gpu0 { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm7550ba-bcl-lvl1 { + cooling-maps { + vph_1_nr_scg { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + vph_1_nr { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + vph_1_mdm_lte { + trip = <&bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + vph_gpu1 { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pm7550ba-bcl-lvl2 { + cooling-maps { + vph_gpu2 { + trip = <&bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; + + pmxr2230-bcl-lvl0 { + cooling-maps { + lbat_0_nr_scg { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_scg_dsc 3 3>; + }; + + lbat_0_nr { + trip = <&bcl_lvl0>; + cooling-device = <&modem_nr_dsc 6 6>; + }; + + lbat_0_mdm_lte { + trip = <&bcl_lvl0>; + cooling-device = <&modem_lte_dsc 8 8>; + }; + + lbat_gpu0 { + trip = <&bcl_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pmxr2230-bcl-lvl1 { + cooling-maps { + lbat_1_nr_scg { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_scg_dsc 10 10>; + }; + + lbat_1_nr { + trip = <&bcl_lvl1>; + cooling-device = <&modem_nr_dsc 9 9>; + }; + + lbat_1_mdm_lte { + trip = <&bcl_lvl1>; + cooling-device = <&modem_lte_dsc 10 10>; + }; + + lbat_gpu1 { + trip = <&bcl_lvl1>; + cooling-device = <&msm_gpu 3 3>; + }; + }; + }; + + pmxr2230-bcl-lvl2 { + cooling-maps { + lbat_gpu2 { + trip = <&bcl_lvl2>; + cooling-device = <&msm_gpu 7 7>; + }; + }; + }; + + sys-therm-0 { + cooling-maps { + apc1_cdev { + trip = <&trip_config0>; + cooling-device = <&APC1_MX_CX_PAUSE 1 1>; + }; + + apc0_cdev { + trip = <&trip_config0>; + cooling-device = <&APC0_MX_CX_PAUSE 1 1>; + }; + + cdsp_cdev { + trip = <&trip_config0>; + cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>; + }; + + gpu_cdev { + trip = <&trip_config0>; + cooling-device = <&msm_gpu 5 THERMAL_NO_LIMIT>; + }; + + cpu3_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; + + cpu4_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; + + cpu5_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; + + cpu6_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; + + cpu7_hot_cdev { + trip = <&trip_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; + + lte_cdev { + trip = <&trip_config1>; + cooling-device = <&modem_lte_dsc 255 255>; + }; + + nr_cdev { + trip = <&trip_config1>; + cooling-device = <&modem_nr_scg_dsc 255 255>; + }; + + display_cdev1 { + trip = <&display_test_config1>; + cooling-device = <&display_fps 1 1>; + }; + + display_cdev2 { + trip = <&display_test_config2>; + cooling-device = <&display_fps 2 2>; + }; + + display_cdev3 { + trip = <&display_test_config3>; + cooling-device = <&display_fps 3 3>; + }; + }; + }; +}; diff --git a/qcom/tuna-thermal.dtsi b/qcom/tuna-thermal.dtsi index 0f0afb75..f555783e 100644 --- a/qcom/tuna-thermal.dtsi +++ b/qcom/tuna-thermal.dtsi @@ -5,6 +5,10 @@ #include +&msm_gpu { + #cooling-cells = <2>; +}; + &soc { tsens0: tsens0@c228000 { compatible = "qcom,tsens-v2"; @@ -207,6 +211,11 @@ }; }; + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + qcom,cpufreq-cdev { compatible = "qcom,cpufreq-cdev"; @@ -236,16 +245,6 @@ #cooling-cells = <2>; }; - cdsp_sw_hvx: cdsp_sw_hvx { - qcom,qmi-dev-name = "cdsp_sw_hvx"; - #cooling-cells = <2>; - }; - - cdsp_sw_hmx: cdsp_sw_hmx { - qcom,qmi-dev-name = "cdsp_sw_hmx"; - #cooling-cells = <2>; - }; - cdsp_hw: cdsp_hw { qcom,qmi-dev-name = "cdsp_hw"; #cooling-cells = <2>; @@ -1241,6 +1240,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-1 { @@ -1273,6 +1279,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-2 { @@ -1305,6 +1318,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu2_cdev { + trip = <&gpu2_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-3 { @@ -1337,6 +1357,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu3_cdev { + trip = <&gpu3_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-4 { @@ -1369,6 +1396,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu4_cdev { + trip = <&gpu4_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; gpu-5 { @@ -1401,6 +1435,13 @@ type = "hot"; }; }; + + cooling-maps { + gpu5_cdev { + trip = <&gpu5_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; + }; }; nsphvx-0 { diff --git a/qcom/tuna-usb.dtsi b/qcom/tuna-usb.dtsi index 88fa476e..295425b4 100644 --- a/qcom/tuna-usb.dtsi +++ b/qcom/tuna-usb.dtsi @@ -9,11 +9,13 @@ &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; - reg = <0xa600000 0x100000>; - reg-names = "core_base"; + reg = <0xa600000 0x100000>, + <0x1fc6000 0x4>; + reg-names = "core_base", + "tcsr_dyn_en_dis"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -28,23 +30,45 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + qcom,use-pdc-interrupts; + qcom,use-eusb2-phy; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-disconnected = <133333333>; - dwc3@a600000 { + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd93c>; + reg = <0x0 0xa600000 0x0 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; + usb-phy = <&eusb2_phy0>, <&usb_nop_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -59,4 +83,258 @@ usb-role-switch; }; }; + + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-snps-eusb2-phy"; + reg = <0x88e3000 0x154>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&L3B>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&L4B>; + vdd_refgen-supply = <&L2B>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L3B>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4B>; + vdd_refgen-supply = <&L2B>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* based on tsmcn3e_USB3_Gen2_Seq v1.6 */ + + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100b 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xb>; + qcom,usb-audio-intr-num = <2>; + }; + }; diff --git a/qcom/tuna-vm-dma-heaps.dtsi b/qcom/tuna-vm-dma-heaps.dtsi index f784d64d..575b2573 100644 --- a/qcom/tuna-vm-dma-heaps.dtsi +++ b/qcom/tuna-vm-dma-heaps.dtsi @@ -9,6 +9,18 @@ compatible = "qcom,dma-heaps"; depends-on-supply = <&qcom_scm>; + qcom,tui { + qcom,dma-heap-name = "qcom,tui"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + + qcom,tui_demura { + qcom,dma-heap-name = "qcom,tui_demura"; + qcom,dma-heap-type = ; + qcom,dynamic-heap; + }; + qcom,ms1 { qcom,dma-heap-name = "qcom,ms1"; qcom,dma-heap-type = ; diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi index b2f4335d..814a1852 100644 --- a/qcom/tuna-vm.dtsi +++ b/qcom/tuna-vm.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { #address-cells = <0x2>; @@ -52,6 +53,29 @@ }; }; + dmesg-dump { + compatible = "qcom,dmesg-dump"; + gunyah-label = <7>; + ddump-pubkey-size = <270>; + ddump-pubkey = /bits/ 8 <0x30 0x82 0x01 0x0a 0x02 0x82 0x01 0x01 0x00 0xe6 0x4b 0x31 0x82 0x61 0x14 0xf2 + 0xbe 0xd1 0xe4 0xde 0xe7 0xed 0xba 0x8f 0x3b 0x23 0x5f 0x7a 0xb8 0x16 0x40 0x96 + 0xae 0x77 0x5e 0x1b 0xf0 0x3f 0x39 0xab 0x69 0x90 0xb1 0xd4 0x70 0xcb 0x66 0xbc + 0x41 0x08 0x1d 0x37 0xdb 0x49 0xc8 0x49 0x5b 0x99 0x5c 0x32 0xbe 0x62 0xd5 0xa7 + 0x3c 0x0f 0xa4 0x4b 0x43 0x49 0xdb 0x54 0x69 0x06 0x0c 0xe5 0x99 0xe5 0xf9 0x1e + 0x25 0x84 0x17 0x47 0x62 0x2b 0x5d 0x0d 0xec 0x5e 0xc6 0xb5 0x86 0xb9 0x75 0x6d + 0xfe 0x7d 0x35 0x4f 0x35 0xc1 0x48 0x10 0x75 0x4c 0x57 0x6b 0x46 0x4b 0xff 0x5b + 0x52 0x22 0x40 0x2c 0xb0 0x47 0xe1 0x47 0xc4 0xe5 0x47 0x0c 0x56 0xe8 0x17 0xd0 + 0x7e 0xc3 0x4d 0x9f 0xea 0xd0 0xea 0x87 0xe5 0x51 0x39 0xe8 0x45 0x4c 0x54 0x27 + 0x9c 0x50 0x38 0xb7 0x72 0x93 0x12 0x0b 0xa1 0x2f 0x9e 0x04 0x92 0x20 0x6e 0x31 + 0x42 0x87 0xe1 0xfe 0x88 0x3f 0xe5 0x09 0xe1 0xf9 0xbe 0x44 0xc6 0xbf 0x10 0x79 + 0x36 0x47 0x7b 0xa0 0x8e 0x27 0x31 0xa3 0x70 0x69 0x01 0x54 0x92 0xf4 0x42 0xbd + 0xcd 0x7e 0x79 0x2b 0x2c 0xe1 0xd4 0xba 0x6e 0x34 0xc6 0xe6 0xc6 0x5c 0x63 0xd0 + 0x7f 0x39 0x1f 0xe8 0x8d 0x67 0xe6 0x27 0x67 0x0d 0x16 0x57 0x94 0xd1 0xfb 0xdf + 0xce 0xaf 0xfd 0x43 0xb3 0xbe 0x5d 0x83 0x4b 0x93 0x05 0xe8 0xdf 0x04 0xad 0xac + 0xeb 0xa6 0x81 0xa7 0xd5 0x04 0x63 0xbf 0x83 0xb8 0x0c 0xbc 0x20 0x18 0xb5 0x50 + 0xd7 0x61 0x84 0x11 0xca 0x2d 0x22 0xb3 0x29 0x02 0x03 0x01 0x00 0x01>; + }; + qcom,vm-config { compatible = "qcom,vm-1.0"; vm-type = "aarch64-guest"; @@ -71,6 +95,10 @@ vm-attrs = "context-dump", "crash-restart"; + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0 + 0x0 0x407000 0x0 0x407000 0x0 0x1000 0x0>; + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. * QUP1_SE4: GPII5 : IRQ_316 * QUP2_SE7: GPII5 : IRQ_625 @@ -96,7 +124,7 @@ vcpus { config = "/cpus"; affinity = "proxy"; - affinity-map = <0x5 0x6>; + affinity-map = <0x0 0x0>; sched-priority = <0>; /* relative to PVM */ sched-timeslice = <2000>; /* in ms */ }; @@ -187,6 +215,37 @@ allocate-base; }; + mem-buf-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/membuf-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000001>; + }; + + ddump-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/ddump-shm"; + push-compatible = "qcom,ddump-gunyah-gen"; + peer-default; + memory { + qcom,label = <0x7>; + allocate-base; + }; + }; + + gunyah-panic-notifier-shm { + vdevice-type = "shm-doorbell"; + generate = "/hypervisor/gpn-shm"; + push-compatible = "qcom,gunyah-panic-gen"; + peer-default; + memory { + qcom,label = <0x9>; + allocate-base; + }; + }; + gpiomem0 { vdevice-type = "iomem"; patch = "/soc/tlmm-vm-mem-access"; @@ -199,6 +258,37 @@ }; }; + test-dbl-tuivm { + vdevice-type = "doorbell"; + generate = "/hypervisor/test-dbl-tuivm"; + qcom,label = <0x4>; + peer-default; + }; + + test-dbl-tuivm-source { + vdevice-type = "doorbell-source"; + generate = "/hypervisor/test-dbl-tuivm-source"; + qcom,label = <0x4>; + peer-default; + }; + + test-msgq-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-msgq-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0x4>; + peer-default; + }; + + test-large-dmabuf-tuivm { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/test-large-dmabuf-tuivm-pair"; + message-size = <0xf0>; + queue-depth = <0x8>; + qcom,label = <0xd>; + peer-default; + }; }; }; @@ -245,15 +335,13 @@ interrupt-controller; #interrupt-cells = <2>; /* Valid pins */ - gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>; + gpios = /bits/ 16 <77 78 14 126 16 17 18 19 189 176 44 45 46 47>; }; tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; tlmm-vm-test { @@ -261,10 +349,8 @@ pinctrl-names = "active", "sleep"; pinctrl-0 = <&qupv3_se1_7i2c_active>; pinctrl-1 = <&qupv3_se1_7i2c_sleep>; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; pinctrl@f000000 { @@ -311,6 +397,15 @@ <0x17180000 0x200000>; /* GICR * 8 */ }; + ipcc_mproc_ns1: qcom,ipcc@407000 { + compatible = "qcom,ipcc"; + reg = <0x407000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; always-on; @@ -330,4 +425,251 @@ qcom,custom-bridge-size = <64>; qcom,support-hypervisor; }; + + qti,smmu-proxy { + compatible = "smmu-proxy-receiver"; + }; + + qti,smmu-proxy-camera-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + iommus = <&apps_smmu 0x1810 0x20>, + <&apps_smmu 0x1C10 0x0>, + <&apps_smmu 0x18F0 0x0>; + dma-coherent; + }; + + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + gunyah-label = <9>; + }; + + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + affinity = <0>; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,secondary; + }; + + qti,smmu-proxy-display-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + iommus = <&apps_smmu 0x801 0x0>; + dma-coherent; + }; + + qti,smmu-proxy-eva-cb { + compatible = "smmu-proxy-cb"; + qti,cb-id = ; + qcom,iommu-defer-smr-config; + qcom,iommu-dma-addr-pool = <0x00000000 0xffffffff>; + iommus = <&apps_smmu 0x1927 0x0>; + dma-coherent; + }; + + qcom,mem-buf { + compatible = "qcom,mem-buf"; + qcom,mem-buf-capabilities = "consumer"; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,dmabuf-ipa-size = <0x1 0x00000000>; /* 4GB IPA space for dmabuf */ + qcom,vmid = <45>; + }; + + mem_buf_msgq: qcom,mem-buf-msgq { + compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm"; + }; + + virtio_mem_device { + compatible = "qcom,virtio-mem"; + depends-on-supply = <&mem_buf_msgq>; + /* Must be memory_block_size_bytes() aligned */ + qcom,max-size = <0x0 0x18000000>; + qcom,ipa-range = <0x0 0x0 0xf 0xffffffff>; + qcom,block-size = <0x400000>; + qcom,initial-movable-zone-size = <0x2000000>; + }; + + /* + * QUP1 : SE4 - Primary touch + * QUP2 : SE7 - Secondary touch + */ + qup_iommu_group: qup_common_iommu_group { + iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>, + <&qupv3_1 0x00000000 0x00020000>, + <&gpi_dma2 0x00000000 0x00020000>, + <&qupv3_2 0x00000000 0x00020000>; + }; + + /* QUPv3_1 GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Touchscreen I2C Instance */ + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 4 3 64 0xc>, + <&gpi_dma1 1 4 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 4 1 64 0xc>, + <&gpi_dma1 1 4 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + /* QUPv3_2 GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Secondary Tounch */ + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma2 0 7 3 64 0xc>, + <&gpi_dma2 1 7 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Secondary Tounch */ + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma2 0 7 1 64 0xc>, + <&gpi_dma2 1 7 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; }; + +#include "msm-arm-smmu-tuna-vm.dtsi" +#include "tuna-vm-dma-heaps.dtsi" diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi index 1a106540..e0d24717 100644 --- a/qcom/tuna.dtsi +++ b/qcom/tuna.dtsi @@ -20,6 +20,8 @@ #include #include #include +#include +#include / { model = "Qualcomm Technologies, Inc. Tuna"; @@ -36,7 +38,7 @@ }; chosen: chosen { - bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance"; + bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance page_poison=on cgroup.memory=nokmem,nosocket"; stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8"; }; @@ -44,11 +46,18 @@ ddr-regions { }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x2 0xc0000000 0x1 0x0>; + granule = <512>; + qcom,qmp = <&aoss_qmp>; + }; + firmware: firmware { qcom_scm: qcom_scm {}; }; - aliases { + aliases: aliases { serial0 = &qupv3_se7_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ mmc1 = &sdhc_2; /* SDC2 SD card slot */ @@ -648,6 +657,18 @@ interrupts = ; cap-based-alloc-and-pwr-collapse; + + llcc_perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; + }; + + gic-interrupt-router { + compatible = "qcom,gic-intr-routing"; + qcom,gic-class0-cpus = <&CPU0 &CPU1>; + qcom,gic-class1-cpus = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>; }; apps_rsc: rsc@17a00000 { @@ -710,6 +731,7 @@ qcom,mem-buf-msgq { compatible = "qcom,mem-buf-msgq"; + qcom,msgq-names = "trusted_vm", "oem_vm"; }; cam_rsc: rsc@adc8000 { @@ -813,6 +835,55 @@ }; }; + disp_crm: crm@af21000 { + label = "disp_crm"; + compatible = "qcom,disp-crm-v2"; + reg = <0xaf21000 0x6000>, <0xaf27000 0x400>, <0xaf27400 0x400>, + <0xaf27800 0x2000>, <0xaf29800 0x700>, <0xaf29f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = , + , + , + , + , + ; + interrupt-names = "disp_crm_drv0", + "disp_crm_drv1", + "disp_crm_drv2", + "disp_crm_drv3", + "disp_crm_drv4", + "disp_crm_drv5"; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2 3 4 5>; + qcom,sw-drv-ids = <0 1 2 3 4 5>; + }; + + cam_crm: crm@adcb000 { + label = "cam_crm"; + compatible = "qcom,cam-crm-v2"; + reg = <0xadcb000 0x1e00>, <0xadcce00 0x400>, <0xadcd200 0x400>, + <0xadcd600 0x2000>, <0xadcf600 0x700>, <0xadcfd00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = ; + interrupt-names = "cam_crm_drv0"; + clocks = <&camcc CAM_CC_DRV_AHB_CLK>; + qcom,hw-drv-ids = <0 1 2>; + qcom,sw-drv-ids = <0>; + }; + + pcie_crm: crm@1d01000 { + label = "pcie_crm"; + compatible = "qcom,pcie-crm-v2"; + reg = <0x1d01000 0x2000>, <0x1d03000 0x400>, <0x1d03400 0x400>, + <0x1d03800 0x2000>, <0x1d05800 0x700>, <0x1d05f00 0x100>; + reg-names = "base", "crm_b", "crm_b_pt", "crm_c", "crm_v", "common"; + interrupts = ; + interrupt-names = "pcie_crm_drv0"; + clocks = <&pcie_0_pipe_clk>; + qcom,hw-drv-ids = <0 1>; + qcom,sw-drv-ids = <0>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,tuna-pdc", "qcom,pdc"; reg = <0xb220000 0x10000>, <0x174000f0 0x64>; @@ -835,6 +906,16 @@ interrupt-controller; }; + adsp_sleepmon: adsp-sleepmon { + compatible = "qcom,adsp-sleepmon"; + qcom,rproc-handle = <&adsp_pas>; + }; + + pcie_pdc: pdc@b360000 { + compatible = "qcom,tuna-pcie-pdc", "qcom,pcie-pdc"; + reg = <0xb360000 0x10000>; + }; + adsp_pas: remoteproc-adsp@03000000 { compatible = "qcom,tuna-adsp-pas"; reg = <0x03000000 0x10000>; @@ -1059,6 +1140,66 @@ }; }; + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-qmc-dma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_dma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-qmc-cma { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; + qcom,glinkpkt-dev-name = "qmc_cma"; + qcom,glinkpkt-enable-ch-close; + }; + + qcom,glinkpkt-xpan_control { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "bt_cp_ctrl"; + qcom,glinkpkt-dev-name = "bt_cp_ctrl"; + }; + }; + sys-pm-vx@c320000 { compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna"; reg = <0xc320000 0x400>; @@ -1083,20 +1224,16 @@ tuivm { qcom,label = <0x08>; qcom,vmid = <45>; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; }; tlmm-vm-test { compatible = "qcom,tlmm-vm-test"; qcom,master; - tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0 - &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0 - &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0 - &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>; + tlmm-vm-gpio-list = <&tlmm 77 0 &tlmm 78 0 &tlmm 14 0 &tlmm 126 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 189 0 &tlmm 176 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0>; }; slimbam: bamdma@6c04000 { @@ -1460,6 +1597,19 @@ #size-cells = <1>; read-only; ranges; + feat_conf6: feat_conf6@0118 { + reg = <0x0118 0x4>; + }; + + feat_conf18: feat_conf18@0148 { + reg = <0x0148 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&feat_conf6>, <&feat_conf18>; + nvmem-cell-names = "feat_conf6", "feat_conf18"; }; clocks { @@ -1544,7 +1694,7 @@ sram@c3f0000 { compatible = "qcom,rpmh-stats-v4"; - reg = <0x0c3f0000 0x3ff>; + reg = <0x0c3f0000 0x400>; qcom,qmp = <&aoss_qmp>; ss-name = "modem", "wpss", "adsp", "adsp_island", "cdsp", "apss"; @@ -1577,7 +1727,7 @@ <&cpufreq_hw 3>; }; - cam_crm: syscon@adcd600 { + camcc_crm: syscon@adcd600 { compatible = "syscon"; reg = <0xadcd600 0x2000>; }; @@ -1595,7 +1745,7 @@ clock-names = "bi_tcxo", "sleep_clk", "iface"; - qcom,cam_crm-crmc = <&cam_crm>; + qcom,cam_crm-crmc = <&camcc_crm>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1619,7 +1769,8 @@ "bi_tcxo_ao", "sleep_clk", "iface"; - qcom,dispcc_crm-crmc = <&dispcc_crm>; + qcom,disp_crm-crmc = <&dispcc_crm>; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1680,13 +1831,16 @@ "gpll0_out_main_div"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; gxclkctl: clock-controller@3d68024 { - compatible = "qcom,dummycc"; - clock-output-names = "gxclkctl_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; + compatible = "qcom,tuna-gx_clkctl"; + reg = <0x3d68024 0x8>; + reg-name = "cc_base"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + vdd_gx-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; + #power-domain-cells = <1>; }; tcsrcc: clock-controller@1fbf000 { @@ -1703,6 +1857,7 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mxc-supply = <&VDD_MXC_LEVEL>; + vdd_mm_mxc_voter-supply = <&VDD_MM_MXC_VOTER_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, @@ -1711,6 +1866,7 @@ "bi_tcxo_ao", "sleep_clk", "iface"; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -1847,6 +2003,10 @@ clock-frequency = <32768>; }; + qti,smmu-proxy { + compatible = "smmu-proxy-sender"; + }; + clk_virt: interconnect@0 { compatible = "qcom,tuna-clk_virt"; #interconnect-cells = <1>; @@ -2039,6 +2199,9 @@ interconnect-names = "sdhc-ddr","cpu-sdhc"; operating-points-v2 = <&sdhc2_opp_table>; + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core_reset"; + qos0 { mask = <0xc0>; vote = <44>; @@ -2162,7 +2325,7 @@ qcom,bypass-pbl-rst-wa; qcom,max-cpus = <8>; - reset-gpios = <&tlmm 187 GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; @@ -2412,6 +2575,14 @@ }; }; + + qcom,qrtr-gunyah-oemvm { + compatible = "qcom,qrtr-gunyah"; + qcom,master; + gunyah-label = <8>; + peer-name = <4>; + }; + trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring { size = <0x4000>; gunyah-label = <0x11>; @@ -2549,6 +2720,67 @@ }; }; + qcom,test-dbl-tuivm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x4>; + }; + + qcom,test-dbl-oemvm { + compatible = "qcom,gh-dbl"; + qcom,label = <0x5>; + }; + + qcom,test-msgq-tuivm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x4>; + qcom,primary; + }; + + qcom,test-msgq-oemvm { + compatible = "qcom,gh-msgq-test"; + gunyah-label = <0x5>; + qcom,primary; + }; + + qcom,test-large-dmabuf-tuivm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xd>; + qcom,primary; + }; + + qcom,test-large-dmabuf-oemvm { + compatible = "qcom,gh-large-dmabuf-test"; + gunyah-label = <0xe>; + qcom,primary; + }; + + qcom,gh-qtimer@1742b000 { + compatible = "qcom,gh-qtmr"; + reg = <0x1742b000 0x1000>; + reg-names = "qtmr-base"; + interrupts = ; + interrupt-names = "qcom,qtmr-intr"; + qcom,primary; + }; + + qcom,gunyah-panic-notifier { + compatible = "qcom,gh-panic-notifier"; + qcom,primary-vm; + gunyah-label = <9>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + + dmesg-dump { + compatible = "qcom,dmesg-dump"; + qcom,primary-vm; + gunyah-label = <7>; + peer-name = <2>; + memory-region = <&vm_comm_mem>; + shared-buffer-size = <0x1000>; + }; + mmio_sram: mmio-sram@17D09400 { #address-cells = <2>; #size-cells = <2>; @@ -2981,31 +3213,37 @@ #include "ipcc-test-no-slpi.dtsi" &cam_cc_ipe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_ofe_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_0_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_1_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_tfe_2_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; status = "ok"; }; &cam_cc_titan_top_gdsc { + clocks = <&gcc GCC_CAMERA_AHB_CLK>; compatible = "qcom,gdsc"; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>; interconnect-names = "mmnoc"; @@ -3016,13 +3254,11 @@ &disp_cc_mdss_core_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; - status = "ok"; }; &disp_cc_mdss_core_int2_gdsc { clocks = <&gcc GCC_DISP_AHB_CLK>; parent-supply = <&VDD_MM_LEVEL>; - status = "ok"; }; &eva_cc_mvs0_gdsc { @@ -3077,25 +3313,21 @@ &gpu_cc_cx_gdsc { clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; }; &gx_clkctl_gx_gdsc { parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>; - status = "ok"; }; &video_cc_mvs0_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; - status = "ok"; }; &video_cc_mvs0c_gdsc { clocks = <&gcc GCC_VIDEO_AHB_CLK>; clock-names = "ahb_clk"; parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>; - status = "ok"; }; &reserved_memory { @@ -3166,6 +3398,8 @@ }; }; +#include "tuna-coresight.dtsi" +#include "tuna-debug.dtsi" #include "tuna-pinctrl.dtsi" #include "tuna-regulators.dtsi" #include "tuna-usb.dtsi" @@ -3178,3 +3412,12 @@ &qupv3_se7_2uart { status = "ok"; }; + +&qupv3_se3_i2c { + status = "ok"; + wcd_usbss: wcd939x_i2c@e { + compatible = "qcom,wcd939x-i2c"; + reg = <0xe>; + vdd-usb-cp-supply = <&L7B>; + }; +}; diff --git a/qcom/tuna7.dtsi b/qcom/tuna7.dtsi index 769de07c..38eb356c 100644 --- a/qcom/tuna7.dtsi +++ b/qcom/tuna7.dtsi @@ -8,4 +8,9 @@ model = "Qualcomm Technologies, Inc. Tuna 7"; compatible = "qcom,tuna"; qcom,msm-id = <681 0x10000>; + +}; + +&adsp_pas { + firmware-name = "adsp2.mdt", "adsp2_dtb.mdt"; }; diff --git a/qcom/waipio-vm.dtsi b/qcom/waipio-vm.dtsi index a34d5ec9..80e2cdda 100644 --- a/qcom/waipio-vm.dtsi +++ b/qcom/waipio-vm.dtsi @@ -210,7 +210,7 @@ peer-default; memory { qcom,label = <0x8>; - qcom,mem-info-tag = <0x2>; + qcom,mem-info-tag = <0x3>; allocate-base; }; }; @@ -287,7 +287,9 @@ tlmm-vm-mem-access { compatible = "qcom,tlmm-vm-mem-access"; - tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>; + tlmm-vm-gpio-list = <&tlmm 64 0 &tlmm 65 0 &tlmm 66 0 &tlmm 67 0 &tlmm 0 0 + &tlmm 4 0 &tlmm 86 0 &tlmm 87 0 &tlmm 16 0 &tlmm 17 0 + &tlmm 18 0 &tlmm 19 0 &tlmm 20 0 &tlmm 21 0>; }; vgic: interrupt-controller@17100000 {