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Change-Id: I50fc4d8be5ef4a92565908ad8fd9deeb15e82dfc
This commit is contained in:
Linux Build Service Account
2024-10-23 08:30:44 -07:00
parent 6defd49114 6047c61f82
commit a06a26e922
46 changed files with 10230 additions and 94 deletions
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2
bindings/arm/msm/sys-pm-violators.yaml
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@@ -26,6 +26,7 @@ properties:
- qcom,sys-pm-pineapple
- qcom,sys-pm-monaco-auto
- qcom,sys-pm-sun
- qcom,sys-pm-tuna
reg:
maxItems: 1
@@ -48,6 +49,7 @@ allOf:
contains:
enum:
- qcom,sys-pm-sun
- qcom,sys-pm-tuna
- qcom,sys-pm-pineapple
- qcom,sys-pm-parrot
- qcom,sys-pm-ravelin

1
bindings/clock/qcom,rpmhcc.yaml
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@@ -35,6 +35,7 @@ properties:
- qcom,pineapple-rpmh-clk
- qcom,sun-rpmh-clk
- qcom,parrot-rpmh-clk
- qcom,tuna-rpmh-clk
clocks:
maxItems: 1

130
bindings/mtd/qcom,msm-nand.yaml Normal file
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@@ -0,0 +1,130 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mtd/qcom,msm-nand.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Technologies, Inc. QPIC nand controller
maintainers:
- Pradeep P V K <quic_pragalla@quicinc.com>
- Sarthak Garg <quic_sartgarg@quicinc.com>
properties:
compatible:
const: qcom,msm-nand
reg:
maxItems: 2
reg-names:
maxItems: 2
clocks:
items:
- description: Core Clock.
clock-names:
items:
- const: core_clk
interrupts:
maxItems: 1
interrupt-names:
const: bam_irq
iommus:
items:
- description: phandle to apps_smmu node with sid mask.
qcom,iommu-dma:
description: |
default
Standard iommu translation behaviour. Calling iommu and DMA apis in
atomic context is not allowed.
bypass
DMA APIs will use 1-to-1 translation between dma_addr and phys_addr.
fastmap
DMA APIs will run faster, but use several orders of magnitude more
memory. Also allows using iommu and DMA apis in atomic context.
atomic
Allows using iommu and DMA apis in atomic context.
disabled
The iommu client is responsible for allocating an iommu domain.
enum:
- default
- bypass
- fastmap
- atomic
- disabled
dma-coherent: true
interconnects:
items:
- description: data path, nand to ddr.
interconnect-names:
items:
- const: nand-ddr
qcom,reg-adjustment-offset:
description: base adjustment offset value for the version registers.
$ref: /schemas/types.yaml#/definitions/uint32
nvmem-cells:
items:
- description: Phandle to nvmem cell that contains 'boot_config'.
nvmem-cell-names:
items:
- const: boot_conf
qcom,boot_dev_bits:
description: Number of FAST_BOOT bits in boot_config register.
$ref: /schemas/types.yaml#/definitions/uint32
qcom,nand_boot:
description: boot device detection values for NAND.
$ref: /schemas/types.yaml#/definitions/uint32-array
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sdx75.h>
qcom,nand@f9af0000 {
compatible = "qcom,msm-nand";
reg = <0xf9af0000 0x1000>,
<0xf9ac4000 0x8000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <0 279 0>;
interrupt-names = "bam_irq";
interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
interconnect-names = "nand-ddr";
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_QPIC_CLK>;
nvmem-cells = <&boot_config>;
nvmem-cell-names = "boot_conf";
qcom,boot_dev_bits = <0x4>;
qcom,nand_boot = <0x0>;
iommus = <&apps_smmu 0x100 0x3>;
qcom,iommu-dma = "atomic";
dma-coherent;
};

15
bindings/thermal/qcom-bcl-pmic5.yaml
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@@ -54,6 +54,20 @@ properties:
- const: bcl-lvl1
- const: bcl-lvl2
qcom,bcl-mon-vbat-only:
type: boolean
description: |
When this flag is defined, the BCL driver will only monitor
Vbat or both Ibat and Vbat based on runtime battery type and
Rsense input.
qcom,bcl-mon-ibat-only:
type: boolean
description: |
When this flag is defined, the BCL driver will only monitor
Ibat or don't monitor anything based on runtime battery type
and Rsense input.
qcom,pmic7-threshold:
type: boolean
description: |
@@ -79,5 +93,6 @@ examples:
<0x2 0x42 0x1 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1";
qcom,bcl-mon-vbat-only;
qcom,pmic7-threshold;
};

1
qcom/Makefile
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@@ -59,6 +59,7 @@ NOAPQ_TUNA_BOARDS += \
tuna-mtp-kiwi-overlay.dtbo \
tuna-mtp-overlay.dtbo \
tuna-mtp-qmp1000-overlay.dtbo \
tuna-mtp-kiwi-pmd802x-overlay.dtbo \
tuna-qrd-overlay.dtbo \
tuna-rcm-kiwi-overlay.dtbo \
tuna-rcm-overlay.dtbo \

10
qcom/ipcc-test-no-slpi.dtsi Normal file
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@@ -0,0 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "ipcc-test.dtsi"
&soc {
/delete-node/ ipcc-self-ping-slpi;
};

4239
qcom/kera-coresight.dtsi Normal file
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File diff suppressed because it is too large Load Diff

14
qcom/kera-reserved-memory.dtsi
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@@ -228,6 +228,20 @@
* varies.
*/
trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf3800000 0x0 0x4400000>;
reusable;
alignment = <0x0 0x400000>;
};
oem_vm_mem: oem_vm_region@f7c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
reusable;
alignment = <0x0 0x400000>;
};
llcc_lpi_mem: llcc_lpi_region@ff800000 {
no-map;
reg = <0x0 0xff800000 0x0 0x400000>;

262
qcom/kera.dtsi
View File

@@ -14,6 +14,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
/ {
model = "Qualcomm Technologies, Inc. Kera";
@@ -36,6 +37,8 @@
reserved_memory: reserved-memory {};
ddr-regions { };
firmware: firmware {
qcom_scm: qcom_scm { };
};
@@ -237,6 +240,25 @@
size = <0x0 0x2000000>;
linux,cma-default;
};
kinfo_mem: debug_kinfo_region {
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x1000>;
no-map;
};
va_md_mem: va_md_mem_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x1000000>;
};
ramoops_mem: ramoops-region {
alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
size = <0x0 0x200000>;
no-map;
};
};
&soc {
@@ -324,6 +346,11 @@
};
};
qcom,secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
apps_rsc: rsc@17a00000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
@@ -399,6 +426,129 @@
interrupt-controller;
};
adsp_pas: remoteproc-adsp@03000000 {
compatible = "qcom,kera-adsp-pas";
reg = <0x03000000 0x10000>;
status = "ok";
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
reg-names = "cx", "mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
interconnect-names = "rproc_ddr", "crypto_ddr";
firmware-name = "adsp.mdt", "adsp_dtb.mdt";
memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;
/* Inputs from ssc */
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
cdsp_pas: remoteproc-cdsp@32300000 {
compatible = "qcom,kera-cdsp-pas";
reg = <0x32300000 0x10000>;
status = "ok";
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx","mx","nsp";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
interconnect-names = "rproc_ddr", "crypto_ddr";
firmware-name = "cdsp.mdt", "cdsp_dtb.mdt";
memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>;
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>,
<&cdsp_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
modem_pas: remoteproc-mss@04080000 {
compatible = "qcom,kera-modem-pas";
reg = <0x4080000 0x10000>;
status = "ok";
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
reg-names = "cx", "mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,qmp = <&aoss_qmp>;
interconnect-names = "rproc_ddr", "crypto_ddr";
firmware-name = "modem.mdt", "modem_dtb.mdt";
memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma &dsm_partition_1_mem &dsm_partition_2_mem>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
tlmm: pinctrl@f000000 {
compatible = "qcom,kera-tlmm";
reg = <0xf000000 0x1000000>;
@@ -630,6 +780,11 @@
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
@@ -638,6 +793,64 @@
interrupt-names = "smp2p-sleepstate-in";
};
qcom,msm-imem@14680000 {
compatible = "qcom,msm-imem";
reg = <0x14680000 0x1000>;
ranges = <0x0 0x14680000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
modem_dsm@c98 {
compatible = "qcom,msm-imem-mss-dsm";
reg = <0xc98 0x10>;
};
sys_dbg@af8 {
compatible = "qcom,msm-imem-gpu-dump-skip";
reg = <0xb0c 0x4>;
};
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
@@ -651,12 +864,50 @@
status = "ok";
};
google,debug-kinfo {
compatible = "google,debug-kinfo";
memory-region = <&kinfo_mem>;
};
mini_dump_node {
compatible = "qcom,minidump";
status = "ok";
};
va_mini_dump {
compatible = "qcom,va-minidump";
memory-region = <&va_md_mem>;
status = "ok";
};
qcom_ramoops {
compatible = "qcom,ramoops";
memory-region = <&ramoops_mem>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem_heap>;
restrict-access;
};
qfprom: qfprom@221c8000 {
compatible = "qcom,kera-qfprom", "qcom,qfprom";
reg = <0x221c8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
@@ -770,9 +1021,18 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
gh-secure-vm-loader@2 {
compatible = "qcom,gh-secure-vm-loader";
qcom,pas-id = <35>;
qcom,vmid = <50>;
qcom,firmware-name = "cpusys_vm";
memory-region = <&cpusys_vm_mem>;
};
};
#include "tuna-gdsc.dtsi"
#include "ipcc-test-no-slpi.dtsi"
&cam_cc_ipe_0_gdsc {
compatible = "regulator-fixed";
@@ -906,7 +1166,9 @@
size = <0x0 0x4800000>;
};
};
#include "kera-debug.dtsi"
#include "kera-coresight.dtsi"
#include "kera-pinctrl.dtsi"
#include "kera-stub-regulators.dtsi"
#include "kera-usb.dtsi"

3
qcom/parrot-atp.dtsi
View File

@@ -53,6 +53,9 @@
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vccq2-parent-supply = <&S8E>;
qcom,vccq2-parent-max-microamp = <210000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;

3
qcom/parrot-idp.dtsi
View File

@@ -144,6 +144,9 @@
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vccq2-parent-supply = <&S8E>;
qcom,vccq2-parent-max-microamp = <210000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;

3
qcom/parrot-qrd.dtsi
View File

@@ -94,6 +94,9 @@
vccq2-supply = <&L19B>;
vccq2-max-microamp = <750000>;
qcom,vccq2-parent-supply = <&S8E>;
qcom,vccq2-parent-max-microamp = <210000>;
qcom,vddp-ref-clk-supply = <&L13B>;
qcom,vddp-ref-clk-max-microamp = <100>;

6
qcom/parrot-regulators.dtsi
View File

@@ -685,6 +685,11 @@
rpmh-regulator-smpe8 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "smpe8";
qcom,regulator-type = "pmic5-hfsmps";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_RET
RPMH_REGULATOR_MODE_AUTO>;
qcom,mode-threshold-currents = <0 200000>;
S8E:
pm6150l_s8: regulator-pm6150l-s8 {
regulator-name = "pm6150l_s8";
@@ -692,6 +697,7 @@
regulator-min-microvolt = <1816000>;
regulator-max-microvolt = <2040000>;
qcom,init-voltage = <1872000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_RET>;
};
};

6
qcom/pm7550ba.dtsi
View File

@@ -74,7 +74,7 @@
#size-cells = <0>;
status = "disabled";
oledb_vreg: oledb@fa00 {
pm7550ba_oledb_vreg: oledb@fa00 {
reg = <0xfa00>;
reg-names = "oledb_base";
regulator-name = "oledb";
@@ -83,7 +83,7 @@
qcom,swire-control;
};
ab_vreg: ab@f900 {
pm7550ba_ab_vreg: ab@f900 {
reg = <0xf900>;
reg-names = "ab_base";
regulator-name = "ab";
@@ -92,7 +92,7 @@
qcom,swire-control;
};
ibb_vreg: ibb@f800 {
pm7550ba_ibb_vreg: ibb@f800 {
reg = <0xf800>;
reg-names = "ibb_base";
regulator-name = "ibb";

14
qcom/pmih010x.dtsi
View File

@@ -250,6 +250,20 @@
#thermal-sensor-cells = <1>;
};
pmih010x_bcl2: bcl@4900 {
compatible = "qcom,bcl-v5";
reg = <0x4900 0x100>;
interrupts = <0x7 0x49 0x0 IRQ_TYPE_NONE>,
<0x7 0x49 0x1 IRQ_TYPE_NONE>,
<0x7 0x49 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
status = "disabled";
};
bcl_soc: bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;

129
qcom/pmiv010x.dtsi Normal file
View File

@@ -0,0 +1,129 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmiv010x_7: qcom,pmiv0108@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmiv010x_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmiv010x_gpios: pinctrl@8800 {
compatible = "qcom,pmiv0108-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmiv010x_eusb2_repeater: eusb2-repeater@fd00 {
compatible = "qcom,pmic-eusb2-repeater";
reg = <0xfd00>;
};
pmiv010x_vib: qcom,vibrator@df00 {
compatible = "qcom,qpnp-vibrator-ldo";
reg = <0xdf00>;
qcom,vib-ldo-volt-uv = <3000000>;
qcom,disable-overdrive;
};
pmiv010x_amoled: qcom,amoled {
compatible = "qcom,amoled-regulator";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
oledb_vreg: oledb@fa00 {
reg = <0xfa00>;
reg-names = "oledb_base";
regulator-name = "oledb";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <8000000>;
qcom,swire-control;
};
ab_vreg: ab@f900 {
reg = <0xf900>;
reg-names = "ab_base";
regulator-name = "ab";
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <5200000>;
qcom,swire-control;
};
ibb_vreg: ibb@f800 {
reg = <0xf800>;
reg-names = "ibb_base";
regulator-name = "ibb";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <6600000>;
qcom,swire-control;
regulator-allow-set-load;
};
};
pmiv010x_amoled_ecm: qcom,amoled-ecm@f900 {
compatible = "qcom,amoled-ecm";
reg = <0xf900>;
status = "disabled";
nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1",
"amoled-ecm-sdam2";
nvmem = <&pmk8550_sdam_13>, <&pmk8550_sdam_14>,
<&pmk8550_sdam_41>;
interrupt-names = "ecm-sdam0", "ecm-sdam1",
"ecm-sdam2";
interrupts = <0x7 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
<0x7 0x7d 0x1 IRQ_TYPE_EDGE_RISING>,
<0x7 0x98 0x1 IRQ_TYPE_EDGE_RISING>;
};
};
};
&thermal_zones {
pmiv010x_temp_alarm: pmiv010x_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmiv010x_tz>;
trips {
pmiv010x_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmiv010x_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "passive";
};
pmiv010x_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

83
qcom/pmxr2230.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
@@ -34,86 +35,30 @@
#interrupt-cells = <2>;
};
pmxr2230_pwm_1: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
led-controller {
compatible = "qcom,pm8350c-pwm";
#address-cells = <1>;
#size-cells = <0>;
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>;
nvmem-names = "lpg_chan_sdam", "lut_sdam";
qcom,lut-sdam-base = <0x45>;
qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
90 80 70 60 50 40 30 20 10 0>;
qcom,tick-duration-us = <7800>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};
pmxr2230_pwm_2: pwms@e900 {
compatible = "qcom,pwm-lpg";
reg = <0xe900>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <1>;
};
pmxr2230_pwm_4: pwms@eb00 {
compatible = "qcom,pwm-lpg";
reg = <0xeb00>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <1>;
};
pmxr2230_rgb: qcom,leds@ef00 {
compatible = "qcom,tri-led";
reg = <0xef00>;
red {
led@1 {
reg = <1>;
color = <LED_COLOR_ID_RED>;
label = "red";
pwms = <&pmxr2230_pwm_1 0 1000000>;
led-sources = <0>;
linux,default-trigger = "timer";
};
green {
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
label = "green";
pwms = <&pmxr2230_pwm_1 1 1000000>;
led-sources = <1>;
linux,default-trigger = "timer";
};
blue {
led@3 {
reg = <3>;
color = <LED_COLOR_ID_BLUE>;
label = "blue";
pwms = <&pmxr2230_pwm_1 2 1000000>;
led-sources = <2>;
linux,default-trigger = "timer";
};
};

4
qcom/sdxkova-idp-m2.dtsi
View File

@@ -5,3 +5,7 @@
&soc {
};
&qnand_1 {
status = "ok";
};

4
qcom/sdxkova-idp-mbb.dtsi
View File

@@ -30,6 +30,10 @@
operating-points-v2 = <&sdhc2_opp_table>;
};
&qnand_1 {
status = "ok";
};
&pmk8550_vadc {
/* PM8550BA Channel nodes */
pm7550ba_offset_ref {

31
qcom/sdxkova.dtsi
View File

@@ -1707,6 +1707,37 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
};
qnand_1: nand@1c98000 {
compatible = "qcom,msm-nand";
reg = <0x0 0x01c98000 0x0 0x1000>,
<0x0 0x01c9C000 0x0 0x1c000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_QPIC_CLK>;
interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
interconnect-names = "nand-ddr";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<0 0>,
/* Voting for max b/w on PNOC bus for now */
<1057800 725760>;
iommus = <&apps_smmu 0x100 0x3>;
qcom,iommu-dma = "atomic";
dma-coherent;
status = "disabled";
};
};
&gcc {

149
qcom/sun-qrd-sku1.dtsi
View File

@@ -96,3 +96,152 @@
&ibat_lvl1 {
temperature = <7000>;
};
&pmih010x_bcl {
qcom,bcl-mon-vbat-only;
status = "okay";
};
&pmih010x_bcl2 {
qcom,bcl-mon-ibat-only;
status = "okay";
};
&thermal_zones {
pmih010x-ibat2-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmih010x_bcl2 0>;
trips {
ibat2_lvl0:ibat2-lvl0 {
temperature = <6500>;
hysteresis = <200>;
type = "passive";
};
};
};
pmih010x-ibat2-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmih010x_bcl2 1>;
trips {
ibat2_lvl1:ibat2-lvl1 {
temperature = <7000>;
hysteresis = <200>;
type = "passive";
};
};
};
pmih010x-bcl2-lvl0 {
polling-delay-passive = <50>;
polling-delay = <0>;
thermal-sensors = <&pmih010x_bcl2 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl2_lvl0: b-bcl2-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
lbat2_modem0 {
trip = <&b_bcl2_lvl0>;
cooling-device = <&modem_bcl 1 1>;
};
lbat2_gpu0 {
trip = <&b_bcl2_lvl0>;
cooling-device = <&msm_gpu 1 1>;
};
};
};
pmih010x-bcl2-lvl1 {
polling-delay-passive = <50>;
polling-delay = <0>;
thermal-sensors = <&pmih010x_bcl2 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl2_lvl1: b-bcl2-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
lbat2_modem1 {
trip = <&b_bcl2_lvl1>;
cooling-device = <&modem_bcl 2 2>;
};
lbat2_gpu1 {
trip = <&b_bcl2_lvl1>;
cooling-device = <&msm_gpu 2 2>;
};
};
};
pmih010x-bcl2-lvl2 {
polling-delay-passive = <50>;
polling-delay = <0>;
thermal-sensors = <&pmih010x_bcl2 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl2_lvl2: b-bcl2-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
cooling-maps {
lbat2_gpu2 {
trip = <&b_bcl2_lvl2>;
cooling-device = <&msm_gpu 3 3>;
};
};
};
};

2
qcom/tuna-atp-overlay.dts
View File

@@ -7,6 +7,8 @@
/plugin/;
#include "tuna-atp.dtsi"
#include "tuna-pmih010x.dtsi"
#include "pmd802x.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna ATP";

1
qcom/tuna-cdp-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-cdp.dtsi"
#include "tuna-pmiv0108.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna CDP";

27
qcom/tuna-cdp.dtsi
View File

@@ -3,6 +3,9 @@
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
&qupv3_se4_i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -83,3 +86,27 @@
status = "ok";
};
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976310>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";
};

1
qcom/tuna-mtp-kiwi-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-mtp-kiwi.dtsi"
#include "tuna-pm7550ba.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";

18
qcom/tuna-mtp-kiwi-pmd802x-overlay.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include "tuna-mtp-kiwi.dtsi"
#include "tuna-pm7550ba-pmd802x.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + pmd802x";
compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
"qcom,mtp";
qcom,msm-id = <681 0x10000>, <655 0x10000>;
qcom,board-id = <8 2>;
};

1
qcom/tuna-mtp-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-mtp.dtsi"
#include "tuna-pm7550ba-pmd802x.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP";

1
qcom/tuna-mtp-qmp1000-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-mtp-qmp1000.dtsi"
#include "tuna-pm7550ba-pmd802x.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000";

28
qcom/tuna-mtp.dtsi
View File

@@ -2,6 +2,10 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
&qupv3_se4_i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,3 +86,27 @@
status = "ok";
};
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976310>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";
};

301
qcom/tuna-pcie.dtsi Normal file
View File

@@ -0,0 +1,301 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-tuna.h>
#include <dt-bindings/gpio/gpio.h>
&soc {
pcie0: pcie@1c00000 {
compatible = "qcom,pci-msm";
device_type = "pci";
reg = <0x1c00000 0x3000>,
<0x1c06000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>,
<0x1c03000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
msi-map = <0x0 &gic_its 0x1400 0x1>,
<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
perst-gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>;
wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_perst_default
&pcie0_clkreq_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_perst_default
&pcie0_clkreq_sleep
&pcie0_wake_default>;
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
vreg-1p2-supply = <&L4B>;
vreg-0p9-supply = <&L2B>;
vreg-qref-supply = <&L2B>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>;
qcom,vreg-0p9-voltage-level = <912000 880000 92070>;
qcom,vreg-qref-voltage-level = <880000 880000 46800>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&pcie_0_pipe_clk>;
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
"pcie_aux_clk", "pcie_cfg_ahb_clk",
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
"pcie_rate_change_clk",
"gcc_ddrss_pcie_sf_qtb_clk",
"pcie_aggre_noc_axi_clk",
"gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk",
"pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
<100000000>, <0>, <0>, <0>, <0>, <0>, <0>;
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
<0>, <0>, <0>, <1>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_0_BCR>,
<&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1400>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,drv-name = "lpass";
qcom,drv-l1ss-timeout-us = <5000>;
qcom,pcie-phy-ver = <112>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x00c0 0x01 0x0
0x00cc 0x62 0x0
0x00d0 0x02 0x0
0x0060 0xf8 0x0
0x0064 0x01 0x0
0x0000 0x93 0x0
0x0004 0x01 0x0
0x00e0 0x90 0x0
0x00e4 0x82 0x0
0x00f4 0x07 0x0
0x0070 0x02 0x0
0x0010 0x02 0x0
0x0074 0x16 0x0
0x0014 0x16 0x0
0x0078 0x36 0x0
0x0018 0x36 0x0
0x0110 0x08 0x0
0x00bc 0x0a 0x0
0x0120 0x42 0x0
0x0080 0x04 0x0
0x0084 0x0d 0x0
0x0020 0x0a 0x0
0x0024 0x1a 0x0
0x0088 0x41 0x0
0x0028 0x34 0x0
0x0090 0xab 0x0
0x0094 0xaa 0x0
0x0098 0x01 0x0
0x0030 0x55 0x0
0x0034 0x55 0x0
0x0038 0x01 0x0
0x0140 0x14 0x0
0x0164 0x34 0x0
0x003c 0x01 0x0
0x001c 0x04 0x0
0x0174 0x16 0x0
0x01bc 0x0f 0x0
0x0170 0xa0 0x0
0x11a4 0x38 0x0
0x10dc 0x11 0x0
0x1160 0xbf 0x0
0x1164 0xbf 0x0
0x1168 0xb7 0x0
0x116c 0xea 0x0
0x115c 0x3f 0x0
0x1174 0x5c 0x0
0x1178 0x9c 0x0
0x117c 0x1a 0x0
0x1180 0x89 0x0
0x1170 0xdc 0x0
0x1188 0x94 0x0
0x118c 0x5b 0x0
0x1190 0x1a 0x0
0x1194 0x89 0x0
0x10cc 0x00 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x10d8 0x0f 0x0
0x1118 0x1c 0x0
0x10f8 0x07 0x0
0x11f8 0x08 0x0
0x1600 0x00 0x0
0x0e84 0x15 0x0
0x0e90 0x3f 0x0
0x0ee4 0x02 0x0
0x0e40 0x06 0x0
0x0e3c 0x18 0x0
0x19a4 0x38 0x0
0x18dc 0x11 0x0
0x1960 0xbf 0x0
0x1964 0xbf 0x0
0x1968 0xb7 0x0
0x196c 0xea 0x0
0x195c 0x3f 0x0
0x1974 0x5c 0x0
0x1978 0x9c 0x0
0x197c 0x1a 0x0
0x1980 0x89 0x0
0x1970 0xdc 0x0
0x1988 0x94 0x0
0x198c 0x5b 0x0
0x1990 0x1a 0x0
0x1994 0x89 0x0
0x18cc 0x00 0x0
0x1808 0x09 0x0
0x1814 0x05 0x0
0x184c 0x08 0x0
0x1850 0x08 0x0
0x18d8 0x0f 0x0
0x1918 0x1c 0x0
0x18f8 0x07 0x0
0x19f8 0x08 0x0
0x1684 0x15 0x0
0x1690 0x3f 0x0
0x16e4 0x02 0x0
0x1640 0x06 0x0
0x163c 0x18 0x0
0x02dc 0x05 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x06a4 0x1e 0x0
0x06f4 0x27 0x0
0x03e0 0x0f 0x0
0x060c 0x1d 0x0
0x0614 0x07 0x0
0x0620 0xc1 0x0
0x0694 0x00 0x0
0x03d0 0x8c 0x0
0x0368 0x17 0x0
0x0370 0x2e 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
status = "disabled";
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@17110040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17110040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
};

393
qcom/tuna-pinctrl.dtsi
View File

@@ -4,6 +4,337 @@
*/
&tlmm {
i2s0_sck {
i2s0_sck_sleep: i2s0_sck_sleep {
mux {
pins = "gpio128";
function = "gpio";
};
config {
pins = "gpio128";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s0_sck_active: i2s0_sck_active {
mux {
pins = "gpio128";
function = "i2s0_sck";
};
config {
pins = "gpio128";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s0_ws {
i2s0_ws_sleep: i2s0_ws_sleep {
mux {
pins = "gpio129";
function = "gpio";
};
config {
pins = "gpio129";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s0_ws_active: i2s0_ws_active {
mux {
pins = "gpio129";
function = "i2s0_ws";
};
config {
pins = "gpio129";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s0_sd0 {
i2s0_sd0_sleep: i2s0_sd0_sleep {
mux {
pins = "gpio130";
function = "gpio";
};
config {
pins = "gpio130";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s0_sd0_active: i2s0_sd0_active {
mux {
pins = "gpio130";
function = "i2s0_data0";
};
config {
pins = "gpio130";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s0_sd1 {
i2s0_sd1_sleep: i2s0_sd1_sleep {
mux {
pins = "gpio131";
function = "gpio";
};
config {
pins = "gpio131";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s0_sd1_active: i2s0_sd1_active {
mux {
pins = "gpio131";
function = "i2s0_data1";
};
config {
pins = "gpio131";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s1_sck {
i2s1_sck_sleep: i2s1_sck_sleep {
mux {
pins = "gpio123";
function = "gpio";
};
config {
pins = "gpio123";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s1_sck_active: i2s1_sck_active {
mux {
pins = "gpio123";
function = "i2s1_sck";
};
config {
pins = "gpio123";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s1_ws {
i2s1_ws_sleep: i2s1_ws_sleep {
mux {
pins = "gpio125";
function = "gpio";
};
config {
pins = "gpio125";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s1_ws_active: i2s1_ws_active {
mux {
pins = "gpio125";
function = "i2s1_ws";
};
config {
pins = "gpio125";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s1_sd0 {
i2s1_sd0_sleep: i2s1_sd0_sleep {
mux {
pins = "gpio124";
function = "gpio";
};
config {
pins = "gpio124";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s1_sd0_active: i2s1_sd0_active {
mux {
pins = "gpio124";
function = "i2s1_data0";
};
config {
pins = "gpio124";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
i2s1_sd1 {
i2s1_sd1_sleep: i2s1_sd1_sleep {
mux {
pins = "gpio126";
function = "gpio";
};
config {
pins = "gpio126";
drive-strength = <2>; /* 2 mA */
bias-pull-down; /* PULL DOWN */
input-enable;
};
};
i2s1_sd1_active: i2s1_sd1_active {
mux {
pins = "gpio126";
function = "i2s1_data1";
};
config {
pins = "gpio126";
drive-strength = <8>; /* 8 mA */
bias-disable; /* NO PULL */
output-high;
};
};
};
/* WCD reset pin */
wcd_reset_active: wcd_reset_active {
mux {
pins = "gpio150";
function = "gpio";
};
config {
pins = "gpio150";
drive-strength = <16>;
output-high;
};
};
wcd_reset_sleep: wcd_reset_sleep {
mux {
pins = "gpio150";
function = "gpio";
};
config {
pins = "gpio150";
drive-strength = <16>;
bias-disable;
output-low;
};
};
/* WSA speaker reset pins North Pins*/
spkr_1_sd_n {
spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
mux {
pins = "gpio119";
function = "gpio";
};
config {
pins = "gpio119";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
input-enable;
};
};
spkr_1_sd_n_active: spkr_1_sd_n_active {
mux {
pins = "gpio119";
function = "gpio";
};
config {
pins = "gpio119";
drive-strength = <16>; /* 16 mA */
bias-disable;
output-high;
};
};
};
/* WSA speaker reset pins south Pins*/
spkr_2_sd_n {
spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
mux {
pins = "gpio183";
function = "gpio";
};
config {
pins = "gpio183";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
input-enable;
};
};
spkr_2_sd_n_active: spkr_2_sd_n_active {
mux {
pins = "gpio183";
function = "gpio";
};
config {
pins = "gpio183";
drive-strength = <16>; /* 16 mA */
bias-disable;
output-high;
};
};
};
qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
mux {
@@ -1584,21 +1915,21 @@
sdc2_on: sdc2_on {
clk {
pins = "gpio62";
function = "sdc2_clk";
function = "SDC2_CLK";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "gpio51";
function = "sdc2_cmd";
function = "SDC2_CMD";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "gpio63", "gpio120", "gpio48", "gpio49";
function = "sdc2_data";
function = "SDC2_DATA";
bias-pull-up;
drive-strength = <10>;
};
@@ -1638,8 +1969,8 @@
drive-strength = <2>;
};
};
/* touchscreen pins */
/* touchscreen pins */
pmx_ts_active {
ts_active: ts_active {
mux {
@@ -1700,4 +2031,58 @@
};
};
pcie0 {
pcie0_perst_default: pcie0_perst_default {
mux {
pins = "gpio33";
function = "gpio";
};
config {
pins = "gpio33";
drive-strength = <2>;
bias-pull-down;
};
};
pcie0_clkreq_default: pcie0_clkreq_default {
mux {
pins = "gpio118";
function = "pcie0_clk_req_n";
};
config {
pins = "gpio118";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_wake_default: pcie0_wake_default {
mux {
pins = "gpio81";
function = "gpio";
};
config {
pins = "gpio81";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
mux {
pins = "gpio118";
function = "gpio";
};
config {
pins = "gpio118";
drive-strength = <2>;
bias-pull-up;
input-enable;
};
};
};
};

81
qcom/tuna-pm7550ba-pmd802x.dtsi Normal file
View File

@@ -0,0 +1,81 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "tuna-pm7550ba.dtsi"
#include "pmd802x.dtsi"
/ {
qcom,pmic-id-size = <8>;
qcom,pmic-id = <0x0 0x0 0x0 0x0 0x57 0x0 0x0 0x4C>;
};
&pm7550ba_amoled {
status = "disabled";
};
&pm7550ba_amoled_ecm {
status = "disabled";
};
&pmic_glink_debug {
/delete-node/ i2c@104;
/delete-node/ spmi@200;
i2c@104 {
reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1500@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
qcom,smb1500@68 {
compatible = "qcom,i2c-pmic";
reg = <0x68>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
status = "ok";
/delete-node/ smb1398_1_iin;
/delete-node/ smb1398_1_ichg;
/delete-node/ smb1398_1_die_temp;
smb1500_1_iin {
reg = <0x1046901>;
label = "smb1393_1_iin";
};
smb1500_1_ichg {
reg = <0x1046902>;
label = "smb1393_1_ichg";
};
smb1500_1_die_temp {
reg = <0x1046903>;
label = "smb1393_1_die_temp";
};
smb1500_2_iin {
reg = <0x1046801>;
label = "smb1393_2_iin";
};
smb1500_2_ichg {
reg = <0x1046802>;
label = "smb1393_2_ichg";
};
smb1500_2_die_temp {
reg = <0x1046803>;
label = "smb1393_2_die_temp";
};
};

180
qcom/tuna-pm7550ba.dtsi
View File

@@ -5,6 +5,8 @@
#include "pm7550ba.dtsi"
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm7550ba.h>
/ {
qcom,pmic-id-size = <8>;
@@ -34,6 +36,126 @@
qcom,can-sleep;
};
};
i2c@104 {
reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1398@34 {
compatible = "qcom,i2c-pmic";
reg = <0x34>;
qcom,can-sleep;
};
};
/* SPMI bridge bus 1 with SMB1510 device */
spmi@200 {
reg = <0x200>;
#address-cells = <2>;
#size-cells = <0>;
qcom,bus-type = "spmi";
qcom,smb1510@d {
compatible = "qcom,spmi-pmic";
reg = <13 SPMI_USID>;
qcom,can-sleep;
};
};
};
&pmic_glink_adc {
status = "ok";
smb1398_1_iin {
reg = <0x1043401>;
label = "smb1393_1_iin";
};
smb1398_1_ichg {
reg = <0x1043402>;
label = "smb1393_1_ichg";
};
smb1398_1_die_temp {
reg = <0x1043403>;
label = "smb1393_1_die_temp";
};
};
&pmk8550_vadc {
pinctrl-0 = <&sys_therm_7_gpio6_default &sys_therm_6_gpio7_default>;
pinctrl-names = "default";
/* PM7550BA Channel nodes */
pm7550ba_offset_ref {
reg = <PM7550BA_ADC5_GEN3_OFFSET_REF>;
label = "pm7550ba_offset_ref";
qcom,pre-scaling = <1 1>;
};
pm7550ba_vref_1p25 {
reg = <PM7550BA_ADC5_GEN3_1P25VREF>;
label = "pm7550ba_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm7550ba_die_temp {
reg = <PM7550BA_ADC5_GEN3_DIE_TEMP>;
label = "pm7550ba_die_temp";
qcom,pre-scaling = <1 1>;
};
pm7550ba_vph_pwr {
reg = <PM7550BA_ADC5_GEN3_VPH_PWR>;
label = "pm7550ba_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pm7550ba_chg_temp {
reg = <PM7550BA_ADC5_GEN3_CHG_TEMP_V>;
label = "pm7550ba_chg_temp";
};
pm7550ba_iin_fb {
reg = <PM7550BA_ADC5_GEN3_IIN_FB>;
label = "pm7550ba_iin_fb";
};
pm7550ba_ichg_fb {
reg = <PM7550BA_ADC5_GEN3_ICHG_FB>;
label = "pm7550ba_ichg_fb";
};
pm7550ba_sys_therm_7 {
reg = <PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
label = "pm7550ba_sys_therm_7";
qcom,adc-tm-type = <1>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm7550ba_sys_therm_8 {
reg = <PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
label = "pm7550ba_sys_therm_8";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm7550ba_batt_therm {
reg = <PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU>;
label = "pm7550ba_batt_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
};
};
&pm7550ba_vib {
@@ -44,3 +166,61 @@
status = "okay";
};
&pm7550ba_tz {
io-channels = <&pmk8550_vadc PM7550BA_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
#cooling-cells = <2>;
};
&pm7550ba_gpios {
sys_therm_7_gpio6 {
sys_therm_7_gpio6_default: sys_therm_7_gpio6_default {
pins = "gpio6";
bias-high-impedance;
};
};
};
&thermal_zones {
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

35
qcom/tuna-pmic-overlay.dtsi
View File

@@ -11,7 +11,6 @@
#include "pm8550vs.dtsi"
#include "pmr735b.dtsi"
#include "pm8550ve.dtsi"
#include "pmd802x.dtsi"
#include "pm8010.dtsi"
&pm8550vs_g {
@@ -108,6 +107,12 @@
linux,can-disable;
};
};
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
};
&thermal_zones {
@@ -243,6 +248,25 @@
};
};
};
sys-therm-11 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};
&pmk8550_vadc {
@@ -342,6 +366,15 @@
qcom,adc-tm-type = <1>;
};
pmxr2230_sys_therm_11 {
reg = <PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>;
label = "pmxr2230_sys_therm_11";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pm8550vs_d_die_temp {
reg = <PM8550VX_ADC5_GEN3_DIE_TEMP(3)>;
label = "pm8550vs_d_die_temp";

200
qcom/tuna-pmih010x.dtsi Normal file
View File

@@ -0,0 +1,200 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pmih010x.dtsi"
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen4-pmih010x.h>
&pmic_glink_debug {
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
pmih010x_glink_debug: qcom,pmih010x-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
qcom,can-sleep;
};
};
i2c@104 {
reg = <0x104>; /* I2C instance 4 in ADSP for SE5 */
#address-cells = <1>;
#size-cells = <0>;
qcom,bus-type = "i2c";
qcom,smb1500@69 {
compatible = "qcom,i2c-pmic";
reg = <0x69>;
qcom,can-sleep;
};
};
};
&spmi0_debug_bus {
qcom,pmih010x-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&pmic_glink_adc {
status = "ok";
smb1500_1_iin {
reg = <0x1046901>;
label = "smb1393_1_iin";
};
smb1500_1_ichg {
reg = <0x1046902>;
label = "smb1393_1_ichg";
};
smb1500_1_die_temp {
reg = <0x1046903>;
label = "smb1393_1_die_temp";
};
};
&battery_charger {
qcom,thermal-mitigation-step = <500000>;
#cooling-cells = <2>;
};
&pmih010x_haptics {
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8550_sdam_46>;
};
&pmih010x_tz {
io-channels = <&pmk8550_vadc PMIH010X_ADC5_GEN4_DIE_TEMP>;
io-channel-names = "thermal";
};
&pmk8550_vadc {
pmih010x_sys_therm_8 {
reg = <PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU>;
label = "pmih010x_usb_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
qcom,adc5-gen4;
};
pmih010x_sys_therm_7 {
reg = <PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU>;
label = "pmih010x_wls_therm";
qcom,ratiometric;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
qcom,adc5-gen4;
};
pmih010x_offset_ref {
reg = <PMIH010X_ADC5_GEN4_OFFSET_REF>;
label = "pmih010x_offset_ref";
qcom,pre-scaling = <1 1>;
qcom,adc5-gen4;
};
pmih010x_vref_1p25 {
reg = <PMIH010X_ADC5_GEN4_1P25VREF>;
label = "pmih010x_vref_1p25";
qcom,pre-scaling = <1 1>;
qcom,adc5-gen4;
};
pmih010x_die_temp {
reg = <PMIH010X_ADC5_GEN4_DIE_TEMP>;
label = "pmih010x_die_temp";
qcom,pre-scaling = <1 1>;
qcom,adc5-gen4;
};
pmih010x_vph_pwr {
reg = <PMIH010X_ADC5_GEN4_VPH_PWR>;
label = "pmih010x_vph_pwr";
qcom,pre-scaling = <1 3>;
qcom,adc5-gen4;
};
pmih010x_vbat_sns_qbg {
reg = <PMIH010X_ADC5_GEN4_VBAT_SNS_QBG>;
label = "pmih010x_vbat_sns_qbg";
qcom,pre-scaling = <1 3>;
qcom,adc5-gen4;
};
pmih010x_iin {
reg = <PMIH010X_ADC5_GEN4_IIN>;
label = "pmih010x_iin";
qcom,adc5-gen4;
};
pmih010x_ichg_fb {
reg = <PMIH010X_ADC5_GEN4_ICHG_FB>;
label = "pmih010x_ichg_fb";
qcom,adc5-gen4;
};
pmih010x_chg_temp {
reg = <PMIH010X_ADC5_GEN4_CHG_TEMP>;
label = "pmih010x_chg_temp";
qcom,adc5-gen4;
};
pmih010x_lite_die_temp {
reg = <PMIH010X_ADC5_GEN4_TEMP_ALARM_LITE>;
label = "pmih010x_lite_die_temp";
qcom,pre-scaling = <1 1>;
qcom,adc5-gen4;
};
};
&thermal_zones {
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

186
qcom/tuna-pmiv0108.dtsi Normal file
View File

@@ -0,0 +1,186 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmiv0104.h>
#include "pmiv010x.dtsi"
&pmiv010x_gpios {
charger_skin_therm {
charger_skin_therm_default: charger_skin_therm_default {
pins = "gpio6";
bias-high-impedence;
};
};
};
&pmiv010x_amoled {
status= "disabled";
};
&pmiv010x_amoled_ecm {
status = "disabled";
};
&pmiv010x_tz {
io-channels = <&pmk8550_vadc PMIV0104_ADC5_GEN3_DIE_TEMP>;
io-channel-names = "thermal";
};
&battery_charger {
#cooling-cells = <2>;
qcom,thermal-mitigation-step = <500000>;
};
&pmk8550_vadc {
pinctrl-names = "default";
pinctrl-0 = <&charger_skin_therm_default &sys_therm_6_gpio7_default>;
pmiv010x_ref_gnd {
reg = <PMIV0104_ADC5_GEN3_OFFSET_REF>;
label = "pmiv010x_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pmiv010x_vref_1p25 {
reg = <PMIV0104_ADC5_GEN3_1P25VREF>;
label = "pmiv010x_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmiv010x_die_temp {
reg = <PMIV0104_ADC5_GEN3_DIE_TEMP>;
label = "pmiv010x_die_temp";
qcom,pre-scaling = <1 1>;
};
pmiv010x_vph_pwr {
reg = <PMIV0104_ADC5_GEN3_VPH_PWR>;
label = "pmiv010x_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pmiv010x_vbat_sns_qbg {
reg = <PMIV0104_ADC5_GEN3_VBAT_SNS_QBG>;
label = "pmiv010x_vbat_sns";
qcom,pre-scaling = <1 3>;
};
pmiv010x_chg_temp {
reg = <PMIV0104_ADC5_GEN3_CHG_TEMP>;
label = "pmiv010x_chg_temp";
qcom,pre-scaling = <1 1>;
};
pmiv010x_bat_therm {
reg = <PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU>;
label = "pmiv010x_bat_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
};
pmiv010x_bat_id {
reg = <PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU>;
label = "pmiv010x_bat_id";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K>;
};
pmiv010x_iin_fb {
reg = <PMIV0104_ADC5_GEN3_IIN_FB>;
label = "pmiv010x_iin_fb";
};
pmiv010x_ichg_fb {
reg = <PMIV0104_ADC5_GEN3_ICHG_FB>;
label = "pmiv010x_ichg_fb";
};
pmiv010x_sys_therm_7 {
reg = <PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
label = "pmiv010x_charger_skin_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
pmiv010x_sys_therm_8 {
reg = <PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
label = "pmiv010x_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
qcom,adc-tm-type = <1>;
};
};
&pmic_glink_debug {
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pmiv010x-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
qcom,can-sleep;
};
};
};
&spmi0_debug_bus {
qcom,pmiv010x-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
&thermal_zones {
sys-therm-7 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm-8 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8550_vadc PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

2
qcom/tuna-qrd-overlay.dts
View File

@@ -7,6 +7,8 @@
/plugin/;
#include "tuna-qrd.dtsi"
#include "tuna-pmih010x.dtsi"
#include "pmd802x.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna QRD";

29
qcom/tuna-qrd.dtsi
View File

@@ -2,6 +2,8 @@
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
&qupv3_se4_spi {
#address-cells = <1>;
@@ -86,3 +88,30 @@
status = "ok";
};
&sdhc_2 {
vdd-supply = <&L13B>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 976310>;
vdd-io-supply = <&L23B>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 5830>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_SDCC2_BCR>;
reset-names = "core_reset";
qcom,uses_level_shifter;
status = "ok";
};
&thermal_zones {
/delete-node/ sys-therm-11;
};

1
qcom/tuna-rcm-kiwi-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-rcm-kiwi.dtsi"
#include "tuna-pmiv0108.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";

1
qcom/tuna-rcm-overlay.dts
View File

@@ -7,6 +7,7 @@
/plugin/;
#include "tuna-rcm.dtsi"
#include "tuna-pmiv0108.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Tuna RCM";

1319
qcom/tuna-regulators.dtsi Normal file
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File diff suppressed because it is too large Load Diff

14
qcom/tuna-reserved-memory.dtsi
View File

@@ -233,6 +233,20 @@
* varies.
*/
trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf3800000 0x0 0x4400000>;
reusable;
alignment = <0x0 0x400000>;
};
oem_vm_mem: oem_vm_region@f7c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
reusable;
alignment = <0x0 0x400000>;
};
llcc_lpi_mem: llcc_lpi_region@ff800000 {
no-map;
reg = <0x0 0xff800000 0x0 0x400000>;

22
qcom/tuna-rumi.dtsi
View File

@@ -174,3 +174,25 @@
&APSS_OFF {
status = "disabled";
};
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};
&tsens2 {
status = "disabled";
};
&tsens3 {
status = "disabled";
};
&rpmhcc {
compatible = "fixed-clock";
clock-output-names = "rpmh_clocks";
clock-frequency = <19200000>;
};

1765
qcom/tuna-thermal.dtsi Normal file
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File diff suppressed because it is too large Load Diff

80
qcom/tuna-vm.dtsi
View File

@@ -187,6 +187,19 @@
allocate-base;
};
gpiomem0 {
vdevice-type = "iomem";
patch = "/soc/tlmm-vm-mem-access";
push-compatible = "qcom,tlmm-vm-mem-access";
peer-default;
memory {
qcom,label = <0x8>;
qcom,mem-info-tag = <0x3>;
allocate-base;
};
};
};
};
@@ -216,6 +229,73 @@
wakeup-source;
};
vm_tlmm_irq: vm-tlmm-irq@0 {
compatible = "qcom,tlmm-vm-irq";
reg = <0x0 0x0>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,tuna-vm-tlmm";
reg = <0x0F000000 0x1000000>;
interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
/* Valid pins */
gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>;
};
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
};
tlmm-vm-test {
compatible = "qcom,tlmm-vm-test";
pinctrl-names = "active", "sleep";
pinctrl-0 = <&qupv3_se1_7i2c_active>;
pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
};
pinctrl@f000000 {
qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins {
qupv3_se1_7i2c_active: qupv3_se1_7i2c_active {
mux {
pins = "gpio44";
function = "qup2_se7_l0";
};
config {
pins = "gpio44";
drive-strength = <2>;
bias-pull-up;
};
};
qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep {
mux {
pins = "gpio44";
function = "gpio";
};
config {
pins = "gpio44";
drive-strength = <2>;
};
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";

527
qcom/tuna.dtsi
View File

@@ -36,12 +36,14 @@
};
chosen: chosen {
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops";
bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance";
stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
};
reserved_memory: reserved-memory {};
ddr-regions { };
firmware: firmware {
qcom_scm: qcom_scm {};
};
@@ -91,6 +93,8 @@
cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_0>;
capacity-dmips-mhz = <1024>;
@@ -115,6 +119,8 @@
cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_1>;
capacity-dmips-mhz = <1024>;
@@ -135,9 +141,11 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 3>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_2>;
capacity-dmips-mhz = <1024>;
capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>;
L2_2: l2-cache {
compatible = "cache";
@@ -154,9 +162,11 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 3>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_3>;
capacity-dmips-mhz = <1024>;
capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>;
L2_3: l2-cache {
compatible = "cache";
@@ -173,9 +183,11 @@
cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 3>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_4>;
capacity-dmips-mhz = <1024>;
capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>;
L2_4: l2-cache {
compatible = "cache";
@@ -192,9 +204,11 @@
cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_5>;
capacity-dmips-mhz = <1024>;
capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>;
L2_5: l2-cache {
compatible = "cache";
@@ -211,9 +225,11 @@
cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_6>;
capacity-dmips-mhz = <1024>;
capacity-dmips-mhz = <1035>;
dynamic-power-coefficient = <121>;
L2_6: l2-cache {
compatible = "cache";
@@ -230,9 +246,11 @@
cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
cpu-release-addr = <0x0 0xE3940000>;
next-level-cache = <&L2_7>;
capacity-dmips-mhz = <1300>;
capacity-dmips-mhz = <1178>;
dynamic-power-coefficient = <295>;
L2_7: l2-cache {
compatible = "cache";
@@ -406,6 +424,7 @@
#include "msm-arm-smmu-tuna.dtsi"
#include "tuna-dma-heaps.dtsi"
#include "tuna-vm-dma-heaps.dtsi"
#include "tuna-pcie.dtsi"
&reserved_memory {
#address-cells = <2>;
@@ -521,15 +540,27 @@
};
};
msm_gpu: qcom,kgsl-3d0@3d00000 { };
intc: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
ranges;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x17100000 0x10000>, /* GICD */
<0x17180000 0x200000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
gic_its: msi-controller@0x17140000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x17140000 0x20000>;
};
};
qcom,hdcp {
@@ -647,6 +678,17 @@
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,tuna-rpmh-clk";
#clock-cells = <1>;
};
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC4";
qcom,llcc-bcm-name = "SH5";
};
};
};
@@ -1017,6 +1059,12 @@
};
};
sys-pm-vx@c320000 {
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna";
reg = <0xc320000 0x400>;
qcom,qmp = <&aoss_qmp>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,tuna-tlmm";
reg = <0x0f000000 0x1000000>;
@@ -1029,6 +1077,28 @@
qcom,gpios-reserved = <54 4 5 6 7 82 83 111 112>;
};
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
qcom,master;
tuivm {
qcom,label = <0x08>;
qcom,vmid = <45>;
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
};
};
tlmm-vm-test {
compatible = "qcom,tlmm-vm-test";
qcom,master;
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
&tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
&tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
&tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
};
slimbam: bamdma@6c04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>;
@@ -1383,6 +1453,15 @@
};
qfprom: qfprom@221c8000 {
compatible = "qcom,tuna-qfprom", "qcom,qfprom";
reg = <0x221c8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
@@ -1434,13 +1513,6 @@
};
};
rpmhcc: clock-controller {
compatible = "fixed-clock";
clock-output-names = "rpmh_clocks";
clock-frequency = <19200000>;
#clock-cells = <1>;
};
cambistmclkcc: clock-controller@1760000 {
compatible = "qcom,tuna-cambistmclkcc", "syscon";
reg = <0x1760000 0x6000>;
@@ -1456,6 +1528,54 @@
#reset-cells = <1>;
};
cpuss-sleep-stats@17800054 {
compatible = "qcom,cpuss-sleep-stats";
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
<0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
<0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>,
<0x178c0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
"seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <8>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats-v4";
reg = <0x0c3f0000 0x3ff>;
qcom,qmp = <&aoss_qmp>;
ss-name = "modem", "wpss", "adsp", "adsp_island",
"cdsp", "apss";
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-epss";
reg = <0x17D91000 0x1000>, <0x17D92000 0x1000>,
<0x17D93000 0x1000>, <0x17D94000 0x1000>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2", "freq-domain3";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int",
"dcvsh1_int",
"dcvsh2_int",
"dcvsh3_int";
#freq-domain-cells = <1>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>,
<&cpufreq_hw 1>,
<&cpufreq_hw 2>,
<&cpufreq_hw 3>;
};
cam_crm: syscon@adcd600 {
compatible = "syscon";
@@ -2443,8 +2563,6 @@
};
cpucp: qcom,cpucp@17400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,cpucp";
reg = <0x17d90000 0x2000>,
<0x17400000 0x10>;
@@ -2485,10 +2603,382 @@
compatible = "qcom,cpufreq-stats-v2";
};
llcc_pmu: llcc-pmu@24095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x24095000 0x300>;
reg-names = "lagg-base";
};
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
qcom,long-counter;
qcom,pmu-events-tbl =
< 0x0008 0xFF 0x02 0xFF >,
< 0x0011 0xFF 0x01 0xFF >,
< 0x0017 0xFF 0xFF 0xFF >,
< 0x0037 0xFF 0xFF 0xFF >,
< 0x1000 0xFF 0xFF 0xFF >;
};
ddr_freq_table: ddr-freq-table {
qcom,freq-tbl =
< 547000 >,
< 1353600 >,
< 1555200 >,
< 1708000 >,
< 2092800 >,
< 2736000 >,
< 3187200 >,
< 3686400 >,
< 4224000 >,
< 4761600 >;
};
llcc_freq_table: llcc-freq-table {
qcom,freq-tbl =
< 350000 >,
< 533000 >,
< 600000 >,
< 806000 >,
< 933000 >,
< 1066000 >,
< 1211200 >;
};
ddrqos_freq_table: ddrqos-freq-table {
qcom,freq-tbl =
< 0 >,
< 1 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <2>;
qcom,bus-width = <32>;
reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
qcom,shared-offset = <0x0090>;
};
};
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_llcc_dcvs_hw: llcc {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <1>;
qcom,bus-width = <16>;
qcom,freq-tbl = <&llcc_freq_table>;
llcc_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
};
llcc_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_ddrqos_dcvs_hw: ddrqos {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <3>;
qcom,bus-width = <1>;
qcom,freq-tbl = <&ddrqos_freq_table>;
ddrqos_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
};
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_fp>;
qcom,miss-ev = <0x1000>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 1075200 547000 >,
< 1401600 1555000 >,
< 2016000 2092000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
qcom,cpufreq-memfreq-tbl =
< 633600 547000 >,
< 940800 1555000 >,
< 1190400 1708000 >,
< 1401600 2092000 >,
< 1824000 2736000 >,
< 2073600 3187200 >,
< 2803200 3686400 >,
< 2918400 4224000 >,
< 3014400 4700000 >;
qcom,sampling-enabled;
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 633600 547000 >,
< 960000 1555000 >,
< 1228800 1708000 >,
< 1478400 2092000 >,
< 2169600 3187200 >,
< 2956800 3686400 >,
< 3187200 4224000 >,
< 3206400 4700000 >;
qcom,sampling-enabled;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 547000 >,
< 3187200 2092000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2169600 547000 >,
< 2956800 2092000 >,
< 3206400 4224000 >;
qcom,sampling-enabled;
};
};
llcc {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,sampling-path = <&llcc_dcvs_fp>;
qcom,miss-ev = <0x37>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 883200 350000 >,
< 1401600 533000 >,
< 2016000 600000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 633600 350000 >,
< 1190400 533000 >,
< 1401600 600000 >,
< 1824000 806000 >,
< 2803200 933000 >,
< 2918400 1066000 >,
< 3014400 1211000 >;
qcom,sampling-enabled;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 350000 >,
< 3014400 600000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
};
l3 {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,sampling-path = <&l3_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 364800 364800 >,
< 614400 518400 >,
< 748800 614400 >,
< 883200 806400 >,
< 979200 902400 >,
< 1075200 998400 >,
< 1286400 1209600 >,
< 1401600 1344000 >,
< 1632000 1497600 >,
< 1785600 1593600 >,
< 2016000 1804800 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 633600 518400 >,
< 940800 614400 >,
< 1190400 902400 >,
< 1401600 998400 >,
< 1632000 1209600 >,
< 2073600 1344000 >,
< 2438400 1497600 >,
< 2803200 1593600 >,
< 3014400 1804800 >;
qcom,sampling-enabled;
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 480000 364800 >,
< 633600 518400 >,
< 940800 614400 >,
< 1228800 902400 >,
< 1478400 1209600 >,
< 1920000 1344000 >,
< 2169600 1497600 >,
< 2515200 1593600 >,
< 3206400 1804800 >;
qcom,sampling-enabled;
};
prime-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 1920000 364800 >,
< 2512200 1209600 >,
< 3206400 1804800 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
};
ddrqos {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
qcom,sampling-path = <&ddrqos_dcvs_sp>;
qcom,miss-ev = <0x1000>;
ddrqos_gold_lat: gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 0 >,
< 3014400 1 >;
qcom,sampling-enabled;
};
ddrqos_prime_lat: prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 1478400 0 >,
< 3206400 1 >;
qcom,sampling-enabled;
};
ddrqos_prime_latfloor: prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2169600 0 >,
< 3206400 1 >;
qcom,sampling-enabled;
};
};
};
qcom_llcc_l3_vote: qcom,llcc-l3-vote {
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,secondary-map =
< 350000 364800 >,
< 533000 518400 >,
< 600000 614400 >,
< 806000 806400 >,
< 933000 902400 >,
< 1066000 998400 >,
< 1211200 1209600 >;
};
bwmon_llcc: qcom,bwmon-llcc@240B7300 {
compatible = "qcom,bwmon4";
reg = <0x240B7400 0x300>, <0x240B7300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,second-vote = <&qcom_llcc_l3_vote>;
};
bwmon_ddr: qcom,bwmon-ddr@24091000 {
compatible = "qcom,bwmon5";
reg = <0x24091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
};
#include "tuna-gdsc.dtsi"
#include "ipcc-test-no-slpi.dtsi"
&cam_cc_ipe_0_gdsc {
compatible = "qcom,gdsc";
@@ -2517,6 +3007,8 @@
&cam_cc_titan_top_gdsc {
compatible = "qcom,gdsc";
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
interconnect-names = "mmnoc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
@@ -2675,12 +3167,13 @@
};
#include "tuna-pinctrl.dtsi"
#include "tuna-stub-regulators.dtsi"
#include "tuna-regulators.dtsi"
#include "tuna-usb.dtsi"
#include "tuna-qupv3.dtsi"
#include "msm-rdbg.dtsi"
#include "tuna-pmic-overlay.dtsi"
#include "tuna-walt.dtsi"
#include "tuna-thermal.dtsi"
&qupv3_se7_2uart {
status = "ok";