diff --git a/bindings/arm/msm/sys-pm-violators.yaml b/bindings/arm/msm/sys-pm-violators.yaml
index 8ba5e418..a498fea3 100644
--- a/bindings/arm/msm/sys-pm-violators.yaml
+++ b/bindings/arm/msm/sys-pm-violators.yaml
@@ -26,6 +26,7 @@ properties:
       - qcom,sys-pm-pineapple
       - qcom,sys-pm-monaco-auto
       - qcom,sys-pm-sun
+      - qcom,sys-pm-tuna
 
   reg:
     maxItems: 1
@@ -48,6 +49,7 @@ allOf:
           contains:
             enum:
               - qcom,sys-pm-sun
+              - qcom,sys-pm-tuna
               - qcom,sys-pm-pineapple
               - qcom,sys-pm-parrot
               - qcom,sys-pm-ravelin
diff --git a/bindings/clock/qcom,rpmhcc.yaml b/bindings/clock/qcom,rpmhcc.yaml
index 20c801a4..70fa6032 100644
--- a/bindings/clock/qcom,rpmhcc.yaml
+++ b/bindings/clock/qcom,rpmhcc.yaml
@@ -35,6 +35,7 @@ properties:
       - qcom,pineapple-rpmh-clk
       - qcom,sun-rpmh-clk
       - qcom,parrot-rpmh-clk
+      - qcom,tuna-rpmh-clk
 
   clocks:
     maxItems: 1
diff --git a/bindings/mtd/qcom,msm-nand.yaml b/bindings/mtd/qcom,msm-nand.yaml
new file mode 100644
index 00000000..5831944a
--- /dev/null
+++ b/bindings/mtd/qcom,msm-nand.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mtd/qcom,msm-nand.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Technologies, Inc. QPIC nand controller
+
+maintainers:
+  - Pradeep P V K <quic_pragalla@quicinc.com>
+  - Sarthak Garg <quic_sartgarg@quicinc.com>
+
+properties:
+  compatible:
+    const: qcom,msm-nand
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    maxItems: 2
+
+  clocks:
+    items:
+      - description: Core Clock.
+
+  clock-names:
+    items:
+      - const: core_clk
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    const: bam_irq
+
+  iommus:
+    items:
+      - description: phandle to apps_smmu node with sid mask.
+
+  qcom,iommu-dma:
+    description: |
+      default
+        Standard iommu translation behaviour. Calling iommu and DMA apis in
+        atomic context is not allowed.
+      bypass
+        DMA APIs will use 1-to-1 translation between dma_addr and phys_addr.
+      fastmap
+        DMA APIs will run faster, but use several orders of magnitude more
+        memory. Also allows using iommu and DMA apis in atomic context.
+      atomic
+        Allows using iommu and DMA apis in atomic context.
+      disabled
+        The iommu client is responsible for allocating an iommu domain.
+    enum:
+      - default
+      - bypass
+      - fastmap
+      - atomic
+      - disabled
+
+  dma-coherent: true
+
+  interconnects:
+    items:
+      - description: data path, nand to ddr.
+
+  interconnect-names:
+    items:
+      - const: nand-ddr
+
+  qcom,reg-adjustment-offset:
+    description: base adjustment offset value for the version registers.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  nvmem-cells:
+    items:
+      - description: Phandle to nvmem cell that contains 'boot_config'.
+
+  nvmem-cell-names:
+    items:
+      - const: boot_conf
+
+  qcom,boot_dev_bits:
+    description: Number of FAST_BOOT bits in boot_config register.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  qcom,nand_boot:
+    description: boot device detection values for NAND.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/interconnect/qcom,sdx75.h>
+    qcom,nand@f9af0000 {
+      compatible = "qcom,msm-nand";
+      reg = <0xf9af0000 0x1000>,
+            <0xf9ac4000 0x8000>;
+      reg-names = "nand_phys",
+                  "bam_phys";
+      qcom,reg-adjustment-offset = <0x4000>;
+
+      interrupts = <0 279 0>;
+      interrupt-names = "bam_irq";
+
+      interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
+      interconnect-names = "nand-ddr";
+
+      clock-names = "core_clk";
+      clocks = <&rpmhcc RPMH_QPIC_CLK>;
+
+      nvmem-cells = <&boot_config>;
+      nvmem-cell-names = "boot_conf";
+      qcom,boot_dev_bits = <0x4>;
+      qcom,nand_boot = <0x0>;
+
+      iommus = <&apps_smmu 0x100 0x3>;
+      qcom,iommu-dma = "atomic";
+      dma-coherent;
+
+    };
diff --git a/bindings/thermal/qcom-bcl-pmic5.yaml b/bindings/thermal/qcom-bcl-pmic5.yaml
index 1ee636ab..a0c67869 100644
--- a/bindings/thermal/qcom-bcl-pmic5.yaml
+++ b/bindings/thermal/qcom-bcl-pmic5.yaml
@@ -54,6 +54,20 @@ properties:
       - const: bcl-lvl1
       - const: bcl-lvl2
 
+  qcom,bcl-mon-vbat-only:
+    type: boolean
+    description: |
+      When this flag is defined, the BCL driver will only monitor
+      Vbat or both Ibat and Vbat based on runtime battery type and
+      Rsense input.
+
+  qcom,bcl-mon-ibat-only:
+    type: boolean
+    description: |
+      When this flag is defined, the BCL driver will only monitor
+      Ibat or don't monitor anything based on runtime battery type
+      and Rsense input.
+
   qcom,pmic7-threshold:
     type: boolean
     description: |
@@ -79,5 +93,6 @@ examples:
                      <0x2 0x42 0x1 IRQ_TYPE_NONE>;
         interrupt-names = "bcl-lvl0",
                           "bcl-lvl1";
+        qcom,bcl-mon-vbat-only;
         qcom,pmic7-threshold;
     };
diff --git a/qcom/Makefile b/qcom/Makefile
index be4cf248..3f8b30be 100644
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -59,6 +59,7 @@ NOAPQ_TUNA_BOARDS += \
 		tuna-mtp-kiwi-overlay.dtbo \
 		tuna-mtp-overlay.dtbo \
 		tuna-mtp-qmp1000-overlay.dtbo \
+		tuna-mtp-kiwi-pmd802x-overlay.dtbo \
 		tuna-qrd-overlay.dtbo \
 		tuna-rcm-kiwi-overlay.dtbo \
 		tuna-rcm-overlay.dtbo \
diff --git a/qcom/ipcc-test-no-slpi.dtsi b/qcom/ipcc-test-no-slpi.dtsi
new file mode 100644
index 00000000..bf439c38
--- /dev/null
+++ b/qcom/ipcc-test-no-slpi.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "ipcc-test.dtsi"
+
+&soc {
+	/delete-node/ ipcc-self-ping-slpi;
+};
diff --git a/qcom/kera-coresight.dtsi b/qcom/kera-coresight.dtsi
new file mode 100644
index 00000000..0a23fa78
--- /dev/null
+++ b/qcom/kera-coresight.dtsi
@@ -0,0 +1,4239 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	ipcb_tgu: tgu@10b0e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+		reg = <0x10b0e000 0x1000>;
+		reg-names = "tgu-base";
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <4>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-ipcb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	spmi_tgu0: tgu@10b0f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+
+		reg = <0x10b0f000 0x1000>;
+		reg-names = "tgu-base";
+
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <9>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-spmi0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	spmi_tgu1: tgu@10b10000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+
+		reg = <0x10b10000 0x1000>;
+		reg-names = "tgu-base";
+
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <9>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-spmi1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	csr: csr@10001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x10001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+		qcom,blk-size = <1>;
+	};
+
+	swao_csr: csr@10b11000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x10b11000 0x1000>,
+		      <0x10b110f8 0x78>;
+		reg-names = "csr-base", "msr-base";
+
+		coresight-name = "coresight-swao-csr";
+
+		qcom,timestamp-support;
+		qcom,msr-support;
+		qcom,blk-size = <1>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10982000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10982000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	wpss_cti: cti@10882000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10882000 0x1000>;
+
+		status = "disabled";
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-wpss";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@109b0000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x109b0000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-trace-noc0";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@109b1000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x109b1000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-trace-noc1";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@109b2000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x109b2000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-trace-noc2";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10822000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10822000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-dlct";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10010000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10010000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-qdss";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti@10ba5000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10ba5000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-soccp";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,extended_cti;
+	};
+
+	cti@10cc2000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc2000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_dragonlink_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,extended_cti;
+		status = "disabled";
+	};
+
+	cti@10cc3000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cc3000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_dragonlink_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,extended_cti;
+		status = "disabled";
+	};
+
+	cti@10b85000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b85000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10802000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10802000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mss";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@138e0000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138e0000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@138f0000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138f0000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@13900000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x13900000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti_2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@138e1000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138e1000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti_3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10961000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10961000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-a6x_isdb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10962000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10962000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-a6x_gpmu";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10b42000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b42000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_lpi";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10b4b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b4b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_lpi_qdsp";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@1098b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1098b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing_qdsp";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@1088b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1088b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-wpss-q6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10813000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10813000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mss_vdsp6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@1080b000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x1080b000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mss_qdsp6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10b21000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b21000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-aoss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10d21000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d21000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_shrm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10b41000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b41000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_lpi_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10b51000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b51000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-lpass_lpi_cti_3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10cd1000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10cd1000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-tmess_rvss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	swao_cti: cti@10b00000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b00000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-swao";
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@138e1000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x138e1000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-apss_cti_3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10b35000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10b35000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_lpi";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10d05000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d05000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_center";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10d07000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10d07000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-ddr_chhm02";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10901000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10901000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-a6x_dragonlink";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10831000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10831000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-venus";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,extended_cti;
+	};
+
+	cti@10c62000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c62000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-mdss";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti@10a05000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10a05000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-camera";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+	};
+
+	cti@10982000 {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10982000 0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-turing";
+
+		qcom,extended_cti;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU0>;
+
+		coresight-name = "coresight-ete0";
+		qcom,skip-power-up;
+		atid = <1>;
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	ete1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU1>;
+
+		coresight-name = "coresight-ete1";
+		qcom,skip-power-up;
+		atid = <2>;
+		out-ports {
+			port {
+				ete1_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete1>;
+				};
+			};
+		};
+	};
+
+	ete2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU2>;
+
+		coresight-name = "coresight-ete2";
+		qcom,skip-power-up;
+		atid = <3>;
+		out-ports {
+			port {
+				ete2_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete2>;
+				};
+			};
+		};
+	};
+
+	ete3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU3>;
+
+		coresight-name = "coresight-ete3";
+		qcom,skip-power-up;
+		atid = <4>;
+		out-ports {
+			port {
+				ete3_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete3>;
+				};
+			};
+		};
+	};
+
+	ete4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU4>;
+
+		coresight-name = "coresight-ete4";
+		qcom,skip-power-up;
+		atid = <5>;
+		out-ports {
+			port {
+				ete4_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete4>;
+				};
+			};
+		};
+	};
+
+	ete5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU5>;
+
+		coresight-name = "coresight-ete5";
+		qcom,skip-power-up;
+		atid = <6>;
+		out-ports {
+			port {
+				ete5_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete5>;
+				};
+			};
+		};
+	};
+
+	ete6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU6>;
+
+		coresight-name = "coresight-ete6";
+		qcom,skip-power-up;
+		atid = <7>;
+		out-ports {
+			port {
+				ete6_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete6>;
+				};
+			};
+		};
+	};
+
+	ete7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU7>;
+
+		coresight-name = "coresight-ete7";
+		qcom,skip-power-up;
+		atid = <8>;
+		out-ports {
+			port {
+				ete7_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete7>;
+				};
+			};
+		};
+	};
+
+	funnel_ete {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-ete";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint =
+					<&ete0_out_funnel_ete>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ete_in_ete1: endpoint {
+				remote-endpoint =
+					<&ete1_out_funnel_ete>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ete_in_ete2: endpoint {
+				remote-endpoint =
+					<&ete2_out_funnel_ete>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ete_in_ete3: endpoint {
+				remote-endpoint =
+					<&ete3_out_funnel_ete>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ete_in_ete4: endpoint {
+				remote-endpoint =
+					<&ete4_out_funnel_ete>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_ete_in_ete5: endpoint {
+					remote-endpoint =
+					<&ete5_out_funnel_ete>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_ete_in_ete6: endpoint {
+					remote-endpoint =
+					<&ete6_out_funnel_ete>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_ete_in_ete7: endpoint {
+					remote-endpoint =
+					<&ete7_out_funnel_ete>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+	};
+
+	funnel_apss: funnel@13810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x13810000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_apss_in_funnel_ete: endpoint {
+					remote-endpoint =
+					<&funnel_ete_out_funnel_apss>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_apss_in_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_out_funnel_apss>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_apss_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_funnel_apss>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@138a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_llm_silver_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_gold: tpdm@138b0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138b0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-gold";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_llm_gold_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_llm_gold>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_ext: tpdm@138c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x138c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-ext";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_llm_ext_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_llm_ext>;
+				};
+			};
+		};
+	};
+
+	tpdm_int_cmb0:tpdm@13860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x13860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-int-cmb0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_int_cmb0_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_int_cmb0>;
+				};
+			};
+		};
+	};
+
+	tpdm_int_dsb: tpdm@13862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x13862000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-int-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_int_dsb_out_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_in_tpdm_int_dsb>;
+				};
+			};
+		};
+	};
+
+	tpda_apss: tpda@13864000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x13864000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-apss";
+
+		qcom,cmb-elem-size = <0 32>,
+				<1 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_apss_in_tpdm_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_silver_out_tpda_apss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_apss_in_tpdm_llm_gold: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_gold_out_tpda_apss>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_apss_in_tpdm_llm_ext: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_ext_out_tpda_apss>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				tpda_apss_in_tpdm_int_cmb0: endpoint {
+					remote-endpoint =
+					<&tpdm_int_cmb0_out_tpda_apss>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+				tpda_apss_in_tpdm_int_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_int_dsb_out_tpda_apss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				tpda_apss_out_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_in_tpda_apss>;
+				};
+			};
+		};
+	};
+
+	tpdm_gcc: tpdm@1082c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x1082c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-gcc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_gcc_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_gcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_video: tpdm@10830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-video";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_video_out_funnel_video: endpoint {
+					remote-endpoint =
+					<&funnel_video_in_tpdm_video>;
+				};
+			};
+		};
+	};
+
+	funnel_vide0: funnel@10832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10832000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-video";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_video_in_tpdm_video: endpoint {
+					remote-endpoint =
+					<&tpdm_video_out_funnel_video>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_video_out_tpda_dlct: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_in_funnel_video>;
+				};
+			};
+		};
+	};
+
+	tpdm_mdss: tpdm@10c60000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c60000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_mdss_out_funnel_mdss: endpoint {
+					remote-endpoint =
+					<&funnel_mdss_in_tpdm_mdss>;
+				};
+			};
+		};
+	};
+
+	tpdm_mdss_rscc: tpdm@10c61000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c61000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mdss-rscc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_mdss_rscc_out_funnel_mdss: endpoint {
+					remote-endpoint =
+					<&funnel_mdss_in_tpdm_mdss_rscc>;
+				};
+			};
+		};
+	};
+
+	funnel_mdss: funnel@10c63000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10c63000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-mdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_mdss_in_tpdm_mdss: endpoint {
+					remote-endpoint =
+					<&tpdm_mdss_out_funnel_mdss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_mdss_in_tpdm_mdss_rscc: endpoint {
+					remote-endpoint =
+					<&tpdm_mdss_rscc_out_funnel_mdss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_mdss_out_tpda_dlct_2: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_2_in_funnel_mdss>;
+					source = <&tpdm_mdss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_mdss_out_tpda_dlct_3: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_3_in_funnel_mdss>;
+					source = <&tpdm_mdss_rscc>;
+				};
+			};
+		};
+	};
+
+	tpdm_gfx: tpdm@10900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10900000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-gpu";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_gfx_out_funnel_gfx_dl: endpoint {
+					remote-endpoint =
+					<&funnel_gfx_dl_in_tpdm_gfx>;
+				};
+			};
+		};
+	};
+
+	funnel_gfx: funnel@10963000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10963000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gfx";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				funnel_gfx_out_funnel_gfx_dl: endpoint {
+				remote-endpoint =
+					<&funnel_gfx_dl_in_funnel_gfx>;
+				};
+			};
+		};
+	};
+
+	funnel_gfx_dl: funnel@10902000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10902000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gfx-dl";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_gfx_dl_in_tpdm_gfx: endpoint {
+					remote-endpoint =
+					<&tpdm_gfx_out_funnel_gfx_dl>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_gfx_dl_in_funnel_gfx: endpoint {
+					remote-endpoint =
+					<&funnel_gfx_out_funnel_gfx_dl>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_gfx_dl_out_tpda_dlct_15: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_15_in_funnel_gfx_dl>;
+					source = <&tpdm_gfx>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_gfx_dl_out_funnel_dlct_6: endpoint {
+					remote-endpoint =
+					<&funnel_dlct_6_in_funnel_gfx_dl>;
+				};
+			};
+		};
+	};
+
+	tpdm_wpss_dsb: tpdm@10880000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10880000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-wpss-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_wpss_dsb_out_funnel_wpss: endpoint {
+					remote-endpoint =
+					<&funnel_wpss_in_tpdm_wpss_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_wpss_cmb: tpdm@10881000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10881000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-wpss-cmb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_wpss_cmb_out_funnel_wpss: endpoint {
+					remote-endpoint =
+					<&funnel_wpss_in_tpdm_wpss_cmb>;
+				};
+			};
+		};
+	};
+
+
+	funnel_wpss: funnel@10883000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10883000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-wpss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_wpss_in_tpdm_wpss_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_wpss_dsb_out_funnel_wpss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_wpss_in_tpdm_wpss_cmb: endpoint {
+					remote-endpoint =
+					<&tpdm_wpss_cmb_out_funnel_wpss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				funnel_wpss_out_tpda_dlct_5: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_5_in_funnel_wpss>;
+					source = <&tpdm_wpss_dsb>;
+				};
+			};
+
+			port@1 {
+				funnel_wpss_out_tpda_dlct_6: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_6_in_funnel_wpss>;
+					source = <&tpdm_wpss_cmb>;
+				};
+			};
+		};
+	};
+
+	tpdm_turing: tpdm@10980000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10980000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_turing_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_tpdm_turing>;
+				};
+			};
+		};
+	};
+
+	tpdm_turing_llm: tpdm@10981000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10981000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing-llm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		atid = <78>;
+
+		out-ports {
+			port {
+				tpdm_turing_llm_out_funnel_turing: endpoint {
+					remote-endpoint =
+					<&funnel_turing_in_tpdm_turing_llm>;
+				};
+			};
+		};
+	};
+
+	funnel_turing: funnel@10983000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10983000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_turing_in_tpdm_turing: endpoint {
+					remote-endpoint =
+					<&tpdm_turing_out_funnel_turing>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_turing_in_tpdm_turing_llm: endpoint {
+					remote-endpoint =
+					<&tpdm_turing_llm_out_funnel_turing>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_turing_out_tpda_dlct_17: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_17_in_funnel_turing>;
+					source = <&tpdm_turing>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_turing_out_tpda_dlct_18: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_18_in_funnel_turing>;
+					source = <&tpdm_turing_llm>;
+				};
+			};
+
+		};
+	};
+
+	tpdm_ufs: tpdm@10c23000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c23000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ufs";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ufs_out_tpda_dlct_23: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_23_in_tpdm_ufs>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_llcc0: tpdm@10f82000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10f82000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-llcc0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ddr_llcc0_out_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_in_tpdm_ddr_llcc0>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_llcc2: tpdm@10f83000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10f83000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-llcc2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ddr_llcc2_out_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_in_tpdm_ddr_llcc2>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_dpm: tpdm@10d04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d04000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-dpm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ddr_dpm_out_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_in_tpdm_ddr_dpm>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_shrm: tpdm@10d03000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d03000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-shrm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ddr_shrm_out_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_in_tpdm_ddr_shrm>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_ch02: tpdm@10d06000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10d06000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr-ch02";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ddr_ch02_out_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_in_tpdm_ddr_ch02>;
+				};
+			};
+		};
+	};
+
+	ddr_tn: tn@10d00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000f0c00>;
+		reg = <0x10d00000 0x1000>;
+		reg-names = "traceNoc-base";
+
+		coresight-name = "coresight-tracenoc-ddr";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@7 {
+				reg = <7>;
+				tn_ddr_in_tpdm_ddr_llcc0: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_llcc0_out_tn_ddr>;
+				};
+			};
+
+			port@8 {
+				reg = <8>;
+				tn_ddr_in_tpdm_ddr_llcc2: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_llcc2_out_tn_ddr>;
+				};
+			};
+
+			port@9 {
+				reg = <9>;
+				tn_ddr_in_tpdm_ddr_dpm: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_dpm_out_tn_ddr>;
+				};
+			};
+
+			port@10 {
+				reg = <10>;
+				tn_ddr_in_tpdm_ddr_shrm: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_shrm_out_tn_ddr>;
+				};
+			};
+
+			port@11 {
+				reg = <11>;
+				tn_ddr_in_tpdm_ddr_ch02: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_ch02_out_tn_ddr>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				tn_ddr_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tn_ddr>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr_lpicc {
+		compatible = "arm,coresight-dummy-source";
+		coresight-name = "coresight-tpdm-ddr-lpicc";
+		trace-name = "tracenoc-ddr-lpi";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				tpdm_ddr_lpicc_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_tpdm_ddr_lpicc>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				ddr_lpicc_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_ddr_lpicc>;
+				};
+			};
+		};
+	};
+
+	lpass_stm: lpass-stm {
+		compatible = "arm,coresight-dummy-source";
+		coresight-name = "coresight-lpass-stm";
+		trace-name = "lpass-stm";
+		atid = <25>;
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				lpass_stm_out_funnel_lpass_lpi_1: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_1_in_lpass_stm>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				lpass_stm_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_lpass_stm>;
+				};
+			};
+
+		};
+	};
+
+	tpdm_lpass_lpi {
+		compatible = "arm,coresight-dummy-source";
+		coresight-name = "coresight-tpdm-lpass-lpi";
+
+		trace-name = "tpda-lpass-lpi";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				tpdm_lpass_lpi_out_funnel_lpass_lpi_1: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_1_in_tpdm_lpass_lpi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				lpass_lpi_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_lpass_lpi>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass_audio {
+		compatible = "arm,coresight-dummy-source";
+		coresight-name = "coresight-tpdm-lpass-audio";
+
+		trace-name = "tpda-lpass-audio";
+		status = "disabled";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				tpdm_lpass_audio_out_funnel_lpass_lpi_1: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_1_in_tpdm_lpass_audio>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				lpass_audio_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_lpass_audio>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass_rscc {
+		compatible = "arm,coresight-dummy-source";
+		coresight-name = "coresight-tpdm-lpass-rscc";
+
+		trace-name = "tpda-lpass-rscc";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				tpdm_lpass_rscc_out_funnel_lpass_lpi_1: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_1_in_tpdm_lpass_rscc>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				lpass_rscc_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_lpass_rscc>;
+				};
+			};
+		};
+	};
+
+	audio_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-audio-etm0";
+		qcom,atid-num = <2>;
+		trace-name = "audio-etm0";
+		atid = <40 41>;
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				audio_etm0_out_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_in_audio_etm0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				audio_etm0_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_audio_etm0>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass_crdl: tpdm@10bb4000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10bb4000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-lpass-crdl";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_lpass_crdl_out_tn_lpass: endpoint {
+					remote-endpoint =
+					<&tn_lpass_in_tpdm_lpass_crdl>;
+				};
+			};
+		};
+	};
+
+	tn_lpass: tn@10b80000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000f0c00>;
+		reg = <0x10b80000 0x3400>;
+		reg-names = "traceNoc-base";
+
+		coresight-name = "coresight-tracenoc-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,interconnect-trace-noc;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tn_lpass_in_tpdm_lpass_crdl: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_crdl_out_tn_lpass>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tn_lpass_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tn_lpass>;
+				};
+			};
+		};
+	};
+
+	funnel_lpass_lpi_1 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-lpass_lpi_1";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_lpass_lpi_1_in_lpass_stm: endpoint {
+					remote-endpoint =
+					<&lpass_stm_out_funnel_lpass_lpi_1>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_lpass_lpi_1_in_tpdm_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_lpi_out_funnel_lpass_lpi_1>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_lpass_lpi_1_in_tpdm_lpass_rscc: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_rscc_out_funnel_lpass_lpi_1>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_lpass_lpi_1_in_tpdm_lpass_audio: endpoint {
+					remote-endpoint =
+					<&tpdm_lpass_audio_out_funnel_lpass_lpi_1>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_lpass_lpi_1_out_funnel_lpass_lpi_0: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_0_in_funnel_lpass_lpi_1>;
+				};
+			};
+		};
+	};
+
+	funnel_lpass_lpi_0 {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-lpass_lpi_0";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_lpass_lpi_in_audio_etm0: endpoint {
+					remote-endpoint =
+					<&audio_etm0_out_funnel_lpass_lpi>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_lpass_lpi_0_in_funnel_lpass_lpi_1: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_1_out_funnel_lpass_lpi_0>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_lpass_lpi_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_lpass_lpi>;
+				};
+			};
+		};
+	};
+
+	tpdm_rscc: tpdm@10c70000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c70000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-pcie-rscc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_rscc_out_tpda_rscc: endpoint {
+					remote-endpoint =
+					<&tpda_rscc_in_tpdm_rscc>;
+				};
+			};
+		};
+	};
+
+	tpda_pcie_rscc: tpda@10c71000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10c71000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-pcie-rscc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		qcom,cmb-elem-size = <0 8>;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_rscc_in_tpdm_rscc: endpoint {
+					remote-endpoint =
+					<&tpdm_rscc_out_tpda_rscc>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tpda_pcie_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpda_pcie>;
+				};
+			};
+		};
+	};
+
+	tpdm_titan: tpdm@10a04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10a04000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-titan-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		static = "disabled";
+
+		out-ports {
+			port {
+				tpdm_titan_dsb_out_tn_titan: endpoint {
+					remote-endpoint =
+					<&tn_titan_in_tpdm_titan_dsb>;
+				};
+			};
+		};
+	};
+
+	tn_titan: tn@10a00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000f0c00>;
+		reg = <0x10a00000 0x1000>;
+		reg-names = "traceNoc-base";
+
+		coresight-name = "coresight-tracenoc-titan";
+
+		status = "disabled";
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,trace-noc-v2;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@5 {
+				reg = <5>;
+				tn_titan_in_tpdm_titan_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_titan_dsb_out_tn_titan>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tn_titan_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tn_titan>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess_prng: tpdm@10cc9000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc9000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-tmess-prng";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_tmess_prng_out_tpda_tmess: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_in_tpdm_tmess_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess0: tpdm@10cc0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-tmess-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,hw-enable-check;
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_tmess0_out_tpda_tmess: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_in_tpdm_tmess0>;
+				};
+			};
+		};
+	};
+
+	tpdm_tmess1: tpdm@10cc1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10cc1000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-tmess-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		qcom,hw-enable-check;
+
+		out-ports {
+			port {
+				tpdm_tmess1_out_tpda_tmess: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_in_tpdm_tmess1>;
+				};
+			};
+		};
+	};
+
+	tpda_tmess: tpda@10cc4000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10cc4000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-tmess";
+
+		qcom,dsb-elem-size = <0 32>;
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <2 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_tmess_in_tpdm_tmess_prng: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess_prng_out_tpda_tmess>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_tmess_in_tpdm_tmess0: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess0_out_tpda_tmess>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_tmess_in_tpdm_tmess1: endpoint {
+					remote-endpoint =
+					<&tpdm_tmess1_out_tpda_tmess>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tpda_tmess_out_funnel_tmess: endpoint {
+					remote-endpoint =
+					<&funnel_tmess_in_tpda_tmess>;
+				};
+			};
+		};
+	};
+
+	funnel_tmess: funnel@10cc5000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10cc5000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-tmess";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_tmess_in_tpda_tmess: endpoint {
+					remote-endpoint =
+					<&tpda_tmess_out_funnel_tmess>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_tmess_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_funnel_tmess>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem_rscc {
+		compatible = "qcom,coresight-static-tpdm";
+		coresight-name = "coresight-tpdm-modem-rscc";
+
+		out-ports {
+			port {
+				tpdm_modem_rscc_out_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_in_tpdm_modem_rscc>;
+				};
+			};
+		};
+	};
+
+	modem-etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-modem-etm0";
+		qcom,atid-num = <2>;
+		atid = <36 37>;
+		trace-name = "modem-etm0";
+		qcom,secure-component;
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				modem_etm0_out_funnel_modem_q6_dup: endpoint {
+					remote-endpoint =
+						<&funnel_modem_q6_dup_in_modem_etm0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				modem_etm0_out_qmi: endpoint {
+					remote-endpoint =
+						<&qmi_in_modem_etm0>;
+				};
+			};
+		};
+	};
+
+	tmc_modem: tmc-modem {
+		compatible = "qcom,coresight-secure-etr";
+
+		coresight-name = "coresight-modem-etr1";
+
+		real-name = "coresight-tmc-etr1";
+		qdss,buffer-size = <0x2000000>;
+		qcom,secure-component;
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0x108>;
+		csr-irqctrl-offset = <0x70>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_modem_in_replicator_dummy: endpoint {
+					remote-endpoint =
+					<&replicator_dummy_out_tmc_modem>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tmc_modem_out_qmi: endpoint {
+					remote-endpoint =
+					<&qmi_in_tmc_modem>;
+				};
+			};
+		};
+	};
+
+	modem0-qmi {
+		compatible = "qcom,coresight-qmi";
+
+		coresight-name = "coresight-qmi-modem0";
+		qcom,inst-id = <2>;
+
+		in-ports {
+			port@0 {
+				reg = <0>;
+				qmi_in_modem_etm0: endpoint {
+					remote-endpoint =
+						<&modem_etm0_out_qmi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				qmi_in_tmc_modem: endpoint {
+					remote-endpoint =
+						<&tmc_modem_out_qmi>;
+				};
+			};
+		};
+	};
+
+	funnel_modem_q6_dup: funnel@1080d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x1080d000 0x1000>,
+			<0x1080c000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-modem_q6_dup";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,duplicate-funnel;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_modem_q6_dup_in_modem_etm0: endpoint {
+					remote-endpoint =
+					<&modem_etm0_out_funnel_modem_q6_dup>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_modem_q6_dup_out_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_in_funnel_modem_q6_dup>;
+				};
+			};
+		};
+	};
+
+	modem_diag: modem_diag {
+		compatible = "arm,coresight-dummy-source";
+
+		coresight-name = "coresight-modem-diag";
+		atid = <50>;
+
+		out-ports {
+			port {
+				modem_diag_out_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_in_modem_diag>;
+				};
+			};
+		};
+	};
+
+	funnel_modem_q6: funnel@1080c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x1080c000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-modem_q6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_modem_q6_in_funnel_modem_q6_dup: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_dup_out_funnel_modem_q6>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_modem_q6_in_modem_diag: endpoint {
+					remote-endpoint =
+					<&modem_diag_out_funnel_modem_q6>;
+				};
+			};
+
+			port@3 {
+				funnel_modem_q6_in_tpdm_modem_rscc: endpoint {
+					remote-endpoint =
+					<&tpdm_modem_rscc_out_funnel_modem_q6>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_modem_q6_out_funnel_modem_dl: endpoint {
+					remote-endpoint =
+					<&funnel_modem_dl_in_funnel_modem_q6>;
+				};
+			};
+		};
+	};
+
+	modem2-etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-modem2-etm0";
+		qcom,atid-num = <1>;
+		atid = <39>;
+		trace-name = "modem2-etm0";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				modem2_etm0_out_funnel_modem: endpoint {
+					remote-endpoint =
+						<&funnel_modem_in_modem2_etm0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				modem2_etm0_out_qmi: endpoint {
+					remote-endpoint =
+						<&qmi_in_modem2_etm0>;
+				};
+			};
+		};
+	};
+
+	modem2-qmi {
+		compatible = "qcom,coresight-qmi";
+
+		coresight-name = "coresight-qmi-modem2";
+		qcom,inst-id = <11>;
+
+		in-ports {
+			port {
+				qmi_in_modem2_etm0: endpoint {
+					remote-endpoint =
+						<&modem2_etm0_out_qmi>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem0: tpdm@10800000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10800000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-modem-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_modem0_out_tpda_modem: endpoint {
+					remote-endpoint =
+					<&tpda_modem_in_tpdm_modem0>;
+				};
+			};
+		};
+	};
+
+	tpda_modem: tpda@10803000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10803000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-modem";
+
+		qcom,dsb-elem-size = <0 32>;
+		qcom,cmb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_modem_in_tpdm_modem0: endpoint {
+					remote-endpoint =
+					<&tpdm_modem0_out_tpda_modem>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_modem_in_tpdm_modem1: endpoint {
+					remote-endpoint =
+					<&tpdm_modem1_out_tpda_modem>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tpda_modem_out_funnel_modem_dl: endpoint {
+					remote-endpoint =
+					<&funnel_modem_dl_in_tpda_modem>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem1 {
+		compatible = "qcom,coresight-static-tpdm";
+		coresight-name = "coresight-tpdm-modem-1";
+
+		out-ports {
+			port {
+				tpdm_modem1_out_tpda_modem: endpoint {
+					remote-endpoint =
+					<&tpda_modem_in_tpdm_modem1>;
+				};
+			};
+		};
+	};
+
+	funnel_modem_dl: funnel@10804000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10804000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-modem_dl";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_modem_dl_in_tpda_modem: endpoint {
+					remote-endpoint =
+					<&tpda_modem_out_funnel_modem_dl>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_modem_in_modem2_etm0: endpoint {
+					remote-endpoint =
+					<&modem2_etm0_out_funnel_modem>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_modem_dl_in_funnel_modem_q6: endpoint {
+					remote-endpoint =
+					<&funnel_modem_q6_out_funnel_modem_dl>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_modem_dl_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_funnel_modem_dl>;
+				};
+			};
+		};
+	};
+
+	tpdm_soccp: tpdm@10ba4000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10ba4000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-soccp";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_soccp_crdl_out_tn_soccp: endpoint {
+					remote-endpoint =
+					<&tn_soccp_in_tpdm_soccp_crdl>;
+				};
+			};
+		};
+	};
+
+	tn_soccp: tn@10ba0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000f0c00>;
+		reg = <0x10ba0000 0x1000>;
+		reg-names = "traceNoc-base";
+
+		coresight-name = "coresight-tracenoc-soccp";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,interconnect-trace-noc;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tn_soccp_in_tpdm_soccp_crdl: endpoint {
+					remote-endpoint =
+					<&tpdm_soccp_crdl_out_tn_soccp>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tn_soccp_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tn_soccp>;
+				};
+			};
+		};
+	};
+
+	tpdm_prng: tpdm@10841000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10841000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-prng";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_prng_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_prng>;
+				};
+			};
+		};
+	};
+
+	tpdm_qm: tpdm@109d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109d0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-qm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_qm_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_qm>;
+				};
+			};
+		};
+	};
+
+	tpdm_vsense: tpdm@10840000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10840000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-vsense";
+		status = "disabled";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_vsense_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_vsense>;
+				};
+			};
+		};
+	};
+
+	tpdm_ipa: tpdm@10c22000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c22000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ipa";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ipa_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_ipa>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc5_1: tpdm@10c21000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c21000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-sdcc1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_sdcc5_1_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_sdcc5_1>;
+				};
+			};
+		};
+	};
+
+	tpdm_sdcc5_2: tpdm@10c20000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10c20000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-sdcc2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_sdcc5_2_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_sdcc5_2>;
+				};
+			};
+		};
+	};
+
+	audio-qmi {
+		compatible = "qcom,coresight-qmi";
+
+		coresight-name = "coresight-qmi-auido";
+		qcom,inst-id = <5>;
+
+		in-ports {
+			port@0 {
+				reg = <0>;
+				qmi_in_ddr_lpicc: endpoint {
+					remote-endpoint =
+						<&ddr_lpicc_out_qmi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				qmi_in_audio_etm0: endpoint {
+					remote-endpoint =
+						<&audio_etm0_out_qmi>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				qmi_in_lpass_stm: endpoint {
+					remote-endpoint =
+						<&lpass_stm_out_qmi>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				qmi_in_lpass_lpi: endpoint {
+					remote-endpoint =
+						<&lpass_lpi_out_qmi>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				qmi_in_lpass_rscc: endpoint {
+					remote-endpoint =
+						<&lpass_rscc_out_qmi>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				qmi_in_lpass_audio: endpoint {
+					remote-endpoint =
+						<&lpass_audio_out_qmi>;
+				};
+			};
+
+		};
+	};
+
+	tpdm_dlct_dsb: tpdm@10820000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10820000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-dlct-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_dlct_dsb_out_tpda_dlct_26: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_26_in_tpdm_dlct_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_dlct_cmb: tpdm@10821000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10821000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-dlct-cmb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_dlct_cmb_out_tpda_dlct_27: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_27_in_tpdm_dlct_cmb>;
+				};
+			};
+		};
+	};
+
+	tpda_dlct: tpda@10823000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10823000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-dlct";
+
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <2 32>,
+				     <3 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_dlct_in_funnel_video: endpoint {
+					remote-endpoint =
+					<&funnel_video_out_tpda_dlct>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_dlct_2_in_funnel_mdss: endpoint {
+					remote-endpoint =
+					<&funnel_mdss_out_tpda_dlct_2>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				tpda_dlct_3_in_funnel_mdss: endpoint {
+					remote-endpoint=
+					<&funnel_mdss_out_tpda_dlct_3>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				tpda_dlct_5_in_funnel_wpss: endpoint {
+					remote-endpoint=
+					<&funnel_wpss_out_tpda_dlct_5>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				tpda_dlct_6_in_funnel_wpss: endpoint {
+					remote-endpoint=
+					<&funnel_wpss_out_tpda_dlct_6>;
+				};
+			};
+
+			port@f {
+				reg = <15>;
+				tpda_dlct_15_in_funnel_gfx_dl: endpoint {
+					remote-endpoint=
+					<&funnel_gfx_dl_out_tpda_dlct_15>;
+				};
+			};
+
+			port@11 {
+				reg = <17>;
+				tpda_dlct_17_in_funnel_turing: endpoint {
+					remote-endpoint=
+					<&funnel_turing_out_tpda_dlct_17>;
+				};
+			};
+
+			port@12 {
+				reg = <18>;
+				tpda_dlct_18_in_funnel_turing: endpoint {
+					remote-endpoint=
+					<&funnel_turing_out_tpda_dlct_18>;
+				};
+			};
+
+			port@17 {
+				reg = <23>;
+				tpda_dlct_23_in_tpdm_ufs: endpoint {
+					remote-endpoint=
+					<&tpdm_ufs_out_tpda_dlct_23>;
+				};
+			};
+
+			port@1a {
+				reg = <26>;
+				tpda_dlct_26_in_tpdm_dlct_dsb: endpoint {
+					remote-endpoint=
+					<&tpdm_dlct_dsb_out_tpda_dlct_26>;
+				};
+			};
+
+			port@1b {
+				reg = <27>;
+				tpda_dlct_27_in_tpdm_dlct_cmb: endpoint {
+					remote-endpoint=
+					<&tpdm_dlct_cmb_out_tpda_dlct_27>;
+				};
+			};
+
+
+
+		};
+
+		out-ports {
+			port {
+				tpda_dlct_out_funnel_dlct: endpoint {
+					remote-endpoint =
+					<&funnel_dlct_in_tpda_dlct>;
+				};
+			};
+		};
+	};
+
+	funnel_dlct: funnel@10824000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10824000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dlct";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dlct_in_tpda_dlct: endpoint {
+					remote-endpoint =
+					<&tpda_dlct_out_funnel_dlct>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_dlct_6_in_funnel_gfx_dl: endpoint {
+					remote-endpoint =
+					<&funnel_gfx_dl_out_funnel_dlct_6>;
+				};
+			};
+
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dlct_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_funnel_dlct>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_dlct_out_tn_ag_49: endpoint {
+					remote-endpoint =
+					<&tn_ag_49_in_funnel_dlct>;
+					source = <&funnel_mdss>;
+				};
+			};
+
+		};
+	};
+
+	tpdm_mm_dsb: tpdm@109a4000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109a4000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-mm-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_mm_dsb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_mm_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_west_dsb: tpdm@109ae000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109ae000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-west-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_west_dsb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_west_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_south_dsb: tpdm@109a5000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109a5000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-south-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+		out-ports {
+			port {
+				tpdm_south_dsb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_south_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_ipcc_cmb: tpdm@109ab000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109ab000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-ipcc-cmb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_ipcc_cmb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_ipcc_cmb>;
+				};
+			};
+		};
+	};
+
+	tpdm_center_dsb: tpdm@109aa000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109aa000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-center-dsb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_center_dsb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_center_dsb>;
+				};
+			};
+		};
+	};
+
+	tpdm_rdpm_cx: tpdm@109a7000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109a7000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-rdpm-cx";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_rdpm_cx_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_rdpm_cx>;
+				};
+			};
+		};
+	};
+
+	tpdm_rdpm_mxc: tpdm@109a9000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109a9000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-rdpm-mxc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_rdpm_mxc_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_rdpm_mxc>;
+				};
+			};
+		};
+	};
+
+	tpdm_rdpm_mxa: tpdm@109a8000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109a8000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-rdpm-mxa";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_rdpm_mxa_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_rdpm_mxa>;
+				};
+			};
+		};
+	};
+
+	tpdm_center_cmb: tpdm@109ac000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109ac000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-center-cmb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_center_cmb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_center_cmb>;
+				};
+			};
+		};
+	};
+
+	tpdm_south_cmb: tpdm@109af000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x109af000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-south-cmb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_south_cmb_out_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_in_tpdm_south_cmb>;
+				};
+			};
+		};
+	};
+
+	tn_ag: tn@109a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000f0c00>;
+		reg = <0x109a0000  0x3080>;
+		reg-names = "traceNoc-base";
+
+		coresight-name = "coresight-tracenoc-ag";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,trace-noc-v2;
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@8 {
+				reg = <8>;
+				tn_ag_in_tpda_pcie: endpoint {
+					remote-endpoint =
+					<&tpda_pcie_out_tn_ag>;
+				};
+			};
+
+			port@b {
+				reg = <11>;
+				tn_ag_in_tn_titan: endpoint {
+					remote-endpoint =
+					<&tn_titan_out_tn_ag>;
+				};
+			};
+
+			port@c {
+				reg = <12>;
+				tn_ag_in_funnel_tmess: endpoint {
+					remote-endpoint =
+					<&funnel_tmess_out_tn_ag>;
+				};
+			};
+
+			port@d {
+				reg = <13>;
+				tn_ag_in_funnel_modem_dl: endpoint {
+					remote-endpoint =
+					<&funnel_modem_dl_out_tn_ag>;
+				};
+			};
+
+			port@11 {
+				reg = <17>;
+				tn_ag_in_tpdm_gcc: endpoint {
+					remote-endpoint =
+					<&tpdm_gcc_out_tn_ag>;
+				};
+			};
+
+			port@12 {
+				reg = <18>;
+				tn_ag_in_tpdm_prng: endpoint {
+					remote-endpoint =
+					<&tpdm_prng_out_tn_ag>;
+				};
+			};
+
+			port@13 {
+				reg = <19>;
+				tn_ag_in_tpdm_qm: endpoint {
+					remote-endpoint =
+					<&tpdm_qm_out_tn_ag>;
+				};
+			};
+
+			port@14 {
+				reg = <20>;
+				tn_ag_in_tpdm_vsense: endpoint {
+					remote-endpoint =
+					<&tpdm_vsense_out_tn_ag>;
+				};
+			};
+
+			port@15 {
+				reg = <21>;
+				tn_ag_in_tpdm_ipa: endpoint {
+					remote-endpoint =
+					<&tpdm_ipa_out_tn_ag>;
+				};
+			};
+
+			port@16 {
+				reg = <22>;
+				tn_ag_in_tpdm_sdcc5_2: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc5_2_out_tn_ag>;
+				};
+			};
+
+			port@17 {
+				reg = <23>;
+				tn_ag_in_tpdm_sdcc5_1: endpoint {
+					remote-endpoint =
+					<&tpdm_sdcc5_1_out_tn_ag>;
+				};
+			};
+
+			port@19 {
+				reg = <25>;
+				tn_ag_in_tpdm_mm_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_mm_dsb_out_tn_ag>;
+				};
+			};
+
+			port@1a {
+				reg = <26>;
+				tn_ag_in_tpdm_west_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_west_dsb_out_tn_ag>;
+				};
+			};
+
+			port@1b {
+				reg = <27>;
+				tn_ag_in_tpdm_south_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_south_dsb_out_tn_ag>;
+				};
+			};
+
+			port@1c {
+				reg = <28>;
+				tn_ag_in_tpdm_ipcc_cmb: endpoint {
+					remote-endpoint =
+					<&tpdm_ipcc_cmb_out_tn_ag>;
+				};
+			};
+
+			port@1d {
+				reg = <29>;
+				tn_ag_in_tpdm_center_dsb: endpoint {
+					remote-endpoint =
+					<&tpdm_center_dsb_out_tn_ag>;
+				};
+			};
+
+			port@1e {
+				reg = <30>;
+				tn_ag_in_tpdm_rdpm_cx: endpoint {
+					remote-endpoint =
+					<&tpdm_rdpm_cx_out_tn_ag>;
+				};
+			};
+
+			port@1f {
+				reg = <31>;
+				tn_ag_in_tpdm_rdpm_mxc: endpoint {
+					remote-endpoint =
+					<&tpdm_rdpm_mxc_out_tn_ag>;
+				};
+			};
+
+			port@20 {
+				reg = <32>;
+				tn_ag_in_tpdm_rdpm_mxa: endpoint {
+					remote-endpoint =
+					<&tpdm_rdpm_mxa_out_tn_ag>;
+				};
+			};
+
+			port@21 {
+				reg = <33>;
+				tn_ag_in_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_out_tn_ag>;
+				};
+			};
+
+			port@22 {
+				reg = <34>;
+				tn_ag_in_tpdm_center_cmb: endpoint {
+					remote-endpoint =
+					<&tpdm_center_cmb_out_tn_ag>;
+				};
+			};
+
+			port@25 {
+				reg = <37>;
+				tn_ag_in_tpdm_south_cmb: endpoint {
+					remote-endpoint =
+					<&tpdm_south_cmb_out_tn_ag>;
+				};
+			};
+
+			port@2c {
+				reg = <44>;
+				tn_ag_in_funnel_dlct: endpoint {
+					remote-endpoint =
+					<&funnel_dlct_out_tn_ag>;
+				};
+			};
+
+			port@31 {
+				reg = <49>;
+				tn_ag_49_in_funnel_dlct: endpoint {
+					remote-endpoint =
+					<&funnel_dlct_out_tn_ag_49>;
+				};
+			};
+
+			port@4a {
+				reg = <74>;
+				tn_ag_in_tn_ddr: endpoint {
+					remote-endpoint =
+					<&tn_ddr_out_tn_ag>;
+				};
+			};
+
+			port@5f {
+				reg = <95>;
+				tn_ag_in_tn_lpass: endpoint {
+					remote-endpoint =
+					<&tn_lpass_out_tn_ag>;
+				};
+			};
+
+			port@61 {
+				reg = <97>;
+				tn_ag_in_tn_soccp: endpoint {
+					remote-endpoint =
+					<&tn_soccp_out_tn_ag>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tn_ag_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_tn_ag>;
+				};
+			};
+		};
+	};
+
+	stm: stm@10002000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb962>;
+		reg = <0x10002000 0x1000>,
+			<0x37280000 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		coresight-name = "coresight-stm";
+		atid = <16>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	funnel_in0: funnel@10041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_in0_in_tn_ag: endpoint {
+					remote-endpoint =
+					<&tn_ag_out_funnel_in0>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in0_in_tpda_qdss: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_out_funnel_in0>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					remote-endpoint =
+					<&stm_out_funnel_in0>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_in0_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_in0>;
+				};
+			};
+		};
+	};
+
+	tpdm_dcc: tpdm@10003000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10003000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dcc";
+
+		qcom,hw-enable-check;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_dcc_out_tpda_qdss: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_in_tpdm_dcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_spdm: tpdm@1000f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x1000f000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-spdm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_spdm_out_tpda_qdss: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_in_tpdm_spdm>;
+				};
+			};
+		};
+	};
+
+	tpda_qdss: tpda@10004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10004000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-qdss";
+
+		qcom,cmb-elem-size = <0 32>,
+				<1 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_qdss_in_tpdm_dcc: endpoint {
+					remote-endpoint =
+					<&tpdm_dcc_out_tpda_qdss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_qdss_in_tpdm_spdm: endpoint {
+					remote-endpoint =
+					<&tpdm_spdm_out_tpda_qdss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				tpda_qdss_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_tpda_qdss>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio0: tpdm@10b09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b09000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-prio-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_swao_prio0_out_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_in_tpdm_swao_prio0>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio1: tpdm@10b0a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0a000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-prio-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_swao_prio1_out_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_in_tpdm_swao_prio1>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio2: tpdm@10b0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0b000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-prio-2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_swao_prio2_out_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_in_tpdm_swao_prio2>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao_prio3: tpdm@10b0c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-prio-3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_swao_prio3_out_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_in_tpdm_swao_prio3>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao: tpdm@10b0d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x10b0d000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		out-ports {
+			port {
+				tpdm_swao_out_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_in_tpdm_swao>;
+				};
+			};
+		};
+	};
+
+	tpda_aoss: tpda@10b08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x10b08000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-aoss";
+
+		qcom,cmb-elem-size = <0 64>,
+				     <1 64>,
+				     <2 64>,
+				     <3 64>;
+
+		qcom,dsb-elem-size = <4 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		status = "disabled";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_aoss_in_tpdm_swao_prio0: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio0_out_tpda_aoss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_aoss_in_tpdm_swao_prio1: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio1_out_tpda_aoss>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_aoss_in_tpdm_swao_prio2: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio2_out_tpda_aoss>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				tpda_aoss_in_tpdm_swao_prio3: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_prio3_out_tpda_aoss>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpda_aoss_in_tpdm_swao: endpoint {
+					remote-endpoint =
+					<&tpdm_swao_out_tpda_aoss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				tpda_aoss_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_tpda_aoss>;
+				};
+			};
+		};
+	};
+
+	funnel_aoss: funnel@10b04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x10b04000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-aoss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@3 {
+				reg = <3>;
+				funnel_aoss_in_tpdm_ddr_lpicc: endpoint {
+					remote-endpoint =
+					<&tpdm_ddr_lpicc_out_funnel_aoss>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_aoss_in_funnel_lpass_lpi: endpoint {
+					remote-endpoint =
+					<&funnel_lpass_lpi_out_funnel_aoss>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_aoss_in_tpda_aoss: endpoint {
+					remote-endpoint =
+					<&tpda_aoss_out_funnel_aoss>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_aoss_in_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_out_funnel_aoss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_aoss_out_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_in_funnel_aoss>;
+				};
+			};
+		};
+	};
+
+	tmc_etf: tmc@10b05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x10b05000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etf_in_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_out_tmc_etf>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tmc_etf_out_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_in_tmc_etf>;
+				};
+			};
+		};
+	};
+
+	replicator_swao: replicator@10b06000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x10b06000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_swao";
+
+		qcom,replicator-loses-context;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_swao_in_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_out_replicator_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				replicator_swao_out_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_in_replicator_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_swao_out_eud: endpoint {
+					remote-endpoint =
+					  <&eud_in_replicator_swao>;
+				};
+			};
+		};
+	};
+
+	dummy_eud: dummy-eud {
+		compatible = "arm,coresight-dummy-sink";
+
+		coresight-name = "coresight-eud";
+
+		in-ports {
+			port {
+				eud_in_replicator_swao: endpoint {
+					remote-endpoint =
+						<&replicator_swao_out_eud>;
+				};
+			};
+		};
+	};
+
+	replicator_qdss: replicator@10046000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x10046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_qdss_in_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_out_replicator_qdss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				replicator_qdss_out_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_in_replicator_qdss>;
+				};
+			};
+		};
+	};
+
+	replicator_etr: replicator@1004e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x1004e000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-etr";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_etr_in_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_out_replicator_etr>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_etr_out_tmc_etr: endpoint {
+					remote-endpoint =
+					<&tmc_etr_in_replicator_etr>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_etr_out_replicator_dummy: endpoint {
+					remote-endpoint =
+					<&replicator_dummy_in_replicator_etr>;
+				};
+			};
+		};
+	};
+
+	etr1-replicator {
+		compatible = "arm,coresight-static-replicator";
+
+		coresight-name = "coresight-replicator-etr1";
+
+		in-ports {
+			port {
+				replicator_dummy_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_replicator_dummy>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_dummy_out_tmc_modem: endpoint {
+					remote-endpoint =
+					<&tmc_modem_in_replicator_dummy>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_dummy_out_tmc_etr1: endpoint {
+					remote-endpoint =
+					<&tmc_etr1_in_replicator_dummy>;
+				};
+			};
+		};
+	};
+
+	tmc_etr: tmc@10048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x10048000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etr";
+
+		qcom,iommu-dma = "bypass";
+		iommus = <&apps_smmu 0x04e0 0x0>;
+		dma-coherent;
+		arm,scatter-gather;
+
+		//usb_bamless_support;
+		qcom,sw-usb;
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0xf8>;
+		csr-irqctrl-offset = <0x6c>;
+		byte-cntr-name = "byte-cntr";
+		byte-cntr-class-name = "coresight-tmc-etr-stream";
+		interrupts = <GIC_SPI 738 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etr_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	tmc_etr1: tmc@1004f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x1004f000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etr1";
+
+		iommus = <&apps_smmu 0x0500 0x0>;
+		dma-coherent;
+		arm,scatter-gather;
+
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0x108>;
+		csr-irqctrl-offset = <0x70>;
+		byte-cntr-name = "byte-cntr1";
+		byte-cntr-class-name = "coresight-tmc-etr1-stream";
+		interrupts = <GIC_SPI 737 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etr1_in_replicator_dummy: endpoint {
+					remote-endpoint =
+					<&replicator_dummy_out_tmc_etr1>;
+				};
+			};
+		};
+	};
+};
diff --git a/qcom/kera-reserved-memory.dtsi b/qcom/kera-reserved-memory.dtsi
index b990fbcb..427aea63 100644
--- a/qcom/kera-reserved-memory.dtsi
+++ b/qcom/kera-reserved-memory.dtsi
@@ -228,6 +228,20 @@
 	 * varies.
 	 */
 
+	trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
+		compatible = "shared-dma-pool";
+		reg = <0x0 0xf3800000 0x0 0x4400000>;
+		reusable;
+		alignment = <0x0 0x400000>;
+	};
+
+	oem_vm_mem: oem_vm_region@f7c00000 {
+		compatible = "shared-dma-pool";
+		reg = <0x0 0xf7c00000 0x0 0x4c00000>;
+		reusable;
+		alignment = <0x0 0x400000>;
+	};
+
 	llcc_lpi_mem: llcc_lpi_region@ff800000 {
 		no-map;
 		reg = <0x0 0xff800000 0x0 0x400000>;
diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index 6113449d..53f08502 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Kera";
@@ -36,6 +37,8 @@
 
 	reserved_memory: reserved-memory {};
 
+	ddr-regions { };
+
 	firmware: firmware {
 		qcom_scm: qcom_scm { };
 	};
@@ -237,6 +240,25 @@
 		size = <0x0 0x2000000>;
 		linux,cma-default;
 	};
+
+	kinfo_mem: debug_kinfo_region {
+		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
+		size = <0x0 0x1000>;
+		no-map;
+	};
+
+	va_md_mem: va_md_mem_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		size = <0 0x1000000>;
+	};
+
+	ramoops_mem: ramoops-region {
+		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
+		size = <0x0 0x200000>;
+		no-map;
+	};
 };
 
 &soc {
@@ -324,6 +346,11 @@
 		};
 	};
 
+	qcom,secure-buffer {
+		compatible = "qcom,secure-buffer";
+		qcom,vmid-cp-camera-preview-ro;
+	};
+
 	apps_rsc: rsc@17a00000 {
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
@@ -399,6 +426,129 @@
 		interrupt-controller;
 	};
 
+	adsp_pas: remoteproc-adsp@03000000 {
+		compatible = "qcom,kera-adsp-pas";
+		reg = <0x03000000 0x10000>;
+		status = "ok";
+
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+
+		reg-names = "cx", "mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnect-names = "rproc_ddr", "crypto_ddr";
+
+		firmware-name = "adsp.mdt", "adsp_dtb.mdt";
+		memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;
+
+		/* Inputs from ssc */
+		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+					<&adsp_smp2p_in 0 0>,
+					<&adsp_smp2p_in 2 0>,
+					<&adsp_smp2p_in 1 0>,
+					<&adsp_smp2p_in 3 0>,
+					<&adsp_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+	};
+
+	cdsp_pas: remoteproc-cdsp@32300000 {
+		compatible = "qcom,kera-cdsp-pas";
+		reg = <0x32300000 0x10000>;
+		status = "ok";
+
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+		reg-names = "cx","mx","nsp";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnect-names = "rproc_ddr", "crypto_ddr";
+
+		firmware-name = "cdsp.mdt", "cdsp_dtb.mdt";
+
+		memory-region = <&cdsp_mem &q6_cdsp_dtb_mem &global_sync_mem>;
+
+		/* Inputs from turing */
+		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+					<&cdsp_smp2p_in 0 0>,
+					<&cdsp_smp2p_in 2 0>,
+					<&cdsp_smp2p_in 1 0>,
+					<&cdsp_smp2p_in 3 0>,
+					<&cdsp_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+	};
+
+	modem_pas: remoteproc-mss@04080000 {
+		compatible = "qcom,kera-modem-pas";
+		reg = <0x4080000 0x10000>;
+		status = "ok";
+
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
+
+		reg-names = "cx", "mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		interconnect-names = "rproc_ddr", "crypto_ddr";
+
+		firmware-name = "modem.mdt", "modem_dtb.mdt";
+
+		memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma &dsm_partition_1_mem &dsm_partition_2_mem>;
+
+		/* Inputs from mss */
+		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+					<&modem_smp2p_in 0 0>,
+					<&modem_smp2p_in 2 0>,
+					<&modem_smp2p_in 1 0>,
+					<&modem_smp2p_in 3 0>,
+					<&modem_smp2p_in 7 0>;
+
+		interrupt-names = "wdog",
+				"fatal",
+				"handover",
+				"ready",
+				"stop-ack",
+				"shutdown-ack";
+
+		/* Outputs to mss */
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,kera-tlmm";
 		reg = <0xf000000 0x1000000>;
@@ -630,6 +780,11 @@
 		};
 	};
 
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	qcom,smp2p_sleepstate {
 		compatible = "qcom,smp2p-sleepstate";
 		qcom,smem-states = <&sleepstate_smp2p_out 0>;
@@ -638,6 +793,64 @@
 		interrupt-names = "smp2p-sleepstate-in";
 	};
 
+	qcom,msm-imem@14680000 {
+		compatible = "qcom,msm-imem";
+		reg = <0x14680000 0x1000>;
+		ranges = <0x0 0x14680000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,pil-reloc-info";
+			reg = <0x94c 0xc8>;
+		};
+
+		pil@6dc {
+			compatible = "qcom,msm-imem-pil-disable-timeout";
+			reg = <0x6dc 0x4>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+
+		modem_dsm@c98 {
+			compatible = "qcom,msm-imem-mss-dsm";
+			reg = <0xc98 0x10>;
+		};
+
+		sys_dbg@af8 {
+			compatible = "qcom,msm-imem-gpu-dump-skip";
+			reg = <0xb0c 0x4>;
+		};
+	};
+
 	eud: qcom,msm-eud@88e0000 {
 		compatible = "qcom,msm-eud";
 		interrupt-names = "eud_irq";
@@ -651,12 +864,50 @@
 		status = "ok";
 	};
 
+	google,debug-kinfo {
+		compatible = "google,debug-kinfo";
+		memory-region = <&kinfo_mem>;
+	};
+
+	mini_dump_node {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
+	va_mini_dump {
+		compatible = "qcom,va-minidump";
+		memory-region = <&va_md_mem>;
+		status = "ok";
+	};
+
+	qcom_ramoops {
+		compatible = "qcom,ramoops";
+		memory-region = <&ramoops_mem>;
+		pmsg-size = <0x200000>;
+		mem-type = <2>;
+	};
+
+	qcom,mpm2-sleep-counter@c221000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0xc221000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
 	qcom,msm-adsprpc-mem {
 		compatible = "qcom,msm-adsprpc-mem-region";
 		memory-region = <&adsp_mem_heap>;
 		restrict-access;
 	};
 
+	qfprom: qfprom@221c8000 {
+		compatible = "qcom,kera-qfprom", "qcom,qfprom";
+		reg = <0x221c8000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+	};
+
 	clocks {
 		xo_board: xo_board {
 			compatible = "fixed-clock";
@@ -770,9 +1021,18 @@
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
+
+	gh-secure-vm-loader@2 {
+		compatible = "qcom,gh-secure-vm-loader";
+		qcom,pas-id = <35>;
+		qcom,vmid = <50>;
+		qcom,firmware-name = "cpusys_vm";
+		memory-region = <&cpusys_vm_mem>;
+	};
 };
 
 #include "tuna-gdsc.dtsi"
+#include "ipcc-test-no-slpi.dtsi"
 
 &cam_cc_ipe_0_gdsc {
 	compatible = "regulator-fixed";
@@ -906,7 +1166,9 @@
 		size = <0x0 0x4800000>;
 	};
 };
+
 #include "kera-debug.dtsi"
+#include "kera-coresight.dtsi"
 #include "kera-pinctrl.dtsi"
 #include "kera-stub-regulators.dtsi"
 #include "kera-usb.dtsi"
diff --git a/qcom/parrot-atp.dtsi b/qcom/parrot-atp.dtsi
index 21e0081a..d146ea7a 100644
--- a/qcom/parrot-atp.dtsi
+++ b/qcom/parrot-atp.dtsi
@@ -53,6 +53,9 @@
 	vccq2-supply = <&L19B>;
 	vccq2-max-microamp = <750000>;
 
+	qcom,vccq2-parent-supply = <&S8E>;
+	qcom,vccq2-parent-max-microamp = <210000>;
+
 	qcom,vddp-ref-clk-supply = <&L13B>;
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
diff --git a/qcom/parrot-idp.dtsi b/qcom/parrot-idp.dtsi
index 55a1821d..6902a3d1 100644
--- a/qcom/parrot-idp.dtsi
+++ b/qcom/parrot-idp.dtsi
@@ -144,6 +144,9 @@
 	vccq2-supply = <&L19B>;
 	vccq2-max-microamp = <750000>;
 
+	qcom,vccq2-parent-supply = <&S8E>;
+	qcom,vccq2-parent-max-microamp = <210000>;
+
 	qcom,vddp-ref-clk-supply = <&L13B>;
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
diff --git a/qcom/parrot-qrd.dtsi b/qcom/parrot-qrd.dtsi
index 16fe6774..aa7b33d2 100644
--- a/qcom/parrot-qrd.dtsi
+++ b/qcom/parrot-qrd.dtsi
@@ -94,6 +94,9 @@
 	vccq2-supply = <&L19B>;
 	vccq2-max-microamp = <750000>;
 
+	qcom,vccq2-parent-supply = <&S8E>;
+	qcom,vccq2-parent-max-microamp = <210000>;
+
 	qcom,vddp-ref-clk-supply = <&L13B>;
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
diff --git a/qcom/parrot-regulators.dtsi b/qcom/parrot-regulators.dtsi
index 6772774d..449851f6 100644
--- a/qcom/parrot-regulators.dtsi
+++ b/qcom/parrot-regulators.dtsi
@@ -685,6 +685,11 @@
 	rpmh-regulator-smpe8 {
 		compatible = "qcom,rpmh-vrm-regulator";
 		qcom,resource-name = "smpe8";
+		qcom,regulator-type = "pmic5-hfsmps";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_RET
+			RPMH_REGULATOR_MODE_AUTO>;
+		qcom,mode-threshold-currents = <0 200000>;
 		S8E:
 		pm6150l_s8: regulator-pm6150l-s8 {
 			regulator-name = "pm6150l_s8";
@@ -692,6 +697,7 @@
 			regulator-min-microvolt = <1816000>;
 			regulator-max-microvolt = <2040000>;
 			qcom,init-voltage = <1872000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_RET>;
 		};
 	};
 
diff --git a/qcom/pm7550ba.dtsi b/qcom/pm7550ba.dtsi
index bd9d9220..953da75d 100644
--- a/qcom/pm7550ba.dtsi
+++ b/qcom/pm7550ba.dtsi
@@ -74,7 +74,7 @@
 			#size-cells = <0>;
 			status = "disabled";
 
-			oledb_vreg: oledb@fa00 {
+			pm7550ba_oledb_vreg: oledb@fa00 {
 				reg = <0xfa00>;
 				reg-names = "oledb_base";
 				regulator-name = "oledb";
@@ -83,7 +83,7 @@
 				qcom,swire-control;
 			};
 
-			ab_vreg: ab@f900 {
+			pm7550ba_ab_vreg: ab@f900 {
 				reg = <0xf900>;
 				reg-names = "ab_base";
 				regulator-name = "ab";
@@ -92,7 +92,7 @@
 				qcom,swire-control;
 			};
 
-			ibb_vreg: ibb@f800 {
+			pm7550ba_ibb_vreg: ibb@f800 {
 				reg = <0xf800>;
 				reg-names = "ibb_base";
 				regulator-name = "ibb";
diff --git a/qcom/pmih010x.dtsi b/qcom/pmih010x.dtsi
index 6f31c3c3..42ae38ea 100644
--- a/qcom/pmih010x.dtsi
+++ b/qcom/pmih010x.dtsi
@@ -250,6 +250,20 @@
 			#thermal-sensor-cells = <1>;
 		};
 
+		pmih010x_bcl2: bcl@4900 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x4900 0x100>;
+			interrupts = <0x7 0x49 0x0 IRQ_TYPE_NONE>,
+				     <0x7 0x49 0x1 IRQ_TYPE_NONE>,
+				     <0x7 0x49 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+					  "bcl-lvl1",
+					  "bcl-lvl2";
+			qcom,pmic7-threshold;
+			#thermal-sensor-cells = <1>;
+			status = "disabled";
+		};
+
 		bcl_soc: bcl-soc {
 			compatible = "qcom,msm-bcl-soc";
 			#thermal-sensor-cells = <0>;
diff --git a/qcom/pmiv010x.dtsi b/qcom/pmiv010x.dtsi
new file mode 100644
index 00000000..d53c0606
--- /dev/null
+++ b/qcom/pmiv010x.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	pmiv010x_7: qcom,pmiv0108@7 {
+		compatible = "qcom,spmi-pmic";
+		reg = <7 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pmiv010x_tz: qcom,temp-alarm@a00 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0xa00>;
+			interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			#thermal-sensor-cells = <0>;
+		};
+
+		pmiv010x_gpios: pinctrl@8800 {
+			compatible = "qcom,pmiv0108-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pmiv010x_eusb2_repeater: eusb2-repeater@fd00 {
+			compatible = "qcom,pmic-eusb2-repeater";
+			reg = <0xfd00>;
+		};
+
+		pmiv010x_vib: qcom,vibrator@df00 {
+			compatible = "qcom,qpnp-vibrator-ldo";
+			reg = <0xdf00>;
+			qcom,vib-ldo-volt-uv = <3000000>;
+			qcom,disable-overdrive;
+		};
+
+		pmiv010x_amoled: qcom,amoled {
+			compatible = "qcom,amoled-regulator";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			oledb_vreg: oledb@fa00 {
+				reg = <0xfa00>;
+				reg-names = "oledb_base";
+				regulator-name = "oledb";
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <8000000>;
+				qcom,swire-control;
+			};
+
+			ab_vreg: ab@f900 {
+				reg = <0xf900>;
+				reg-names = "ab_base";
+				regulator-name = "ab";
+				regulator-min-microvolt = <4600000>;
+				regulator-max-microvolt = <5200000>;
+				qcom,swire-control;
+			};
+
+			ibb_vreg: ibb@f800 {
+				reg = <0xf800>;
+				reg-names = "ibb_base";
+				regulator-name = "ibb";
+				regulator-min-microvolt = <1400000>;
+				regulator-max-microvolt = <6600000>;
+				qcom,swire-control;
+				regulator-allow-set-load;
+			};
+		};
+
+		pmiv010x_amoled_ecm: qcom,amoled-ecm@f900 {
+			compatible = "qcom,amoled-ecm";
+			reg = <0xf900>;
+			status = "disabled";
+
+			nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1",
+				      "amoled-ecm-sdam2";
+			nvmem = <&pmk8550_sdam_13>, <&pmk8550_sdam_14>,
+				<&pmk8550_sdam_41>;
+			interrupt-names = "ecm-sdam0", "ecm-sdam1",
+					  "ecm-sdam2";
+			interrupts = <0x7 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x7 0x7d 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x7 0x98 0x1 IRQ_TYPE_EDGE_RISING>;
+		};
+	};
+};
+
+&thermal_zones {
+	pmiv010x_temp_alarm: pmiv010x_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pmiv010x_tz>;
+		trips {
+			pmiv010x_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmiv010x_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pmiv010x_trip2: trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "critical";
+			};
+		};
+	};
+};
diff --git a/qcom/pmxr2230.dtsi b/qcom/pmxr2230.dtsi
index 5dcf1017..6a3e5b4c 100644
--- a/qcom/pmxr2230.dtsi
+++ b/qcom/pmxr2230.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/spmi/spmi.h>
 
 &spmi_bus {
@@ -34,86 +35,30 @@
 			#interrupt-cells = <2>;
 		};
 
-		pmxr2230_pwm_1: pwms@e800 {
-			compatible = "qcom,pwm-lpg";
-			reg = <0xe800>;
-			reg-names = "lpg-base";
+		led-controller {
+			compatible = "qcom,pm8350c-pwm";
+			#address-cells = <1>;
+			#size-cells = <0>;
 			#pwm-cells = <2>;
-			qcom,num-lpg-channels = <3>;
 			nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>;
 			nvmem-names = "lpg_chan_sdam", "lut_sdam";
-			qcom,lut-sdam-base = <0x45>;
-			qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
-					     90 80 70 60 50 40 30 20 10 0>;
-			qcom,tick-duration-us = <7800>;
 
-			lpg@1 {
-				qcom,lpg-chan-id = <1>;
-				qcom,ramp-step-ms = <100>;
-				qcom,ramp-low-index = <0>;
-				qcom,ramp-high-index = <19>;
-				qcom,ramp-pattern-repeat;
-				qcom,lpg-sdam-base = <0x48>;
-			};
-
-			lpg@2 {
-				qcom,lpg-chan-id = <2>;
-				qcom,ramp-step-ms = <100>;
-				qcom,ramp-low-index = <0>;
-				qcom,ramp-high-index = <19>;
-				qcom,ramp-pattern-repeat;
-				qcom,lpg-sdam-base = <0x56>;
-			};
-
-			lpg@3 {
-				qcom,lpg-chan-id = <3>;
-				qcom,ramp-step-ms = <100>;
-				qcom,ramp-low-index = <0>;
-				qcom,ramp-high-index = <19>;
-				qcom,ramp-pattern-repeat;
-				qcom,lpg-sdam-base = <0x64>;
-			};
-		};
-
-		pmxr2230_pwm_2: pwms@e900 {
-			compatible = "qcom,pwm-lpg";
-			reg = <0xe900>;
-			reg-names = "lpg-base";
-			#pwm-cells = <2>;
-			qcom,num-lpg-channels = <1>;
-		};
-
-		pmxr2230_pwm_4: pwms@eb00 {
-			compatible = "qcom,pwm-lpg";
-			reg = <0xeb00>;
-			reg-names = "lpg-base";
-			#pwm-cells = <2>;
-			qcom,num-lpg-channels = <1>;
-		};
-
-		pmxr2230_rgb: qcom,leds@ef00 {
-			compatible = "qcom,tri-led";
-			reg = <0xef00>;
-
-			red {
+			led@1 {
+				reg = <1>;
+				color = <LED_COLOR_ID_RED>;
 				label = "red";
-				pwms = <&pmxr2230_pwm_1 0 1000000>;
-				led-sources = <0>;
-				linux,default-trigger = "timer";
 			};
 
-			green {
+			led@2 {
+				reg = <2>;
+				color = <LED_COLOR_ID_GREEN>;
 				label = "green";
-				pwms = <&pmxr2230_pwm_1 1 1000000>;
-				led-sources = <1>;
-				linux,default-trigger = "timer";
 			};
 
-			blue {
+			led@3 {
+				reg = <3>;
+				color = <LED_COLOR_ID_BLUE>;
 				label = "blue";
-				pwms = <&pmxr2230_pwm_1 2 1000000>;
-				led-sources = <2>;
-				linux,default-trigger = "timer";
 			};
 		};
 
diff --git a/qcom/sdxkova-idp-m2.dtsi b/qcom/sdxkova-idp-m2.dtsi
index 1510613d..a6556953 100644
--- a/qcom/sdxkova-idp-m2.dtsi
+++ b/qcom/sdxkova-idp-m2.dtsi
@@ -5,3 +5,7 @@
 
 &soc {
 };
+
+&qnand_1 {
+	status = "ok";
+};
diff --git a/qcom/sdxkova-idp-mbb.dtsi b/qcom/sdxkova-idp-mbb.dtsi
index 15e414cb..d2dd79f2 100644
--- a/qcom/sdxkova-idp-mbb.dtsi
+++ b/qcom/sdxkova-idp-mbb.dtsi
@@ -30,6 +30,10 @@
 	operating-points-v2 = <&sdhc2_opp_table>;
 };
 
+&qnand_1 {
+	status = "ok";
+};
+
 &pmk8550_vadc {
 	/* PM8550BA Channel nodes */
 	pm7550ba_offset_ref {
diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi
index 1a4d6c59..cafbcccd 100644
--- a/qcom/sdxkova.dtsi
+++ b/qcom/sdxkova.dtsi
@@ -1707,6 +1707,37 @@
 		qcom,smem-states = <&modem_smp2p_out 0>;
 		qcom,smem-state-names = "stop";
 	};
+
+	qnand_1: nand@1c98000 {
+		compatible = "qcom,msm-nand";
+		reg =   <0x0 0x01c98000 0x0 0x1000>,
+			<0x0 0x01c9C000 0x0 0x1c000>;
+		reg-names =     "nand_phys",
+				"bam_phys";
+		qcom,reg-adjustment-offset = <0x4000>;
+
+		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bam_irq";
+
+		clock-names = "core_clk";
+		clocks = <&rpmhcc RPMH_QPIC_CLK>;
+
+		interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "nand-ddr";
+		qcom,msm-bus,name = "qpic_nand";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<0 0>,
+		/* Voting for max b/w on PNOC bus for now */
+			<1057800 725760>;
+
+		iommus = <&apps_smmu 0x100 0x3>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		status = "disabled";
+	};
 };
 
 &gcc {
diff --git a/qcom/sun-qrd-sku1.dtsi b/qcom/sun-qrd-sku1.dtsi
index 5123f1a8..c80165b4 100644
--- a/qcom/sun-qrd-sku1.dtsi
+++ b/qcom/sun-qrd-sku1.dtsi
@@ -96,3 +96,152 @@
 &ibat_lvl1 {
 	temperature = <7000>;
 };
+
+&pmih010x_bcl {
+	qcom,bcl-mon-vbat-only;
+	status = "okay";
+};
+
+&pmih010x_bcl2 {
+	qcom,bcl-mon-ibat-only;
+	status = "okay";
+};
+
+&thermal_zones {
+	pmih010x-ibat2-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmih010x_bcl2 0>;
+
+		trips {
+			ibat2_lvl0:ibat2-lvl0 {
+				temperature = <6500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pmih010x-ibat2-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmih010x_bcl2 1>;
+
+		trips {
+			ibat2_lvl1:ibat2-lvl1 {
+				temperature = <7000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pmih010x-bcl2-lvl0 {
+		polling-delay-passive = <50>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmih010x_bcl2 5>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl2_lvl0: b-bcl2-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lbat2_modem0 {
+				trip = <&b_bcl2_lvl0>;
+				cooling-device = <&modem_bcl 1 1>;
+			};
+
+			lbat2_gpu0 {
+				trip = <&b_bcl2_lvl0>;
+				cooling-device = <&msm_gpu 1 1>;
+			};
+		};
+	};
+
+	pmih010x-bcl2-lvl1 {
+		polling-delay-passive = <50>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmih010x_bcl2 6>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl2_lvl1: b-bcl2-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lbat2_modem1 {
+				trip = <&b_bcl2_lvl1>;
+				cooling-device = <&modem_bcl 2 2>;
+			};
+
+			lbat2_gpu1 {
+				trip = <&b_bcl2_lvl1>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+		};
+	};
+
+	pmih010x-bcl2-lvl2 {
+		polling-delay-passive = <50>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmih010x_bcl2 7>;
+
+		trips {
+			thermal-engine-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			thermal-hal-trip {
+				temperature = <100>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			b_bcl2_lvl2: b-bcl2-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lbat2_gpu2 {
+				trip = <&b_bcl2_lvl2>;
+				cooling-device = <&msm_gpu 3 3>;
+			};
+		};
+	};
+};
diff --git a/qcom/tuna-atp-overlay.dts b/qcom/tuna-atp-overlay.dts
index f11e1579..6c4d6b9a 100644
--- a/qcom/tuna-atp-overlay.dts
+++ b/qcom/tuna-atp-overlay.dts
@@ -7,6 +7,8 @@
 /plugin/;
 
 #include "tuna-atp.dtsi"
+#include "tuna-pmih010x.dtsi"
+#include "pmd802x.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna ATP";
diff --git a/qcom/tuna-cdp-overlay.dts b/qcom/tuna-cdp-overlay.dts
index 82f00661..04abc04c 100644
--- a/qcom/tuna-cdp-overlay.dts
+++ b/qcom/tuna-cdp-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-cdp.dtsi"
+#include "tuna-pmiv0108.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna CDP";
diff --git a/qcom/tuna-cdp.dtsi b/qcom/tuna-cdp.dtsi
index 44461ef5..6b85652a 100644
--- a/qcom/tuna-cdp.dtsi
+++ b/qcom/tuna-cdp.dtsi
@@ -3,6 +3,9 @@
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+
 &qupv3_se4_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -83,3 +86,27 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+
diff --git a/qcom/tuna-mtp-kiwi-overlay.dts b/qcom/tuna-mtp-kiwi-overlay.dts
index 9f8e2b72..bb6fefd8 100644
--- a/qcom/tuna-mtp-kiwi-overlay.dts
+++ b/qcom/tuna-mtp-kiwi-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-mtp-kiwi.dtsi"
+#include "tuna-pm7550ba.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN";
diff --git a/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts b/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts
new file mode 100644
index 00000000..a08d35a8
--- /dev/null
+++ b/qcom/tuna-mtp-kiwi-pmd802x-overlay.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "tuna-mtp-kiwi.dtsi"
+#include "tuna-pm7550ba-pmd802x.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + pmd802x";
+	compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap",
+			"qcom,mtp";
+	qcom,msm-id = <681 0x10000>, <655 0x10000>;
+	qcom,board-id = <8 2>;
+};
diff --git a/qcom/tuna-mtp-overlay.dts b/qcom/tuna-mtp-overlay.dts
index a9ea196b..006e66f8 100644
--- a/qcom/tuna-mtp-overlay.dts
+++ b/qcom/tuna-mtp-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-mtp.dtsi"
+#include "tuna-pm7550ba-pmd802x.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna MTP";
diff --git a/qcom/tuna-mtp-qmp1000-overlay.dts b/qcom/tuna-mtp-qmp1000-overlay.dts
index f366cb86..85d26b68 100644
--- a/qcom/tuna-mtp-qmp1000-overlay.dts
+++ b/qcom/tuna-mtp-qmp1000-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-mtp-qmp1000.dtsi"
+#include "tuna-pm7550ba-pmd802x.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna MTP QMP1000";
diff --git a/qcom/tuna-mtp.dtsi b/qcom/tuna-mtp.dtsi
index 12fe6b41..6b85652a 100644
--- a/qcom/tuna-mtp.dtsi
+++ b/qcom/tuna-mtp.dtsi
@@ -2,6 +2,10 @@
 /*
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
+
 &qupv3_se4_i2c {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -82,3 +86,27 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+
diff --git a/qcom/tuna-pcie.dtsi b/qcom/tuna-pcie.dtsi
new file mode 100644
index 00000000..b0972852
--- /dev/null
+++ b/qcom/tuna-pcie.dtsi
@@ -0,0 +1,301 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-tuna.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&soc {
+	pcie0: pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+		device_type = "pci";
+
+		reg = <0x1c00000 0x3000>,
+			<0x1c06000 0x2000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>,
+			<0x1c03000 0x1000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf", "mhi";
+
+		cell-index = <0>;
+		linux,pci-domain = <0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3d00000>;
+
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+
+		msi-map = <0x0 &gic_its 0x1400 0x1>,
+			<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */
+
+		perst-gpio = <&tlmm 33 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie0_perst_default
+				&pcie0_clkreq_default
+				&pcie0_wake_default>;
+		pinctrl-1 = <&pcie0_perst_default
+				&pcie0_clkreq_sleep
+				&pcie0_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
+		gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
+
+		vreg-1p2-supply = <&L4B>;
+		vreg-0p9-supply = <&L2B>;
+		vreg-qref-supply = <&L2B>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		vreg-mx-supply = <&VDD_MXA_LEVEL>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 15010>;
+		qcom,vreg-0p9-voltage-level = <912000 880000 92070>;
+		qcom,vreg-qref-voltage-level = <880000 880000 46800>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+			<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
+			<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
+			<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+			<&pcie_0_pipe_clk>;
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_aux_clk", "pcie_cfg_ahb_clk",
+				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+				"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
+				"pcie_rate_change_clk",
+				"gcc_ddrss_pcie_sf_qtb_clk",
+				"pcie_aggre_noc_axi_clk",
+				"gcc_cnoc_pcie_sf_axi_clk", "pcie_0_pipe_div2_clk",
+				"pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src";
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
+				<100000000>, <0>, <0>, <0>, <0>, <0>, <0>;
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
+				<0>, <0>, <0>, <1>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1400>;
+		iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+				<0x100 &apps_smmu 0x1401 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <150>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+		qcom,drv-name = "lpass";
+		qcom,drv-l1ss-timeout-us = <5000>;
+
+		qcom,pcie-phy-ver = <112>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x00c0 0x01 0x0
+				0x00cc 0x62 0x0
+				0x00d0 0x02 0x0
+				0x0060 0xf8 0x0
+				0x0064 0x01 0x0
+				0x0000 0x93 0x0
+				0x0004 0x01 0x0
+				0x00e0 0x90 0x0
+				0x00e4 0x82 0x0
+				0x00f4 0x07 0x0
+				0x0070 0x02 0x0
+				0x0010 0x02 0x0
+				0x0074 0x16 0x0
+				0x0014 0x16 0x0
+				0x0078 0x36 0x0
+				0x0018 0x36 0x0
+				0x0110 0x08 0x0
+				0x00bc 0x0a 0x0
+				0x0120 0x42 0x0
+				0x0080 0x04 0x0
+				0x0084 0x0d 0x0
+				0x0020 0x0a 0x0
+				0x0024 0x1a 0x0
+				0x0088 0x41 0x0
+				0x0028 0x34 0x0
+				0x0090 0xab 0x0
+				0x0094 0xaa 0x0
+				0x0098 0x01 0x0
+				0x0030 0x55 0x0
+				0x0034 0x55 0x0
+				0x0038 0x01 0x0
+				0x0140 0x14 0x0
+				0x0164 0x34 0x0
+				0x003c 0x01 0x0
+				0x001c 0x04 0x0
+				0x0174 0x16 0x0
+				0x01bc 0x0f 0x0
+				0x0170 0xa0 0x0
+				0x11a4 0x38 0x0
+				0x10dc 0x11 0x0
+				0x1160 0xbf 0x0
+				0x1164 0xbf 0x0
+				0x1168 0xb7 0x0
+				0x116c 0xea 0x0
+				0x115c 0x3f 0x0
+				0x1174 0x5c 0x0
+				0x1178 0x9c 0x0
+				0x117c 0x1a 0x0
+				0x1180 0x89 0x0
+				0x1170 0xdc 0x0
+				0x1188 0x94 0x0
+				0x118c 0x5b 0x0
+				0x1190 0x1a 0x0
+				0x1194 0x89 0x0
+				0x10cc 0x00 0x0
+				0x1008 0x09 0x0
+				0x1014 0x05 0x0
+				0x104c 0x08 0x0
+				0x1050 0x08 0x0
+				0x10d8 0x0f 0x0
+				0x1118 0x1c 0x0
+				0x10f8 0x07 0x0
+				0x11f8 0x08 0x0
+				0x1600 0x00 0x0
+				0x0e84 0x15 0x0
+				0x0e90 0x3f 0x0
+				0x0ee4 0x02 0x0
+				0x0e40 0x06 0x0
+				0x0e3c 0x18 0x0
+				0x19a4 0x38 0x0
+				0x18dc 0x11 0x0
+				0x1960 0xbf 0x0
+				0x1964 0xbf 0x0
+				0x1968 0xb7 0x0
+				0x196c 0xea 0x0
+				0x195c 0x3f 0x0
+				0x1974 0x5c 0x0
+				0x1978 0x9c 0x0
+				0x197c 0x1a 0x0
+				0x1980 0x89 0x0
+				0x1970 0xdc 0x0
+				0x1988 0x94 0x0
+				0x198c 0x5b 0x0
+				0x1990 0x1a 0x0
+				0x1994 0x89 0x0
+				0x18cc 0x00 0x0
+				0x1808 0x09 0x0
+				0x1814 0x05 0x0
+				0x184c 0x08 0x0
+				0x1850 0x08 0x0
+				0x18d8 0x0f 0x0
+				0x1918 0x1c 0x0
+				0x18f8 0x07 0x0
+				0x19f8 0x08 0x0
+				0x1684 0x15 0x0
+				0x1690 0x3f 0x0
+				0x16e4 0x02 0x0
+				0x1640 0x06 0x0
+				0x163c 0x18 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x77 0x0
+				0x0398 0x0b 0x0
+				0x06a4 0x1e 0x0
+				0x06f4 0x27 0x0
+				0x03e0 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x03d0 0x8c 0x0
+				0x0368 0x17 0x0
+				0x0370 0x2e 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie0_rp: pcie0_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@17110040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17110040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+		status = "disabled";
+	};
+};
diff --git a/qcom/tuna-pinctrl.dtsi b/qcom/tuna-pinctrl.dtsi
index 8c3ca7ff..61496114 100644
--- a/qcom/tuna-pinctrl.dtsi
+++ b/qcom/tuna-pinctrl.dtsi
@@ -4,6 +4,337 @@
  */
 
 &tlmm {
+	i2s0_sck {
+		i2s0_sck_sleep: i2s0_sck_sleep {
+			mux {
+				pins = "gpio128";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s0_sck_active: i2s0_sck_active {
+			mux {
+				pins = "gpio128";
+				function = "i2s0_sck";
+			};
+
+			config {
+				pins = "gpio128";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s0_ws {
+		i2s0_ws_sleep: i2s0_ws_sleep {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s0_ws_active: i2s0_ws_active {
+			mux {
+				pins = "gpio129";
+				function = "i2s0_ws";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s0_sd0 {
+		i2s0_sd0_sleep: i2s0_sd0_sleep {
+			mux {
+				pins = "gpio130";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio130";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s0_sd0_active: i2s0_sd0_active {
+			mux {
+				pins = "gpio130";
+				function = "i2s0_data0";
+			};
+
+			config {
+				pins = "gpio130";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s0_sd1 {
+		i2s0_sd1_sleep: i2s0_sd1_sleep {
+			mux {
+				pins = "gpio131";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio131";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s0_sd1_active: i2s0_sd1_active {
+			mux {
+				pins = "gpio131";
+				function = "i2s0_data1";
+			};
+
+			config {
+				pins = "gpio131";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+
+	i2s1_sck {
+		i2s1_sck_sleep: i2s1_sck_sleep {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s1_sck_active: i2s1_sck_active {
+			mux {
+				pins = "gpio123";
+				function = "i2s1_sck";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s1_ws {
+		i2s1_ws_sleep: i2s1_ws_sleep {
+			mux {
+				pins = "gpio125";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s1_ws_active: i2s1_ws_active {
+			mux {
+				pins = "gpio125";
+				function = "i2s1_ws";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s1_sd0 {
+		i2s1_sd0_sleep: i2s1_sd0_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s1_sd0_active: i2s1_sd0_active {
+			mux {
+				pins = "gpio124";
+				function = "i2s1_data0";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	i2s1_sd1 {
+		i2s1_sd1_sleep: i2s1_sd1_sleep {
+			mux {
+				pins = "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		i2s1_sd1_active: i2s1_sd1_active {
+			mux {
+				pins = "gpio126";
+				function = "i2s1_data1";
+			};
+
+			config {
+				pins = "gpio126";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	/* WCD reset pin */
+	wcd_reset_active: wcd_reset_active {
+		mux {
+			pins = "gpio150";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio150";
+			drive-strength = <16>;
+			output-high;
+		};
+	};
+
+	wcd_reset_sleep: wcd_reset_sleep {
+		mux {
+			pins = "gpio150";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio150";
+			drive-strength = <16>;
+			bias-disable;
+			output-low;
+		};
+	};
+
+/* WSA speaker reset pins  North Pins*/
+	spkr_1_sd_n {
+		spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+			mux {
+				pins = "gpio119";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio119";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_1_sd_n_active: spkr_1_sd_n_active {
+			mux {
+				pins = "gpio119";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio119";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+/* WSA speaker reset pins  south Pins*/
+	spkr_2_sd_n {
+		spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+			mux {
+				pins = "gpio183";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio183";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_2_sd_n_active: spkr_2_sd_n_active {
+			mux {
+				pins = "gpio183";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio183";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
 	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
 		qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
 			mux {
@@ -1584,21 +1915,21 @@
 	sdc2_on: sdc2_on {
 		clk {
 			pins = "gpio62";
-			function = "sdc2_clk";
+			function = "SDC2_CLK";
 			bias-disable;
 			drive-strength = <16>;
 		};
 
 		cmd {
 			pins = "gpio51";
-			function = "sdc2_cmd";
+			function = "SDC2_CMD";
 			bias-pull-up;
 			drive-strength = <10>;
 		};
 
 		data {
 			pins = "gpio63", "gpio120", "gpio48", "gpio49";
-			function = "sdc2_data";
+			function = "SDC2_DATA";
 			bias-pull-up;
 			drive-strength = <10>;
 		};
@@ -1638,8 +1969,8 @@
 			drive-strength = <2>;
 		};
 	};
-	/* touchscreen pins */
 
+	/* touchscreen pins */
 	pmx_ts_active {
 		ts_active: ts_active {
 			mux {
@@ -1700,4 +2031,58 @@
 		};
 	};
 
+	pcie0 {
+		pcie0_perst_default: pcie0_perst_default {
+			mux {
+				pins = "gpio33";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio33";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie0_clkreq_default: pcie0_clkreq_default {
+			mux {
+				pins = "gpio118";
+				function = "pcie0_clk_req_n";
+			};
+
+			config {
+				pins = "gpio118";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_wake_default: pcie0_wake_default {
+			mux {
+				pins = "gpio81";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio81";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+			mux {
+				pins = "gpio118";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio118";
+				drive-strength = <2>;
+				bias-pull-up;
+				input-enable;
+			};
+		};
+	};
 };
diff --git a/qcom/tuna-pm7550ba-pmd802x.dtsi b/qcom/tuna-pm7550ba-pmd802x.dtsi
new file mode 100644
index 00000000..f338c006
--- /dev/null
+++ b/qcom/tuna-pm7550ba-pmd802x.dtsi
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "tuna-pm7550ba.dtsi"
+#include "pmd802x.dtsi"
+
+/ {
+	qcom,pmic-id-size = <8>;
+	qcom,pmic-id = <0x0 0x0 0x0 0x0 0x57 0x0 0x0 0x4C>;
+};
+
+&pm7550ba_amoled {
+	status = "disabled";
+};
+
+&pm7550ba_amoled_ecm {
+	status = "disabled";
+};
+
+&pmic_glink_debug {
+	/delete-node/ i2c@104;
+	/delete-node/ spmi@200;
+
+		i2c@104 {
+		reg = <0x104>;  /* I2C instance 4 in ADSP for SE5 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		qcom,bus-type = "i2c";
+
+		qcom,smb1500@69 {
+			compatible = "qcom,i2c-pmic";
+			reg = <0x69>;
+			qcom,can-sleep;
+		};
+
+		qcom,smb1500@68 {
+			compatible = "qcom,i2c-pmic";
+			reg = <0x68>;
+			qcom,can-sleep;
+		};
+	};
+};
+
+&pmic_glink_adc {
+	status = "ok";
+	/delete-node/ smb1398_1_iin;
+	/delete-node/ smb1398_1_ichg;
+	/delete-node/ smb1398_1_die_temp;
+
+	smb1500_1_iin {
+		reg = <0x1046901>;
+		label = "smb1393_1_iin";
+	};
+
+	smb1500_1_ichg {
+		reg = <0x1046902>;
+		label = "smb1393_1_ichg";
+	};
+
+	smb1500_1_die_temp {
+		reg = <0x1046903>;
+		label = "smb1393_1_die_temp";
+	};
+
+	smb1500_2_iin {
+		reg = <0x1046801>;
+		label = "smb1393_2_iin";
+	};
+
+	smb1500_2_ichg {
+		reg = <0x1046802>;
+		label = "smb1393_2_ichg";
+	};
+
+	smb1500_2_die_temp {
+		reg = <0x1046803>;
+		label = "smb1393_2_die_temp";
+	};
+};
diff --git a/qcom/tuna-pm7550ba.dtsi b/qcom/tuna-pm7550ba.dtsi
index 67e544ad..e0d2e5c3 100644
--- a/qcom/tuna-pm7550ba.dtsi
+++ b/qcom/tuna-pm7550ba.dtsi
@@ -5,6 +5,8 @@
 
 #include "pm7550ba.dtsi"
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm7550ba.h>
 
 / {
 	qcom,pmic-id-size = <8>;
@@ -34,6 +36,126 @@
 			qcom,can-sleep;
 		};
 	};
+
+	i2c@104 {
+		reg = <0x104>;  /* I2C instance 4 in ADSP for SE5 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		qcom,bus-type = "i2c";
+
+		qcom,smb1398@34 {
+			compatible = "qcom,i2c-pmic";
+			reg = <0x34>;
+			qcom,can-sleep;
+		};
+	};
+
+	/* SPMI bridge bus 1 with SMB1510 device */
+	spmi@200 {
+		reg = <0x200>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,bus-type = "spmi";
+
+		qcom,smb1510@d {
+			compatible = "qcom,spmi-pmic";
+			reg = <13 SPMI_USID>;
+			qcom,can-sleep;
+		};
+	};
+};
+
+&pmic_glink_adc {
+	status = "ok";
+
+	smb1398_1_iin {
+		reg = <0x1043401>;
+		label = "smb1393_1_iin";
+	};
+
+	smb1398_1_ichg {
+		reg = <0x1043402>;
+		label = "smb1393_1_ichg";
+	};
+
+	smb1398_1_die_temp {
+		reg = <0x1043403>;
+		label = "smb1393_1_die_temp";
+	};
+};
+
+&pmk8550_vadc {
+	pinctrl-0 = <&sys_therm_7_gpio6_default &sys_therm_6_gpio7_default>;
+	pinctrl-names = "default";
+
+	/* PM7550BA Channel nodes */
+	pm7550ba_offset_ref {
+		reg = <PM7550BA_ADC5_GEN3_OFFSET_REF>;
+		label = "pm7550ba_offset_ref";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm7550ba_vref_1p25 {
+		reg = <PM7550BA_ADC5_GEN3_1P25VREF>;
+		label = "pm7550ba_vref_1p25";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm7550ba_die_temp {
+		reg = <PM7550BA_ADC5_GEN3_DIE_TEMP>;
+		label = "pm7550ba_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm7550ba_vph_pwr {
+		reg = <PM7550BA_ADC5_GEN3_VPH_PWR>;
+		label = "pm7550ba_vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	pm7550ba_chg_temp {
+		reg = <PM7550BA_ADC5_GEN3_CHG_TEMP_V>;
+		label = "pm7550ba_chg_temp";
+	};
+
+	pm7550ba_iin_fb {
+		reg = <PM7550BA_ADC5_GEN3_IIN_FB>;
+		label = "pm7550ba_iin_fb";
+	};
+
+	pm7550ba_ichg_fb {
+		reg = <PM7550BA_ADC5_GEN3_ICHG_FB>;
+		label = "pm7550ba_ichg_fb";
+	};
+
+	pm7550ba_sys_therm_7 {
+		reg = <PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
+		label = "pm7550ba_sys_therm_7";
+		qcom,adc-tm-type = <1>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm7550ba_sys_therm_8 {
+		reg = <PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
+		label = "pm7550ba_sys_therm_8";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+
+	};
+
+	pm7550ba_batt_therm {
+		reg = <PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU>;
+		label = "pm7550ba_batt_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
+	};
+
 };
 
 &pm7550ba_vib {
@@ -44,3 +166,61 @@
 	status = "okay";
 };
 
+&pm7550ba_tz {
+	io-channels = <&pmk8550_vadc PM7550BA_ADC5_GEN3_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&battery_charger {
+	qcom,thermal-mitigation-step = <500000>;
+	#cooling-cells = <2>;
+};
+
+&pm7550ba_gpios {
+	sys_therm_7_gpio6 {
+		sys_therm_7_gpio6_default: sys_therm_7_gpio6_default {
+			pins = "gpio6";
+			bias-high-impedance;
+		};
+	};
+};
+
+&thermal_zones {
+	sys-therm-7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-8 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/tuna-pmic-overlay.dtsi b/qcom/tuna-pmic-overlay.dtsi
index e6ad7b1b..6fe5a0e0 100644
--- a/qcom/tuna-pmic-overlay.dtsi
+++ b/qcom/tuna-pmic-overlay.dtsi
@@ -11,7 +11,6 @@
 #include "pm8550vs.dtsi"
 #include "pmr735b.dtsi"
 #include "pm8550ve.dtsi"
-#include "pmd802x.dtsi"
 #include "pm8010.dtsi"
 
 &pm8550vs_g {
@@ -108,6 +107,12 @@
 			linux,can-disable;
 		};
 	};
+
+	reboot_reason {
+		compatible = "qcom,reboot-reason";
+		nvmem-cells = <&restart_reason>;
+		nvmem-cell-names = "restart_reason";
+	};
 };
 
 &thermal_zones {
@@ -243,6 +248,25 @@
 			};
 		};
 	};
+
+	sys-therm-11 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
 };
 
 &pmk8550_vadc {
@@ -342,6 +366,15 @@
 		qcom,adc-tm-type = <1>;
 	};
 
+	pmxr2230_sys_therm_11 {
+		reg = <PMXR2230_ADC5_GEN3_AMUX_THM5_100K_PU>;
+		label = "pmxr2230_sys_therm_11";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
 	pm8550vs_d_die_temp {
 		reg = <PM8550VX_ADC5_GEN3_DIE_TEMP(3)>;
 		label = "pm8550vs_d_die_temp";
diff --git a/qcom/tuna-pmih010x.dtsi b/qcom/tuna-pmih010x.dtsi
new file mode 100644
index 00000000..2834f616
--- /dev/null
+++ b/qcom/tuna-pmih010x.dtsi
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "pmih010x.dtsi"
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen4-pmih010x.h>
+
+&pmic_glink_debug {
+	spmi@0 {
+		reg = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pmih010x_glink_debug: qcom,pmih010x-debug@7 {
+			compatible = "qcom,spmi-pmic";
+			reg = <7 SPMI_USID>;
+			qcom,can-sleep;
+		};
+	};
+
+	i2c@104 {
+		reg = <0x104>;  /* I2C instance 4 in ADSP for SE5 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		qcom,bus-type = "i2c";
+
+		qcom,smb1500@69 {
+			compatible = "qcom,i2c-pmic";
+			reg = <0x69>;
+			qcom,can-sleep;
+		};
+	};
+};
+
+&spmi0_debug_bus {
+	qcom,pmih010x-debug@7 {
+		compatible = "qcom,spmi-pmic";
+		reg = <7 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,can-sleep;
+	};
+};
+
+&pmic_glink_adc {
+	status = "ok";
+
+	smb1500_1_iin {
+		reg = <0x1046901>;
+		label = "smb1393_1_iin";
+	};
+
+	smb1500_1_ichg {
+		reg = <0x1046902>;
+		label = "smb1393_1_ichg";
+	};
+
+	smb1500_1_die_temp {
+		reg = <0x1046903>;
+		label = "smb1393_1_die_temp";
+	};
+};
+
+&battery_charger {
+	qcom,thermal-mitigation-step = <500000>;
+	#cooling-cells = <2>;
+};
+
+&pmih010x_haptics {
+	nvmem-names = "hap_cfg_sdam";
+	nvmem = <&pmk8550_sdam_46>;
+};
+
+&pmih010x_tz {
+	io-channels = <&pmk8550_vadc PMIH010X_ADC5_GEN4_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pmk8550_vadc {
+	pmih010x_sys_therm_8 {
+		reg = <PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU>;
+		label = "pmih010x_usb_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_sys_therm_7 {
+		reg = <PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU>;
+		label = "pmih010x_wls_therm";
+		qcom,ratiometric;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_offset_ref {
+		reg = <PMIH010X_ADC5_GEN4_OFFSET_REF>;
+		label = "pmih010x_offset_ref";
+		qcom,pre-scaling = <1 1>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_vref_1p25 {
+		reg = <PMIH010X_ADC5_GEN4_1P25VREF>;
+		label = "pmih010x_vref_1p25";
+		qcom,pre-scaling = <1 1>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_die_temp {
+		reg = <PMIH010X_ADC5_GEN4_DIE_TEMP>;
+		label = "pmih010x_die_temp";
+		qcom,pre-scaling = <1 1>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_vph_pwr {
+		reg = <PMIH010X_ADC5_GEN4_VPH_PWR>;
+		label = "pmih010x_vph_pwr";
+		qcom,pre-scaling = <1 3>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_vbat_sns_qbg {
+		reg = <PMIH010X_ADC5_GEN4_VBAT_SNS_QBG>;
+		label = "pmih010x_vbat_sns_qbg";
+		qcom,pre-scaling = <1 3>;
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_iin {
+		reg = <PMIH010X_ADC5_GEN4_IIN>;
+		label = "pmih010x_iin";
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_ichg_fb {
+		reg = <PMIH010X_ADC5_GEN4_ICHG_FB>;
+		label = "pmih010x_ichg_fb";
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_chg_temp {
+		reg = <PMIH010X_ADC5_GEN4_CHG_TEMP>;
+		label = "pmih010x_chg_temp";
+		qcom,adc5-gen4;
+	};
+
+	pmih010x_lite_die_temp {
+		reg = <PMIH010X_ADC5_GEN4_TEMP_ALARM_LITE>;
+		label = "pmih010x_lite_die_temp";
+		qcom,pre-scaling = <1 1>;
+		qcom,adc5-gen4;
+	};
+};
+
+&thermal_zones {
+	sys-therm-7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PMIH010X_ADC5_GEN4_AMUX4_GPIO12_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-8 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PMIH010X_ADC5_GEN4_AMUX_THM4_USB_THERM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/tuna-pmiv0108.dtsi b/qcom/tuna-pmiv0108.dtsi
new file mode 100644
index 00000000..95be68f8
--- /dev/null
+++ b/qcom/tuna-pmiv0108.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmiv0104.h>
+#include "pmiv010x.dtsi"
+
+&pmiv010x_gpios {
+	charger_skin_therm {
+		charger_skin_therm_default: charger_skin_therm_default {
+			pins = "gpio6";
+			bias-high-impedence;
+		};
+	};
+};
+
+&pmiv010x_amoled {
+	status= "disabled";
+};
+
+&pmiv010x_amoled_ecm {
+	status = "disabled";
+};
+
+&pmiv010x_tz {
+	io-channels = <&pmk8550_vadc PMIV0104_ADC5_GEN3_DIE_TEMP>;
+	io-channel-names = "thermal";
+
+};
+
+&battery_charger {
+	#cooling-cells = <2>;
+	qcom,thermal-mitigation-step = <500000>;
+};
+
+&pmk8550_vadc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&charger_skin_therm_default &sys_therm_6_gpio7_default>;
+
+	pmiv010x_ref_gnd {
+		reg = <PMIV0104_ADC5_GEN3_OFFSET_REF>;
+		label = "pmiv010x_ref_gnd";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pmiv010x_vref_1p25 {
+		reg = <PMIV0104_ADC5_GEN3_1P25VREF>;
+		label = "pmiv010x_vref_1p25";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pmiv010x_die_temp {
+		reg = <PMIV0104_ADC5_GEN3_DIE_TEMP>;
+		label = "pmiv010x_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pmiv010x_vph_pwr {
+		reg = <PMIV0104_ADC5_GEN3_VPH_PWR>;
+		label = "pmiv010x_vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	pmiv010x_vbat_sns_qbg {
+		reg = <PMIV0104_ADC5_GEN3_VBAT_SNS_QBG>;
+		label = "pmiv010x_vbat_sns";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	pmiv010x_chg_temp {
+		reg = <PMIV0104_ADC5_GEN3_CHG_TEMP>;
+		label = "pmiv010x_chg_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pmiv010x_bat_therm {
+		reg = <PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU>;
+		label = "pmiv010x_bat_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_THERM_100K>;
+	};
+
+	pmiv010x_bat_id {
+		reg = <PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU>;
+		label = "pmiv010x_bat_id";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K>;
+	};
+
+	pmiv010x_iin_fb {
+		reg = <PMIV0104_ADC5_GEN3_IIN_FB>;
+		label = "pmiv010x_iin_fb";
+	};
+
+	pmiv010x_ichg_fb {
+		reg = <PMIV0104_ADC5_GEN3_ICHG_FB>;
+		label = "pmiv010x_ichg_fb";
+	};
+
+	pmiv010x_sys_therm_7 {
+		reg = <PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
+		label = "pmiv010x_charger_skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+
+	pmiv010x_sys_therm_8 {
+		reg = <PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
+		label = "pmiv010x_conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,adc-tm-type = <1>;
+	};
+};
+
+&pmic_glink_debug {
+	spmi@0 {
+		reg = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,pmiv010x-debug@7 {
+			compatible = "qcom,spmi-pmic";
+			reg = <7 SPMI_USID>;
+			qcom,can-sleep;
+		};
+	};
+};
+
+&spmi0_debug_bus {
+	qcom,pmiv010x-debug@7 {
+		compatible = "qcom,spmi-pmic";
+		reg = <7 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		qcom,can-sleep;
+	};
+};
+
+&thermal_zones {
+	sys-therm-7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-8 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmk8550_vadc PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/tuna-qrd-overlay.dts b/qcom/tuna-qrd-overlay.dts
index 571501ce..8ee4d7ae 100644
--- a/qcom/tuna-qrd-overlay.dts
+++ b/qcom/tuna-qrd-overlay.dts
@@ -7,6 +7,8 @@
 /plugin/;
 
 #include "tuna-qrd.dtsi"
+#include "tuna-pmih010x.dtsi"
+#include "pmd802x.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna QRD";
diff --git a/qcom/tuna-qrd.dtsi b/qcom/tuna-qrd.dtsi
index f307bb6f..86cea255 100644
--- a/qcom/tuna-qrd.dtsi
+++ b/qcom/tuna-qrd.dtsi
@@ -2,6 +2,8 @@
 /*
  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sun.h>
 
 &qupv3_se4_spi {
 	#address-cells = <1>;
@@ -86,3 +88,30 @@
 
 	status = "ok";
 };
+
+&sdhc_2 {
+	vdd-supply = <&L13B>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 976310>;
+
+	vdd-io-supply = <&L23B>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 5830>;
+
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&sdc2_on>;
+	pinctrl-1 = <&sdc2_off>;
+
+	cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+
+	resets = <&gcc GCC_SDCC2_BCR>;
+	reset-names = "core_reset";
+
+	qcom,uses_level_shifter;
+
+	status = "ok";
+};
+
+&thermal_zones {
+	/delete-node/ sys-therm-11;
+};
diff --git a/qcom/tuna-rcm-kiwi-overlay.dts b/qcom/tuna-rcm-kiwi-overlay.dts
index 878afb01..10c4409c 100644
--- a/qcom/tuna-rcm-kiwi-overlay.dts
+++ b/qcom/tuna-rcm-kiwi-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-rcm-kiwi.dtsi"
+#include "tuna-pmiv0108.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna RCM + kiwi WLAN";
diff --git a/qcom/tuna-rcm-overlay.dts b/qcom/tuna-rcm-overlay.dts
index 8ca3a067..c47d003b 100644
--- a/qcom/tuna-rcm-overlay.dts
+++ b/qcom/tuna-rcm-overlay.dts
@@ -7,6 +7,7 @@
 /plugin/;
 
 #include "tuna-rcm.dtsi"
+#include "tuna-pmiv0108.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Tuna RCM";
diff --git a/qcom/tuna-regulators.dtsi b/qcom/tuna-regulators.dtsi
new file mode 100644
index 00000000..e0fb9e3d
--- /dev/null
+++ b/qcom/tuna-regulators.dtsi
@@ -0,0 +1,1319 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&apps_rsc_drv2 {
+	rpmh-regulator-smpb1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb1";
+		S1B:
+		pmxr2230_s1: regulator-pmxr2230-s1 {
+			regulator-name = "pmxr2230_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1856000>;
+			regulator-max-microvolt = <2104000>;
+			qcom,init-voltage = <1856000>;
+		};
+	};
+
+	rpmh-regulator-smpb2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb2";
+		S2B:
+		pmxr2230_s2: regulator-pmxr2230-s2 {
+			regulator-name = "pmxr2230_s2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1256000>;
+			regulator-max-microvolt = <1408000>;
+			qcom,init-voltage = <1256000>;
+		};
+	};
+
+	rpmh-regulator-smpb3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpb3";
+		S3B:
+		pmxr2230_s3: regulator-pmxr2230-s3 {
+			regulator-name = "pmxr2230_s3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <1040000>;
+			qcom,init-voltage = <952000>;
+		};
+	};
+
+	rpmh-regulator-ldob1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1B:
+		pmxr2230_l1: regulator-pmxr2230-l1 {
+			regulator-name = "pmxr2230_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <866000>;
+			regulator-max-microvolt = <958000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2B:
+		pmxr2230_l2: regulator-pmxr2230-l2 {
+			regulator-name = "pmxr2230_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <950000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3B:
+		pmxr2230_l3: regulator-pmxr2230-l3 {
+			regulator-name = "pmxr2230_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <831000>;
+			regulator-max-microvolt = <919000>;
+			qcom,init-voltage = <880000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L4B:
+		pmxr2230_l4: regulator-pmxr2230-l4 {
+			regulator-name = "pmxr2230_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_RET
+			RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000 30000>;
+		L5B:
+		pmxr2230_l5: regulator-pmxr2230-l5 {
+			regulator-name = "pmxr2230_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldob6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L6B:
+		pmxr2230_l6: regulator-pmxr2230-l6 {
+			regulator-name = "pmxr2230_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1170000>;
+			regulator-max-microvolt = <1370000>;
+			qcom,init-voltage = <1256000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L7B:
+		pmxr2230_l7: regulator-pmxr2230-l7 {
+			regulator-name = "pmxr2230_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob8 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob8";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L8B:
+		pmxr2230_l8: regulator-pmxr2230-l8 {
+			regulator-name = "pmxr2230_l8";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob9 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob9";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L9B:
+		pmxr2230_l9: regulator-pmxr2230-l9 {
+			regulator-name = "pmxr2230_l9";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <756000>;
+			regulator-max-microvolt = <816000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob10";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L10B:
+		pmxr2230_l10: regulator-pmxr2230-l10 {
+			regulator-name = "pmxr2230_l10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <866000>;
+			regulator-max-microvolt = <931000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob11 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob11";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L11B:
+		pmxr2230_l11: regulator-pmxr2230-l11 {
+			regulator-name = "pmxr2230_l11";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <2000000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob12 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob12";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L12B:
+		pmxr2230_l12: regulator-pmxr2230-l12 {
+			regulator-name = "pmxr2230_l12";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2400000>;
+			regulator-max-microvolt = <3300000>;
+			qcom,init-voltage = <2504000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob13 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob13";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L13B:
+		pmxr2230_l13: regulator-pmxr2230-l13 {
+			regulator-name = "pmxr2230_l13";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3300000>;
+			qcom,init-voltage = <2960000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob14 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob14";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L14B:
+		pmxr2230_l14: regulator-pmxr2230-l14 {
+			regulator-name = "pmxr2230_l14";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1504000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob15 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob15";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L15B:
+		pmxr2230_l15: regulator-pmxr2230-l15 {
+			regulator-name = "pmxr2230_l15";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1620000>;
+			regulator-max-microvolt = <3300000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob16 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob16";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L16B:
+		pmxr2230_l16: regulator-pmxr2230-l16 {
+			regulator-name = "pmxr2230_l16";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2600000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <3008000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob17 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob17";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L17B:
+		pmxr2230_l17: regulator-pmxr2230-l17 {
+			regulator-name = "pmxr2230_l17";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <3104000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob18 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob18";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L18B:
+		pmxr2230_l18: regulator-pmxr2230-l18 {
+			regulator-name = "pmxr2230_l18";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1600000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <2800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob19 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob19";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L19B:
+		pmxr2230_l19: regulator-pmxr2230-l19 {
+			regulator-name = "pmxr2230_l19";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2650000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <3000000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob20 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob20";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L20B:
+		pmxr2230_l20: regulator-pmxr2230-l20 {
+			regulator-name = "pmxr2230_l20";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1504000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob21 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob21";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L21B:
+		pmxr2230_l21: regulator-pmxr2230-l21 {
+			regulator-name = "pmxr2230_l21";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1504000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob22 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob22";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L22B:
+		pmxr2230_l22: regulator-pmxr2230-l22 {
+			regulator-name = "pmxr2230_l22";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <3200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldob23 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldob23";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 10000>;
+		L23B:
+		pmxr2230_l23: regulator-pmxr2230-l23 {
+			regulator-name = "pmxr2230_l23";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <3544000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-msslvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mss.lvl";
+		VDD_MODEM_LEVEL:
+		S1D_LEVEL:
+		pm_v6d_s1_level: regulator-pm_v6d-s1-level {
+			regulator-name = "pm_v6d_s1_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-nsplvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "nsp.lvl";
+		VDD_NSP1_LEVEL:
+		S4D_LEVEL:
+		pm_v6d_s4_level: regulator-pm_v6d-s4-level {
+			regulator-name = "pm-v6d_s4_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-gfxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "gfx.lvl";
+		VDD_GFX_LEVEL:
+		S5F_LEVEL:
+		pm_v8f_s5_level: regulator-pm_v8f-s5-level {
+			regulator-name = "pm_v8f_s5_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-mmcxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mmcx.lvl";
+		proxy-supply = <&VDD_MMCX_LEVEL>;
+
+		VDD_MMCX_LEVEL: VDD_MM_LEVEL: S2F_LEVEL:
+		pm_v8f_s2_level: regulator-pm-v8f-s2-level {
+			regulator-name = "pm_v8f_s2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				 RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MMCX_LEVEL_AO: VDD_MM_LEVEL_AO: S2F_LEVEL_AO:
+		pm_v8f_s2_level_ao: regulator-pm-v8f-s2-level-ao {
+			regulator-name = "pm_v8f_s2_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+		};
+
+		regulator-pm-v8f-s2-level-so {
+			regulator-name = "pm_v8i_s2_level_so";
+			qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+		};
+	};
+
+	rpmh-regulator-mxclvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mxc.lvl";
+		proxy-supply = <&VDD_MXC_LEVEL>;
+
+		VDD_MXC_LEVEL:
+		S2D_LEVEL:
+		pm_v6d_s2_level: regulator-pm_v6d-s2-level {
+			regulator-name = "pm_v6d_s2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+					RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MXC_LEVEL_AO:
+		S2D_LEVEL_AO:
+		pm_v6d_s2_level_ao: regulator-pm_v6d-s2-level-ao {
+			regulator-name = "pm_v6d_s2_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+
+		VDD_MXC_MMCX_VOTER_LEVEL: VDD_MXC_MM_VOTER_LEVEL:
+		VDD_MM_MXC_VOTER_LEVEL: regulator-pm_v6d-s2-mmcx-voter-level {
+			regulator-name = "pm_v6d_s2_mmcx_voter_level";
+			pm_v6d_s2_mmcx_voter_level-parent-supply =
+				<&VDD_MMCX_LEVEL>;
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+		};
+
+		VDD_MXC_GFX_VOTER_LEVEL: VDD_GFX_MXC_VOTER_LEVEL:
+			regulator-pm_v6d-s2-gfx-voter-level {
+			regulator-name = "pm_v6d_s2_gfx_voter_level";
+			pm_v6d_s2_gfx_voter_level-parent-supply = <&VDD_GFX_LEVEL>;
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+			regulator-max-microvolt =
+				<RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_MIN_SVS>;
+		};
+	};
+
+	rpmh-regulator-smpd3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpd3";
+		S3D:
+		pm_v6d_s3: regulator-pm_v6d-s3 {
+			regulator-name = "pm_v6d_s3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <870000>;
+			regulator-max-microvolt = <970000>;
+			qcom,init-voltage = <904000>;
+		};
+	};
+
+	rpmh-regulator-ldod1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldod1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1D:
+		pm_v6d_l1: regulator-pm_v6d-l1 {
+			regulator-name = "pm_v6d_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1710000>;
+			regulator-max-microvolt = <1950000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-lmxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "lmx.lvl";
+		VDD_LPI_MX_LEVEL:
+		L2D_LEVEL:
+		pm_v6d_l2_level: regulator-pm_v6d-l2-level {
+			regulator-name = "pm_v6d_l2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-ldod3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldod3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3D:
+		pm_v6d_l3: regulator-pm_v6d-l3 {
+			regulator-name = "pm_v6d_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1030000>;
+			regulator-max-microvolt = <1100000>;
+			qcom,init-voltage = <1060000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-cxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "cx.lvl";
+		proxy-supply = <&VDD_CX_LEVEL>;
+
+		VDD_CX_LEVEL:
+		S1F_LEVEL:
+		pm_v8f_s1_level: regulator-pm_v8f-s1-level {
+			regulator-name = "pm_v8f_s1_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_CX_LEVEL_AO:
+		S1F_LEVEL_AO:
+		pm_v8f_s1_level_ao: regulator-pm_v8f-s1-level-ao {
+			regulator-name = "pm_v8f_s1_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-smpf4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpf4";
+		S4F:
+		pm_v8f_s4: regulator-pm_v8f-s4 {
+			regulator-name = "pm_v8f_s4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <570000>;
+			qcom,init-voltage = <500000>;
+		};
+	};
+
+	rpmh-regulator-mxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mx.lvl";
+		proxy-supply = <&VDD_MXA_LEVEL>;
+
+		VDD_MX_LEVEL:
+		VDD_MXA_LEVEL:
+		S8F_LEVEL:
+		pm_v8f_s8_level: regulator-pm_v8f-s8-level {
+			regulator-name = "pm_v8f_s8_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_TURBO>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-voltage =
+				<RPMH_REGULATOR_LEVEL_TURBO
+				RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MXA_LEVEL_AO:
+		S8F_LEVEL_AO:
+		pm_v8f_s8_level_ao: regulator-pm_v8f-s8-level-ao {
+			regulator-name = "pm_v8f_s8_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-ldof1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1F:
+		pm_v8f_l1: regulator-pm_v8f-l1 {
+			regulator-name = "pm_v8f_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <866000>;
+			regulator-max-microvolt = <958000>;
+			qcom,init-voltage = <912000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-lcxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "lcx.lvl";
+		VDD_LPI_CX_LEVEL:
+		L2F_LEVEL:
+		pm_v8f_l2_level: regulator-pm_v8-l2-level {
+			regulator-name = "pm_v8f_l2_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-ldof3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldof3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		proxy-supply = <&L3F>;
+		L3F:
+		pm_v8f_l3: regulator-pm_v8f-l3 {
+			regulator-name = "pm_v8f_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,proxy-consumer-enable;
+			qcom,proxy-consumer-current = <31000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-smpg1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpg1";
+		S1G:
+		pm_v6g_s1: regulator-pm_v6g-s1 {
+			regulator-name = "pm_v6g_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2156000>;
+			regulator-max-microvolt = <2400000>;
+			qcom,init-voltage = <2200000>;
+		};
+	};
+
+	rpmh-regulator-smpg2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpg2";
+		S2G:
+		pm_v6g_s2: regulator-pm_v6g-s2 {
+			regulator-name = "pm_v6g_s2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1170000>;
+			qcom,init-voltage = <1080000>;
+		};
+	};
+
+	rpmh-regulator-ebilvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "ebi.lvl";
+		VDD_EBI_LEVEL:
+		S3G_LEVEL:
+		pm_v6g_s3_level: regulator-pm_v6g-s3-level {
+			regulator-name = "pm_v6g_s3_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,init-voltage-level =
+				<RPMH_REGULATOR_LEVEL_RETENTION>;
+		};
+	};
+
+	rpmh-regulator-ldog1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldog1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1G:
+		pm_v6g_l1: regulator-pm_v6g-l1 {
+			regulator-name = "pm_v6g_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1600000>;
+			regulator-max-microvolt = <2000000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldog2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldog2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2G:
+		pm_v6g_l2: regulator-pm_v6g-l2 {
+			regulator-name = "pm_v6g_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldog3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldog3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3G:
+		pm_v6g_l3: regulator-pm_v6g-l3 {
+			regulator-name = "pm_v6g_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-smpi1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpi1";
+		S1I:
+		pmg1110i_s1: regulator-pmg1110i-s1 {
+			regulator-name = "pmg1110i_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <352000>;
+			regulator-max-microvolt = <1050000>;
+			qcom,init-voltage = <892000>;
+		};
+	};
+
+	rpmh-regulator-smpj1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpj1";
+		S1J:
+		pmg1110j_s1: regulator-pmg1110j-s1 {
+			regulator-name = "pmg1110j_s1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <504000>;
+			regulator-max-microvolt = <868000>;
+			qcom,init-voltage = <800000>;
+		};
+	};
+
+	rpmh-regulator-ldok1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1K:
+		pmr_nalojr_l1: regulator-pmr-nalojr-l1 {
+			regulator-name = "pmr_nalojr_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <488000>;
+			regulator-max-microvolt = <912000>;
+			qcom,init-voltage = <850000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2K:
+		pmr_nalojr_l2: regulator-pmr_nalojr_l2 {
+			regulator-name = "pmr_nalojr_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <920000>;
+			regulator-max-microvolt = <969000>;
+			qcom,init-voltage = <952000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L3K:
+		pmr_nalojr_l3: regulator-pmr_nalojr_l3 {
+			regulator-name = "pmr_nalojr_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1080000>;
+			regulator-max-microvolt = <1430000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L4K:
+		pmr_nalojr_l4: regulator-pmr_nalojr_l4 {
+			regulator-name = "pmr_nalojr_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L5K:
+		pmr_nalojr_l5: regulator-pmr_nalojr_l5 {
+			regulator-name = "pmr_nalojr_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <504000>;
+			regulator-max-microvolt = <868000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok6";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L6K:
+		pmr_nalojr_l6: regulator-pmr_nalojr_l6 {
+			regulator-name = "pmr_nalojr_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1100000>;
+			regulator-max-microvolt = <2000000>;
+			qcom,init-voltage = <1776000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldok7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldok7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L7K:
+		pmr_nalojr_l7: regulator-pmr_nalojr_l7 {
+			regulator-name = "pmr_nalojr_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <504000>;
+			regulator-max-microvolt = <868000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldom1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1M:
+		pm8010m_l1: regulator-pm8010m-l1 {
+			regulator-name = "pm8010m_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1104000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldom2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2M:
+		pm8010m_l2: regulator-pm8010m-l2 {
+			regulator-name = "pm8010m_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <950000>;
+			regulator-max-microvolt = <1150000>;
+			qcom,init-voltage = <1056000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldom3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom3";
+
+		L3M:
+		pm8010m_l3: regulator-pm8010m-l3 {
+			regulator-name = "pm8010m_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2900000>;
+			qcom,init-voltage = <2800000>;
+		};
+	};
+
+	rpmh-regulator-ldom4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom4";
+
+		L4M:
+		pm8010m_l4: regulator-pm8010m-l4 {
+			regulator-name = "pm8010m_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2900000>;
+			qcom,init-voltage = <2800000>;
+		};
+	};
+
+	rpmh-regulator-ldom5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom5";
+
+		L5M:
+		pm8010m_l5: regulator-pm8010m-l5 {
+			regulator-name = "pm8010m_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+		};
+	};
+
+	rpmh-regulator-ldom6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom6";
+
+		L6M:
+		pm8010m_l6: regulator-pm8010m-l6 {
+			regulator-name = "pm8010m_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2900000>;
+			qcom,init-voltage = <2800000>;
+		};
+	};
+
+	rpmh-regulator-ldom7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldom7";
+
+		L7M:
+		pm8010m_l7: regulator-pm8010m-l7 {
+			regulator-name = "pm8010m_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3000000>;
+			qcom,init-voltage = <2800000>;
+		};
+	};
+
+	rpmh-regulator-ldon1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L1N:
+		pm8010n_l1: regulator-pm8010n-l1 {
+			regulator-name = "pm8010n_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1104000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldon2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 30000>;
+		L2N:
+		pm8010n_l2: regulator-pm8010n-l2 {
+			regulator-name = "pm8010n_l2";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1050000>;
+			regulator-max-microvolt = <1150000>;
+			qcom,init-voltage = <1104000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	rpmh-regulator-ldon3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon3";
+
+		L3N:
+		pm8010n_l3: regulator-pm8010n-l3 {
+			regulator-name = "pm8010n_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1792000>;
+			regulator-max-microvolt = <1900000>;
+			qcom,init-voltage = <1800000>;
+		};
+	};
+
+	rpmh-regulator-ldon4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon4";
+
+		L4N:
+		pm8010n_l4: regulator-pm8010n-l4 {
+			regulator-name = "pm8010n_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1792000>;
+			regulator-max-microvolt = <3312000>;
+			qcom,init-voltage = <1800000>;
+		};
+	};
+
+	rpmh-regulator-ldon5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon5";
+
+		L5N:
+		pm8010n_l5: regulator-pm8010n-l5 {
+			regulator-name = "pm8010n_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1504000>;
+			regulator-max-microvolt = <1980000>;
+			qcom,init-voltage = <1800000>;
+		};
+	};
+
+	rpmh-regulator-ldon6 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon6";
+
+		L6N:
+		pm8010n_l6: regulator-pm8010n-l6 {
+			regulator-name = "pm8010n_l6";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <2900000>;
+			qcom,init-voltage = <2800000>;
+		};
+	};
+
+	rpmh-regulator-ldon7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldon7";
+
+		L7N:
+		pm8010n_l7: regulator-pm8010n-l7 {
+			regulator-name = "pm8010n_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3130000>;
+			regulator-max-microvolt = <3470000>;
+			qcom,init-voltage = <3304000>;
+		};
+	};
+};
diff --git a/qcom/tuna-reserved-memory.dtsi b/qcom/tuna-reserved-memory.dtsi
index 1e9c039f..a0c6bbdf 100644
--- a/qcom/tuna-reserved-memory.dtsi
+++ b/qcom/tuna-reserved-memory.dtsi
@@ -233,6 +233,20 @@
 	 * varies.
 	 */
 
+	trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
+		compatible = "shared-dma-pool";
+		reg = <0x0 0xf3800000 0x0 0x4400000>;
+		reusable;
+		alignment = <0x0 0x400000>;
+	};
+
+	oem_vm_mem: oem_vm_region@f7c00000 {
+		compatible = "shared-dma-pool";
+		reg = <0x0 0xf7c00000 0x0 0x4c00000>;
+		reusable;
+		alignment = <0x0 0x400000>;
+	};
+
 	llcc_lpi_mem: llcc_lpi_region@ff800000 {
 		no-map;
 		reg = <0x0 0xff800000 0x0 0x400000>;
diff --git a/qcom/tuna-rumi.dtsi b/qcom/tuna-rumi.dtsi
index e6ac068f..5f538408 100644
--- a/qcom/tuna-rumi.dtsi
+++ b/qcom/tuna-rumi.dtsi
@@ -174,3 +174,25 @@
 &APSS_OFF {
 	status = "disabled";
 };
+
+&tsens0 {
+	status = "disabled";
+};
+
+&tsens1 {
+	status = "disabled";
+};
+
+&tsens2 {
+	status = "disabled";
+};
+
+&tsens3 {
+	status = "disabled";
+};
+
+&rpmhcc {
+	compatible = "fixed-clock";
+	clock-output-names = "rpmh_clocks";
+	clock-frequency = <19200000>;
+};
diff --git a/qcom/tuna-thermal.dtsi b/qcom/tuna-thermal.dtsi
new file mode 100644
index 00000000..0f0afb75
--- /dev/null
+++ b/qcom/tuna-thermal.dtsi
@@ -0,0 +1,1765 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&soc {
+	tsens0: tsens0@c228000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0xc228000 0x1ff>, /* TM */
+			  <0xc222000 0x1ff>; /* SROT */
+		#qcom,sensors = <8>;
+		interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens1: tsens1@c229000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0xc229000 0x1ff>, /* TM */
+			  <0xc223000 0x1ff>; /* SROT */
+		#qcom,sensors = <11>;
+		interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens2: tsens2@c22a000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0xc22a000 0x1ff>, /* TM */
+			  <0xc224000 0x1ff>; /* SROT */
+		#qcom,sensors = <15>;
+		interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens3: tsens3@c22b000 {
+		compatible = "qcom,tsens-v2";
+		reg = <0xc22b000 0x1ff>, /* TM */
+			  <0xc225000 0x1ff>; /* SROT */
+		#qcom,sensors = <5>;
+		interrupts = <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "uplow","critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	qcom,cpu-pause {
+		compatible = "qcom,thermal-pause";
+
+		cpu0_pause: cpu0-pause {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "thermal-pause-1";
+			#cooling-cells = <2>;
+		};
+
+		cpu1_pause: cpu1-pause {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "thermal-pause-2";
+			#cooling-cells = <2>;
+		};
+
+		cpu2_pause: cpu2-pause {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "thermal-pause-4";
+			#cooling-cells = <2>;
+		};
+
+		cpu3_pause: cpu3-pause {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "thermal-pause-8";
+			#cooling-cells = <2>;
+		};
+
+		cpu4_pause: cpu4-pause {
+			qcom,cpus = <&CPU4>;
+			qcom,cdev-alias = "thermal-pause-10";
+			#cooling-cells = <2>;
+		};
+
+		cpu5_pause: cpu5-pause {
+			qcom,cpus = <&CPU5>;
+			qcom,cdev-alias = "thermal-pause-20";
+			#cooling-cells = <2>;
+		};
+
+		cpu6_pause: cpu6-pause {
+			qcom,cpus = <&CPU6>;
+			qcom,cdev-alias = "thermal-pause-40";
+			#cooling-cells = <2>;
+		};
+
+		cpu7_pause: cpu7-pause {
+			qcom,cpus = <&CPU7>;
+			qcom,cdev-alias = "thermal-pause-80";
+			#cooling-cells = <2>;
+		};
+
+		APC0_MX_CX_PAUSE: apc0-mx-cx-pause {
+			qcom,cpus = <&CPU2 &CPU3 &CPU4 &CPU5>;
+			qcom,cdev-alias = "thermal-pause-3C";
+			#cooling-cells = <2>;
+		};
+
+		APC1_MX_CX_PAUSE: apc1-mx-cx-pause {
+			qcom,cpus = <&CPU6 &CPU7>;
+			qcom,cdev-alias = "thermal-pause-C0";
+			#cooling-cells = <2>;
+		};
+
+		/* Thermal-engine cooling devices */
+		pause-cpu0 {
+			qcom,cpus = <&CPU0>;
+			qcom,cdev-alias = "pause-cpu0";
+		};
+
+		pause-cpu1 {
+			qcom,cpus = <&CPU1>;
+			qcom,cdev-alias = "pause-cpu1";
+		};
+
+		pause-cpu2 {
+			qcom,cpus = <&CPU2>;
+			qcom,cdev-alias = "pause-cpu2";
+		};
+
+		pause-cpu3 {
+			qcom,cpus = <&CPU3>;
+			qcom,cdev-alias = "pause-cpu3";
+		};
+
+		pause-cpu4 {
+			qcom,cpus = <&CPU4>;
+			qcom,cdev-alias = "pause-cpu4";
+		};
+
+		pause-cpu5 {
+			qcom,cpus = <&CPU5>;
+			qcom,cdev-alias = "pause-cpu5";
+		};
+
+		pause-cpu6 {
+			qcom,cpus = <&CPU6>;
+			qcom,cdev-alias = "pause-cpu6";
+		};
+
+		pause-cpu7 {
+			qcom,cpus = <&CPU7>;
+			qcom,cdev-alias = "pause-cpu7";
+		};
+	};
+
+	qcom,cpu-hotplug {
+		compatible = "qcom,cpu-hotplug";
+
+		cpu0_hotplug: cpu0-hotplug {
+			qcom,cpu = <&CPU0>;
+			qcom,cdev-alias = "cpu-hotplug0";
+			#cooling-cells = <2>;
+		};
+
+		cpu1_hotplug: cpu1-hotplug {
+			qcom,cpu = <&CPU1>;
+			qcom,cdev-alias = "cpu-hotplug1";
+			#cooling-cells = <2>;
+		};
+
+		cpu2_hotplug: cpu2-hotplug {
+			qcom,cpu = <&CPU2>;
+			qcom,cdev-alias = "cpu-hotplug2";
+			#cooling-cells = <2>;
+		};
+
+		cpu3_hotplug: cpu3-hotplug {
+			qcom,cpu = <&CPU3>;
+			qcom,cdev-alias = "cpu-hotplug3";
+			#cooling-cells = <2>;
+		};
+
+		cpu4_hotplug: cpu4-hotplug {
+			qcom,cpu = <&CPU4>;
+			qcom,cdev-alias = "cpu-hotplug4";
+			#cooling-cells = <2>;
+		};
+
+		cpu5_hotplug: cpu5-hotplug {
+			qcom,cpu = <&CPU5>;
+			qcom,cdev-alias = "cpu-hotplug5";
+			#cooling-cells = <2>;
+		};
+
+		cpu6_hotplug: cpu6-hotplug {
+			qcom,cpu = <&CPU6>;
+			qcom,cdev-alias = "cpu-hotplug6";
+			#cooling-cells = <2>;
+		};
+
+		cpu7_hotplug: cpu7-hotplug {
+			qcom,cpu = <&CPU7>;
+			qcom,cdev-alias = "cpu-hotplug7";
+			#cooling-cells = <2>;
+		};
+	};
+
+	qcom,cpufreq-cdev {
+		compatible = "qcom,cpufreq-cdev";
+
+		cpu-cluster0 {
+			qcom,cpus = <&CPU0 &CPU1>;
+		};
+
+		cpu-cluster1 {
+			qcom,cpus = <&CPU2 &CPU3 &CPU4>;
+		};
+
+		cpu-cluster2 {
+			qcom,cpus = <&CPU5 &CPU6>;
+		};
+
+		cpu-cluster3 {
+			qcom,cpus = <&CPU7>;
+		};
+	};
+
+	qmi_tmd: qmi-tmd-devices {
+		cdsp {
+			qcom,instance-id = <QMI_CDSP_INST_ID>;
+
+			cdsp_sw: cdsp {
+				qcom,qmi-dev-name = "cdsp_sw";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_sw_hvx: cdsp_sw_hvx {
+				qcom,qmi-dev-name = "cdsp_sw_hvx";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_sw_hmx: cdsp_sw_hmx {
+				qcom,qmi-dev-name = "cdsp_sw_hmx";
+				#cooling-cells = <2>;
+			};
+
+			cdsp_hw: cdsp_hw {
+				qcom,qmi-dev-name = "cdsp_hw";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qcom,userspace-cdev {
+		compatible = "qcom,userspace-cooling-devices";
+
+		display_fps: display-fps {
+			qcom,max-level = <16>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	limits_stat: limits-stat {
+		compatible = "qcom,limits-stat";
+		qcom,limits-stat-sensor-names = "aoss-0", "cpu-2-0-0", "cpu-2-0-1",
+						"cpu-2-0-2", "cpu-1-0-0", "cpu-1-0-1",
+						"cpu-1-1-0", "cpu-1-1-1", "aoss-1",
+						"cpuss-0-0", "cpuss-0-1", "cpu-1-2-0", "cpu-1-2-1",
+						"cpu-1-3-0", "cpu-1-3-1", "cpu-1-4-0", "cpu-1-4-1",
+						"cpu-0-0-0", "cpu-0-1-0", "aoss-2", "camera-0",
+						"camera-1", "video", "ddr-0", "gpu-0", "gpu-1",
+						"gpu-2", "gpu-3", "gpu-4", "gpu-5", "nsphvx-0",
+						"nsphvx-1", "nsphmx-0", "nsphmx-1", "aoss-3",
+						"mdmss-0", "mdmss-1", "mdmss-2", "mdmss-3";
+	};
+};
+
+#include "sun-thermal-modem.dtsi"
+
+&thermal_zones {
+	aoss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 0>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	cpu-2-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 1>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg0: cpu7-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu7_emerg0_1: cpu7-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu200_cdev {
+				trip = <&cpu7_emerg0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+
+			cpu200_cdev1 {
+				trip = <&cpu7_emerg0_1>;
+				cooling-device = <&cpu7_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-2-0-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 2>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg1: cpu7-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu7_emerg1_1: cpu7-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu201_cdev {
+				trip = <&cpu7_emerg1>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+
+			cpu201_cdev1 {
+				trip = <&cpu7_emerg1_1>;
+				cooling-device = <&cpu7_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-2-0-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 3>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu7_emerg2: cpu7-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu7_emerg2_1: cpu7-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu202_cdev {
+				trip = <&cpu7_emerg2>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+
+			cpu202_cdev1 {
+				trip = <&cpu7_emerg2_1>;
+				cooling-device = <&cpu7_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu2_emerg0: cpu2-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu2_emerg0_1: cpu2-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu100_cdev {
+				trip = <&cpu2_emerg0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			cpu100_cdev1 {
+				trip = <&cpu2_emerg0_1>;
+				cooling-device = <&cpu2_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-0-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 5>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu2_emerg1: cpu2-emerg1-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu2_emerg1_1: cpu2-emerg1-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu101_cdev {
+				trip = <&cpu2_emerg1>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			cpu101_cdev1 {
+				trip = <&cpu2_emerg1_1>;
+				cooling-device = <&cpu2_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-1-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 6>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu3_emerg0: cpu3-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu3_emerg0_1: cpu3-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu110_cdev {
+				trip = <&cpu3_emerg0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			cpu110_cdev1 {
+				trip = <&cpu3_emerg0_1>;
+				cooling-device = <&cpu3_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-1-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu3_emerg1: cpu3-emerg1-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu3_emerg1_1: cpu3-emerg1-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu111_cdev {
+				trip = <&cpu3_emerg1>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			cpu111_cdev1 {
+				trip = <&cpu3_emerg1_1>;
+				cooling-device = <&cpu3_hotplug 1 1>;
+			};
+		};
+	};
+
+	aoss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 0>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	cpuss-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 1>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	cpuss-0-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 2>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	cpu-1-2-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu4_emerg0: cpu4-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu4_emerg0_1: cpu4-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu120_cdev {
+				trip = <&cpu4_emerg0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			cpu120_cdev1 {
+				trip = <&cpu4_emerg0_1>;
+				cooling-device = <&cpu4_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-2-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 4>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu4_emerg1: cpu4-emerg1-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu4_emerg1_1: cpu4-emerg1-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu121_cdev {
+				trip = <&cpu4_emerg1>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			cpu121_cdev1 {
+				trip = <&cpu4_emerg1_1>;
+				cooling-device = <&cpu4_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 5>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu5_emerg0: cpu5-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu5_emerg0_1: cpu5-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point4 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu130_cdev {
+				trip = <&cpu5_emerg0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			cpu130_cdev1 {
+				trip = <&cpu5_emerg0_1>;
+				cooling-device = <&cpu5_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 6>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu5_emerg1: cpu5-emerg1-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu5_emerg1_1: cpu5-emerg1-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu131_cdev {
+				trip = <&cpu5_emerg1>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			cpu131_cdev1 {
+				trip = <&cpu5_emerg1_1>;
+				cooling-device = <&cpu5_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-4-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 7>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu6_emerg0: cpu6-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu6_emerg0_1: cpu6-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu140_cdev {
+				trip = <&cpu6_emerg0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			cpu140_cdev1 {
+				trip = <&cpu6_emerg0_1>;
+				cooling-device = <&cpu6_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-1-4-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 8>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu6_emerg1: cpu6-emerg1-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu6_emerg1_1: cpu6-emerg1-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu141_cdev {
+				trip = <&cpu6_emerg1>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			cpu141_cdev1 {
+				trip = <&cpu6_emerg1_1>;
+				cooling-device = <&cpu6_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-0-0-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 9>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu0_emerg0: cpu0-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu0_emerg0_1: cpu0-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu000_cdev {
+				trip = <&cpu0_emerg0>;
+				cooling-device = <&cpu0_pause 1 1>;
+			};
+
+			cpu000_cdev1 {
+				trip = <&cpu0_emerg0_1>;
+				cooling-device = <&cpu0_hotplug 1 1>;
+			};
+		};
+	};
+
+	cpu-0-1-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 10>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu1_emerg0: cpu1-emerg0-cfg {
+				temperature = <118000>;
+				hysteresis = <8000>;
+				type = "passive";
+			};
+
+			cpu1_emerg0_1: cpu1-emerg0-1-cfg {
+				temperature = <120000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			cpu010_cdev {
+				trip = <&cpu1_emerg0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			cpu010_cdev1 {
+				trip = <&cpu1_emerg0_1>;
+				cooling-device = <&cpu1_hotplug 1 1>;
+			};
+		};
+	};
+
+	aoss-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 0>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	camera-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 1>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	camera-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 2>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	video {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 3>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+
+		};
+	};
+
+	ddr-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 4>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 5>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu0_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 6>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu1_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 7>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu2_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 8>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu3_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 9>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu4_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	gpu-5 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 10>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			gpu5_tj_cfg: tj_cfg {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	nsphvx-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 11>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	nsphvx-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 12>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	nsphmx-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 13>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	nsphmx-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens2 14>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point2 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	aoss-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 0>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+	};
+
+	mdmss-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 1>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss0_config0: mdmss0-config0 {
+				temperature = <102000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			mdmss0_config1: mdmss0-config1 {
+				temperature = <105000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_nr_scg_dsc 100 100>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss0_config0>;
+				cooling-device = <&modem_nr_dsc 10 10>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss0_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss0_config1>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 2>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss1_config0: mdmss1-config0 {
+				temperature = <102000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			mdmss1_config1: mdmss1-config1 {
+				temperature = <105000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_nr_scg_dsc 100 100>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss1_config0>;
+				cooling-device = <&modem_nr_dsc 10 10>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss1_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss1_config1>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 3>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss2_config0: mdmss2-config0 {
+				temperature = <102000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			mdmss2_config1: mdmss2-config1 {
+				temperature = <105000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_nr_scg_dsc 100 100>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss2_config0>;
+				cooling-device = <&modem_nr_dsc 10 10>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss2_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss2_config1>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+
+	mdmss-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens3 4>;
+
+		trips {
+			trip-point0 {
+				temperature = <135000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdmss3_config0: mdmss3-config0 {
+				temperature = <102000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			mdmss3_config1: mdmss3-config1 {
+				temperature = <105000>;
+				hysteresis = <3000>;
+				type = "passive";
+			};
+
+			trip-point1 {
+				temperature = <125000>;
+				hysteresis = <0>;
+				type = "hot";
+			};
+		};
+
+		cooling-maps {
+			lte_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_lte_dsc 8 8>;
+			};
+
+			nr_scg_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_nr_scg_dsc 100 100>;
+			};
+
+			nr_cdev0 {
+				trip = <&mdmss3_config0>;
+				cooling-device = <&modem_nr_dsc 10 10>;
+			};
+
+			lte_cdev2 {
+				trip = <&mdmss3_config1>;
+				cooling-device = <&modem_lte_dsc 255 255>;
+			};
+
+			nr_cdev2 {
+				trip = <&mdmss3_config1>;
+				cooling-device = <&modem_nr_dsc 255 255>;
+			};
+		};
+	};
+};
diff --git a/qcom/tuna-vm.dtsi b/qcom/tuna-vm.dtsi
index 830368e7..b2f4335d 100644
--- a/qcom/tuna-vm.dtsi
+++ b/qcom/tuna-vm.dtsi
@@ -187,6 +187,19 @@
 				allocate-base;
 			};
 
+			gpiomem0 {
+				vdevice-type = "iomem";
+				patch = "/soc/tlmm-vm-mem-access";
+				push-compatible = "qcom,tlmm-vm-mem-access";
+				peer-default;
+				memory {
+					qcom,label = <0x8>;
+					qcom,mem-info-tag = <0x3>;
+					allocate-base;
+				};
+			};
+
+
 		};
 	};
 
@@ -216,6 +229,73 @@
 		wakeup-source;
 	};
 
+	vm_tlmm_irq: vm-tlmm-irq@0 {
+		compatible = "qcom,tlmm-vm-irq";
+		reg = <0x0 0x0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,tuna-vm-tlmm";
+		reg = <0x0F000000 0x1000000>;
+		interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		/* Valid pins */
+		gpios = /bits/ 16 <86 87 98 97 16 17 18 19 161 162 100 44 45 46 47 88 14 126 77 78 189 176>;
+	};
+
+	tlmm-vm-mem-access {
+		compatible = "qcom,tlmm-vm-mem-access";
+		tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
+					 &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
+					 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
+					 &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
+	};
+
+	tlmm-vm-test {
+		compatible = "qcom,tlmm-vm-test";
+		pinctrl-names = "active", "sleep";
+		pinctrl-0 = <&qupv3_se1_7i2c_active>;
+		pinctrl-1 = <&qupv3_se1_7i2c_sleep>;
+		tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
+					 &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
+					 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
+					 &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
+	};
+
+	pinctrl@f000000 {
+		qupv3_se1_7i2c_pins: qupv3_se1_7i2c_pins {
+			qupv3_se1_7i2c_active: qupv3_se1_7i2c_active {
+				mux {
+					pins = "gpio44";
+					function = "qup2_se7_l0";
+				};
+
+				config {
+					pins = "gpio44";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se1_7i2c_sleep: qupv3_se1_7i2c_sleep {
+				mux {
+					pins = "gpio44";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio44";
+					drive-strength = <2>;
+				};
+			};
+		};
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index ede3e8d1..1a106540 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -36,12 +36,14 @@
 	};
 
 	chosen: chosen {
-		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops";
+		bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 pcie_ports=compat irqaffinity=0-1 printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 ftrace_dump_on_oops cpufreq.default_governor=performance";
 		stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
 	};
 
 	reserved_memory: reserved-memory {};
 
+	ddr-regions { };
+
 	firmware: firmware {
 		qcom_scm: qcom_scm {};
 	};
@@ -91,6 +93,8 @@
 			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
 			power-domains = <&CPU_PD0>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_0>;
 			capacity-dmips-mhz = <1024>;
@@ -115,6 +119,8 @@
 			cpu-idle-states = <&GOLD_OFF_CL0 &GOLD_RAIL_OFF_CL0>;
 			power-domains = <&CPU_PD1>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_1>;
 			capacity-dmips-mhz = <1024>;
@@ -135,9 +141,11 @@
 			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
 			power-domains = <&CPU_PD2>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 3>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_2>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_2: l2-cache {
 			      compatible = "cache";
@@ -154,9 +162,11 @@
 			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
 			power-domains = <&CPU_PD3>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 3>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_3>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_3: l2-cache {
 			      compatible = "cache";
@@ -173,9 +183,11 @@
 			cpu-idle-states = <&GOLD_OFF_CL1 &GOLD_RAIL_OFF_CL1>;
 			power-domains = <&CPU_PD4>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 3>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_4>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_4: l2-cache {
 			      compatible = "cache";
@@ -192,9 +204,11 @@
 			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
 			power-domains = <&CPU_PD5>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_5>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_5: l2-cache {
 			      compatible = "cache";
@@ -211,9 +225,11 @@
 			cpu-idle-states = <&GOLD_OFF_CL2 &GOLD_RAIL_OFF_CL2>;
 			power-domains = <&CPU_PD6>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_6>;
-			capacity-dmips-mhz = <1024>;
+			capacity-dmips-mhz = <1035>;
 			dynamic-power-coefficient = <121>;
 			L2_6: l2-cache {
 			      compatible = "cache";
@@ -230,9 +246,11 @@
 			cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>;
 			power-domains = <&CPU_PD7>;
 			power-domain-names = "psci";
+			qcom,freq-domain = <&cpufreq_hw 2>;
+			#cooling-cells = <2>;
 			cpu-release-addr = <0x0 0xE3940000>;
 			next-level-cache = <&L2_7>;
-			capacity-dmips-mhz = <1300>;
+			capacity-dmips-mhz = <1178>;
 			dynamic-power-coefficient = <295>;
 			L2_7: l2-cache {
 			      compatible = "cache";
@@ -406,6 +424,7 @@
 #include "msm-arm-smmu-tuna.dtsi"
 #include "tuna-dma-heaps.dtsi"
 #include "tuna-vm-dma-heaps.dtsi"
+#include "tuna-pcie.dtsi"
 
 &reserved_memory {
 	#address-cells = <2>;
@@ -521,15 +540,27 @@
 		};
 	};
 
+	msm_gpu: qcom,kgsl-3d0@3d00000 { };
+
 	intc: interrupt-controller@17100000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
 		interrupt-controller;
+		ranges;
 		#redistributor-regions = <1>;
 		redistributor-stride = <0x0 0x40000>;
 		reg = <0x17100000 0x10000>,	/* GICD */
 		      <0x17180000 0x200000>;	/* GICR * 8 */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		gic_its: msi-controller@0x17140000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x17140000 0x20000>;
+		};
 	};
 
 	qcom,hdcp {
@@ -647,6 +678,17 @@
 			apps_bcm_voter: bcm_voter {
 				compatible = "qcom,bcm-voter";
 			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,tuna-rpmh-clk";
+				#clock-cells = <1>;
+			};
+
+			dcvs_fp: qcom,dcvs-fp {
+				compatible = "qcom,dcvs-fp";
+				qcom,ddr-bcm-name = "MC4";
+				qcom,llcc-bcm-name = "SH5";
+			};
 		};
 	};
 
@@ -1017,6 +1059,12 @@
 		};
 	};
 
+	sys-pm-vx@c320000 {
+		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-tuna";
+		reg = <0xc320000 0x400>;
+		qcom,qmp = <&aoss_qmp>;
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,tuna-tlmm";
 		reg = <0x0f000000 0x1000000>;
@@ -1029,6 +1077,28 @@
 		qcom,gpios-reserved = <54 4 5 6 7 82 83 111 112>;
 	};
 
+	tlmm-vm-mem-access {
+		compatible = "qcom,tlmm-vm-mem-access";
+		qcom,master;
+		tuivm {
+			qcom,label = <0x08>;
+			qcom,vmid = <45>;
+			tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
+					 &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
+					 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
+					 &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
+		};
+	};
+
+	tlmm-vm-test {
+		compatible = "qcom,tlmm-vm-test";
+		qcom,master;
+		tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 98 0 &tlmm 97 0 &tlmm 16 0 &tlmm 17 0
+					 &tlmm 18 0 &tlmm 19 0 &tlmm 161 0 &tlmm 162 0 &tlmm 100 0 &tlmm 44 0
+					 &tlmm 45 0 &tlmm 46 0 &tlmm 47 0 &tlmm 88 0 &tlmm 14 0 &tlmm 126 0
+					 &tlmm 77 &tlmm 78 &tlmm 189 0 &tlmm 176 0>;
+	};
+
 	slimbam: bamdma@6c04000 {
 		compatible = "qcom,bam-v1.7.0";
 		reg = <0x6c04000 0x20000>, <0x6c8f000 0x1000>;
@@ -1383,6 +1453,15 @@
 
 	};
 
+	qfprom: qfprom@221c8000 {
+		compatible = "qcom,tuna-qfprom", "qcom,qfprom";
+		reg = <0x221c8000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+	};
+
 	clocks {
 		xo_board: xo_board {
 			compatible = "fixed-clock";
@@ -1434,13 +1513,6 @@
 		};
 	};
 
-	rpmhcc: clock-controller {
-		compatible = "fixed-clock";
-		clock-output-names = "rpmh_clocks";
-		clock-frequency = <19200000>;
-		#clock-cells = <1>;
-	};
-
 	cambistmclkcc: clock-controller@1760000 {
 		compatible = "qcom,tuna-cambistmclkcc", "syscon";
 		reg = <0x1760000 0x6000>;
@@ -1456,6 +1528,54 @@
 		#reset-cells = <1>;
 	};
 
+	cpuss-sleep-stats@17800054 {
+		compatible = "qcom,cpuss-sleep-stats";
+		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
+		      <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
+		      <0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>,
+		      <0x178c0000 0x10000>;
+		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
+			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
+			    "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
+			    "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
+			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
+		num-cpus = <8>;
+	};
+
+	sram@c3f0000 {
+		compatible = "qcom,rpmh-stats-v4";
+		reg = <0x0c3f0000 0x3ff>;
+		qcom,qmp = <&aoss_qmp>;
+		ss-name = "modem", "wpss", "adsp", "adsp_island",
+			  "cdsp", "apss";
+	};
+
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-epss";
+		reg = <0x17D91000 0x1000>, <0x17D92000 0x1000>,
+		      <0x17D93000 0x1000>, <0x17D94000 0x1000>;
+		reg-names = "freq-domain0", "freq-domain1",
+			    "freq-domain2", "freq-domain3";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+		clock-names = "xo", "alternate";
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dcvsh0_int",
+				  "dcvsh1_int",
+				  "dcvsh2_int",
+				  "dcvsh3_int";
+		#freq-domain-cells = <1>;
+	};
+
+	qcom,cpufreq-hw-debug {
+		compatible = "qcom,cpufreq-hw-epss-debug";
+		qcom,freq-hw-domain = <&cpufreq_hw 0>,
+				      <&cpufreq_hw 1>,
+				      <&cpufreq_hw 2>,
+				      <&cpufreq_hw 3>;
+	};
 
 	cam_crm: syscon@adcd600 {
 		compatible = "syscon";
@@ -2443,8 +2563,6 @@
 	};
 
 	cpucp: qcom,cpucp@17400000 {
-		#address-cells = <2>;
-		#size-cells = <2>;
 		compatible = "qcom,cpucp";
 		reg =   <0x17d90000 0x2000>,
 			<0x17400000 0x10>;
@@ -2485,10 +2603,382 @@
 		compatible = "qcom,cpufreq-stats-v2";
 	};
 
+	llcc_pmu: llcc-pmu@24095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x24095000 0x300>;
+		reg-names = "lagg-base";
+	};
 
+	qcom_pmu: qcom,pmu {
+		compatible = "qcom,pmu";
+		qcom,long-counter;
+		qcom,pmu-events-tbl =
+			< 0x0008 0xFF 0x02 0xFF >,
+			< 0x0011 0xFF 0x01 0xFF >,
+			< 0x0017 0xFF 0xFF 0xFF >,
+			< 0x0037 0xFF 0xFF 0xFF >,
+			< 0x1000 0xFF 0xFF 0xFF >;
+	};
+
+	ddr_freq_table: ddr-freq-table {
+		qcom,freq-tbl =
+			<  547000 >,
+			< 1353600 >,
+			< 1555200 >,
+			< 1708000 >,
+			< 2092800 >,
+			< 2736000 >,
+			< 3187200 >,
+			< 3686400 >,
+			< 4224000 >,
+			< 4761600 >;
+	};
+
+	llcc_freq_table: llcc-freq-table {
+		qcom,freq-tbl =
+			<  350000 >,
+			<  533000 >,
+			<  600000 >,
+			<  806000 >,
+			<  933000 >,
+			< 1066000 >,
+			< 1211200 >;
+	};
+
+	ddrqos_freq_table: ddrqos-freq-table {
+		qcom,freq-tbl =
+			< 0 >,
+			< 1 >;
+	};
+
+	qcom_dcvs: qcom,dcvs {
+		compatible = "qcom,dcvs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom_l3_dcvs_hw: l3 {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <2>;
+			qcom,bus-width = <32>;
+			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
+			reg-names = "l3-base", "l3tbl-base";
+
+			l3_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				qcom,shared-offset = <0x0090>;
+			};
+		};
+
+		qcom_ddr_dcvs_hw: ddr {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <0>;
+			qcom,bus-width = <4>;
+			qcom,freq-tbl = <&ddr_freq_table>;
+
+			ddr_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+
+			ddr_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_llcc_dcvs_hw: llcc {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <1>;
+			qcom,bus-width = <16>;
+			qcom,freq-tbl = <&llcc_freq_table>;
+
+			llcc_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&gem_noc MASTER_APPSS_PROC
+						 &gem_noc SLAVE_LLCC>;
+			};
+
+			llcc_dcvs_fp: fp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <1>;
+				qcom,fp-voter = <&dcvs_fp>;
+			};
+		};
+
+		qcom_ddrqos_dcvs_hw: ddrqos {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <3>;
+			qcom,bus-width = <1>;
+			qcom,freq-tbl = <&ddrqos_freq_table>;
+
+			ddrqos_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+		};
+	};
+
+	qcom_memlat: qcom,memlat {
+		compatible = "qcom,memlat";
+
+		ddr {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+			qcom,sampling-path = <&ddr_dcvs_fp>;
+			qcom,miss-ev = <0x1000>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1075200  547000 >,
+					< 1401600 1555000 >,
+					< 2016000 2092000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
+				qcom,cpufreq-memfreq-tbl =
+					<  633600  547000 >,
+					<  940800 1555000 >,
+					< 1190400 1708000 >,
+					< 1401600 2092000 >,
+					< 1824000 2736000 >,
+					< 2073600 3187200 >,
+					< 2803200 3686400 >,
+					< 2918400 4224000 >,
+					< 3014400 4700000 >;
+				qcom,sampling-enabled;
+			};
+
+			prime {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  633600  547000 >,
+					<  960000 1555000 >,
+					< 1228800 1708000 >,
+					< 1478400 2092000 >,
+					< 2169600 3187200 >,
+					< 2956800 3686400 >,
+					< 3187200 4224000 >,
+					< 3206400 4700000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2073600  547000 >,
+					< 3187200 2092000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+
+			prime-latfloor {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2169600  547000 >,
+					< 2956800 2092000 >,
+					< 3206400 4224000 >;
+				qcom,sampling-enabled;
+			};
+		};
+
+		llcc {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+			qcom,sampling-path = <&llcc_dcvs_fp>;
+			qcom,miss-ev = <0x37>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1>;
+				qcom,cpufreq-memfreq-tbl =
+					<  883200  350000 >,
+					< 1401600  533000 >,
+					< 2016000  600000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  633600  350000 >,
+					< 1190400  533000 >,
+					< 1401600  600000 >,
+					< 1824000  806000 >,
+					< 2803200  933000 >,
+					< 2918400 1066000 >,
+					< 3014400 1211000 >;
+				qcom,sampling-enabled;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2073600  350000 >,
+					< 3014400  600000 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		l3 {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_l3_dcvs_hw>;
+			qcom,sampling-path = <&l3_dcvs_sp>;
+			qcom,miss-ev = <0x17>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1>;
+				qcom,cpufreq-memfreq-tbl =
+					<  364800  364800 >,
+					<  614400  518400 >,
+					<  748800  614400 >,
+					<  883200  806400 >,
+					<  979200  902400 >,
+					< 1075200  998400 >,
+					< 1286400 1209600 >,
+					< 1401600 1344000 >,
+					< 1632000 1497600 >,
+					< 1785600 1593600 >,
+					< 2016000 1804800 >;
+				qcom,sampling-enabled;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
+				qcom,cpufreq-memfreq-tbl =
+					<  480000  364800 >,
+					<  633600  518400 >,
+					<  940800  614400 >,
+					< 1190400  902400 >,
+					< 1401600  998400 >,
+					< 1632000 1209600 >,
+					< 2073600 1344000 >,
+					< 2438400 1497600 >,
+					< 2803200 1593600 >,
+					< 3014400 1804800 >;
+				qcom,sampling-enabled;
+			};
+
+			prime {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					<  480000  364800 >,
+					<  633600  518400 >,
+					<  940800  614400 >,
+					< 1228800  902400 >,
+					< 1478400 1209600 >,
+					< 1920000 1344000 >,
+					< 2169600 1497600 >,
+					< 2515200 1593600 >,
+					< 3206400 1804800 >;
+				qcom,sampling-enabled;
+			};
+
+			prime-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1920000  364800 >,
+					< 2512200 1209600 >,
+					< 3206400 1804800 >;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+			};
+		};
+
+		ddrqos {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
+			qcom,sampling-path = <&ddrqos_dcvs_sp>;
+			qcom,miss-ev = <0x1000>;
+
+			ddrqos_gold_lat: gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2073600 0 >,
+					< 3014400 1 >;
+				qcom,sampling-enabled;
+			};
+
+			ddrqos_prime_lat: prime {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 1478400 0 >,
+					< 3206400 1 >;
+				qcom,sampling-enabled;
+			};
+
+			ddrqos_prime_latfloor: prime-latfloor {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,cpufreq-memfreq-tbl =
+					< 2169600 0 >,
+					< 3206400 1 >;
+				qcom,sampling-enabled;
+			};
+		};
+	};
+
+	qcom_llcc_l3_vote: qcom,llcc-l3-vote {
+		qcom,target-dev = <&qcom_l3_dcvs_hw>;
+		qcom,secondary-map =
+			<  350000  364800 >,
+			<  533000  518400 >,
+			<  600000  614400 >,
+			<  806000  806400 >,
+			<  933000  902400 >,
+			< 1066000  998400 >,
+			< 1211200 1209600 >;
+	};
+
+	bwmon_llcc: qcom,bwmon-llcc@240B7300 {
+		compatible = "qcom,bwmon4";
+		reg = <0x240B7400 0x300>, <0x240B7300 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+		qcom,second-vote = <&qcom_llcc_l3_vote>;
+	};
+
+	bwmon_ddr: qcom,bwmon-ddr@24091000 {
+		compatible = "qcom,bwmon5";
+		reg = <0x24091000 0x1000>;
+		reg-names = "base";
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+	};
 };
 
 #include "tuna-gdsc.dtsi"
+#include "ipcc-test-no-slpi.dtsi"
 
 &cam_cc_ipe_0_gdsc {
 	compatible = "qcom,gdsc";
@@ -2517,6 +3007,8 @@
 
 &cam_cc_titan_top_gdsc {
 	compatible = "qcom,gdsc";
+	interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+	interconnect-names = "mmnoc";
 	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 	status = "ok";
 };
@@ -2675,12 +3167,13 @@
 };
 
 #include "tuna-pinctrl.dtsi"
-#include "tuna-stub-regulators.dtsi"
+#include "tuna-regulators.dtsi"
 #include "tuna-usb.dtsi"
 #include "tuna-qupv3.dtsi"
 #include "msm-rdbg.dtsi"
 #include "tuna-pmic-overlay.dtsi"
 #include "tuna-walt.dtsi"
+#include "tuna-thermal.dtsi"
 
 &qupv3_se7_2uart {
 	status = "ok";