ARM: dts: msm: add initial dsi display nodes for Kera
Add initial dsi display nodes for Kera. Change-Id: I09194c34f8ac1ec6d606879267b1732a72c0cd4e Signed-off-by: Abhinav Saurabh <quic_abhisaur@quicinc.com> Signed-off-by: lnxdisplay <lnxdisplay@localhost>
This commit is contained in:
Abhinav Saurabh
committed by
lnxdisplay
lnxdisplay
parent
4a86f982ac
commit
984fda4d7d
149
display/kera-sde-common.dtsi
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149
display/kera-sde-common.dtsi
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@@ -0,0 +1,149 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@ae00000 {
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};
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mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
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compatible = "qcom,dsi-ctrl-hw-v2.9";
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label = "dsi-ctrl-0";
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cell-index = <0>;
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frame-threshold-time-us = <800>;
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reg = <0xae94000 0x1000>,
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<0xaf0f000 0x4>,
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<0x0ae36000 0x300>;
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reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1320000>;
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qcom,supply-enable-load = <16600>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
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compatible = "qcom,dsi-ctrl-hw-v2.9";
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label = "dsi-ctrl-1";
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cell-index = <1>;
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frame-threshold-time-us = <800>;
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reg = <0xae96000 0x1000>,
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<0xaf0f000 0x4>,
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<0x0ae37000 0x300>;
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reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <5 0>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1320000>;
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qcom,supply-enable-load = <16600>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
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compatible = "qcom,dsi-phy-v5.2";
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label = "dsi-phy-0";
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cell-index = <0>;
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#clock-cells = <1>;
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reg = <0xae95000 0xa00>,
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<0xae95500 0x400>,
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<0xae94200 0xa0>;
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reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
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pll-label = "dsi_pll_4nm";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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55 03
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55 00];
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qcom,platform-lane-config = [00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 8a 8a];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <950000>;
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qcom,supply-enable-load = <98000>;
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qcom,supply-disable-load = <96>;
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};
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};
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};
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mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
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compatible = "qcom,dsi-phy-v5.2";
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label = "dsi-phy-1";
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cell-index = <1>;
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#clock-cells = <1>;
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reg = <0xae97000 0xa00>,
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<0xae97500 0x400>,
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<0xae96200 0xa0>;
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reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
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pll-label = "dsi_pll_4nm";
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qcom,platform-strength-ctrl = [55 03
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55 03
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55 03
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55 03
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55 00];
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qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
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qcom,platform-lane-config = [00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 0a 0a
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00 00 8a 8a];
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <950000>;
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qcom,supply-enable-load = <98000>;
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qcom,supply-disable-load = <96>;
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};
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};
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};
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dsi_pll_codes_data:dsi_pll_codes {
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reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
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0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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label = "dsi_pll_codes";
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};
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};
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147
display/kera-sde-display.dtsi
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147
display/kera-sde-display.dtsi
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@@ -0,0 +1,147 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include "kera-sde-display-common.dtsi"
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&soc {
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};
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&sde_dsi {
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clocks = <&mdss_dsi_phy0 0>,
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<&mdss_dsi_phy0 1>,
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<&mdss_dsi_phy1 2>,
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<&mdss_dsi_phy1 3>,
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/*
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* Currently the dsi clock handles are under the dsi
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* controller DT node. As soon as the controller probe
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* finishes, the dispcc sync state can get called before
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* the dsi_display probe potentially disturbing the clock
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* votes for cont_splash use case. Hence we are no longer
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* protected by the component model in this case against the
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* disp cc sync state getting triggered after the dsi_ctrl
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* probe. To protect against this incorrect sync state trigger
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* add this dummy MDP clk vote handle to the dsi_display
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* DT node. Since the dsi_display driver does not parse
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* MDP clock nodes, no actual vote shall be added and this
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* change is done just to satisfy sync state requirements.
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*/
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1",
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"mdp_core_clk";
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vddio-supply = <&L8B>;
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vci-supply = <&L19B>;
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vdd-supply = <&L1G>;
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};
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&sde_dsi1 {
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clocks = <&mdss_dsi_phy0 0>,
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<&mdss_dsi_phy0 1>,
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<&mdss_dsi_phy1 2>,
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<&mdss_dsi_phy1 3>,
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/*
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* Currently the dsi clock handles are under the dsi
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* controller DT node. As soon as the controller probe
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* finishes, the dispcc sync state can get called before
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* the dsi_display probe potentially disturbing the clock
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* votes for cont_splash use case. Hence we are no longer
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* protected by the component model in this case against the
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* disp cc sync state getting triggered after the dsi_ctrl
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* probe. To protect against this incorrect sync state trigger
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* add this dummy MDP clk vote handle to the dsi_display
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* DT node. Since the dsi_display driver does not parse
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* MDP clock nodes, no actual vote shall be added and this
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* change is done just to satisfy sync state requirements.
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*/
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "pll_byte_clk0", "pll_dsi_clk0",
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"pll_byte_clk1", "pll_dsi_clk1",
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"mdp_core_clk";
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vddio-supply = <&L8B>;
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vci-supply = <&L19B>;
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vdd-supply = <&L1G>;
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};
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&mdss_mdp {
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connectors = <&sde_dsi &sde_dsi1>;
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};
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&dsi_vtdr6130_amoled_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@1 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@2 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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timing@3 {
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qcom,partial-update-enabled = "single_roi";
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qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
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};
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};
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};
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&dsi_vtdr6130_amoled_qsync_144hz_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 { /* WQHD 60FPS cmd vid mode*/
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qcom,panel-roi-alignment = <720 40 720 40 720 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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timing@2 { /* FHD 60FPS cmd mode*/
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qcom,panel-roi-alignment = <540 20 540 20 540 20>;
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qcom,partial-update-enabled = "single_roi";
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};
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timing@3 { /* HD 60FPS cmd mode*/
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qcom,panel-roi-alignment = <360 40 360 40 360 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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};
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};
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&dsi_sim_dsc_375_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_dsc_10b_cmd {
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qcom,ulps-enabled;
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};
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&dsi_dual_sim_cmd {
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qcom,ulps-enabled;
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};
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&dsi_dual_sim_dsc_375_cmd {
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qcom,ulps-enabled;
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};
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&dsi_sim_sec_hd_cmd {
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qcom,ulps-enabled;
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qcom,mdss-dsi-display-timings {
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timing@0 {
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qcom,panel-roi-alignment = <720 40 720 40 720 40>;
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qcom,partial-update-enabled = "single_roi";
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};
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};
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};
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14
display/kera-sde.dts
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14
display/kera-sde.dts
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@@ -0,0 +1,14 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include "kera-sde.dtsi"
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/ {
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qcom,msm-id = <686 0x10000>, <659 0x10000>;
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qcom,board-id = <0 0>;
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};
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58
display/kera-sde.dtsi
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58
display/kera-sde.dtsi
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@@ -0,0 +1,58 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include "kera-sde-common.dtsi"
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&soc {
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};
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&mdss_mdp {
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};
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&mdss_dsi0 {
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vdda-1p2-supply = <&L4B>;
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qcom,split-link-supported;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
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};
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&mdss_dsi1 {
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vdda-1p2-supply = <&L4B>;
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qcom,split-link-supported;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
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};
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&mdss_dsi_phy0 {
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vdda-0p9-supply = <&L2B>;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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pll_codes_region = <&dsi_pll_codes_data>;
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};
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&mdss_dsi_phy1 {
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vdda-0p9-supply = <&L2B>;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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pll_codes_region = <&dsi_pll_codes_data>;
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};
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