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ARM: dts: msm: add xo clock to sde_cesta node in sun target

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Add XO clock to sde_cesta node. This will help to vote
XO freq for cesta idle vote for mdp-clk.

Change-Id: I33b309ed9ac2d9013fee8f071c5f07938e651e5f
Signed-off-by: Spurthy Mutturaj <quic_smuttura@quicinc.com>
Signed-off-by: Sampurna Bolloju <quic_sampboll@quicinc.com>
This commit is contained in:
Spurthy Mutturaj
2024-08-29 10:38:33 -07:00
committed by V S Ganga VaraPrasad (VARA) Adabala
parent 46b41adcfe
commit 95aa5d8b14
1 changed files with 6 additions and 5 deletions
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11
display/sun-sde.dtsi
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@@ -226,12 +226,13 @@
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_XO_CLK_SRC>;
clock-names = "branch_clk", "core_clk";
clock-rate = <575000000 575000000>;
clock-max-rate = <575000000 575000000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>;
clock-names = "branch_clk", "core_clk","xo";
clock-rate = <575000000 575000000 19200000>;
clock-max-rate = <575000000 575000000 19200000>;
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>;
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,